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0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * NVEC: NVIDIA compliant embedded controller interface
0004  *
0005  * Copyright (C) 2011 The AC100 Kernel Team <ac100@lists.lauchpad.net>
0006  *
0007  * Authors:  Pierre-Hugues Husson <phhusson@free.fr>
0008  *           Ilya Petrov <ilya.muromec@gmail.com>
0009  *           Marc Dietrich <marvin24@gmx.de>
0010  *           Julian Andres Klode <jak@jak-linux.org>
0011  */
0012 
0013 #include <linux/kernel.h>
0014 #include <linux/module.h>
0015 #include <linux/atomic.h>
0016 #include <linux/clk.h>
0017 #include <linux/completion.h>
0018 #include <linux/delay.h>
0019 #include <linux/err.h>
0020 #include <linux/gpio/consumer.h>
0021 #include <linux/interrupt.h>
0022 #include <linux/io.h>
0023 #include <linux/irq.h>
0024 #include <linux/of.h>
0025 #include <linux/list.h>
0026 #include <linux/mfd/core.h>
0027 #include <linux/mutex.h>
0028 #include <linux/notifier.h>
0029 #include <linux/slab.h>
0030 #include <linux/spinlock.h>
0031 #include <linux/workqueue.h>
0032 
0033 #include "nvec.h"
0034 
0035 #define I2C_CNFG            0x00
0036 #define I2C_CNFG_PACKET_MODE_EN     BIT(10)
0037 #define I2C_CNFG_NEW_MASTER_SFM     BIT(11)
0038 #define I2C_CNFG_DEBOUNCE_CNT_SHIFT 12
0039 
0040 #define I2C_SL_CNFG     0x20
0041 #define I2C_SL_NEWSL        BIT(2)
0042 #define I2C_SL_NACK     BIT(1)
0043 #define I2C_SL_RESP     BIT(0)
0044 #define I2C_SL_IRQ      BIT(3)
0045 #define END_TRANS       BIT(4)
0046 #define RCVD            BIT(2)
0047 #define RNW         BIT(1)
0048 
0049 #define I2C_SL_RCVD     0x24
0050 #define I2C_SL_STATUS       0x28
0051 #define I2C_SL_ADDR1        0x2c
0052 #define I2C_SL_ADDR2        0x30
0053 #define I2C_SL_DELAY_COUNT  0x3c
0054 
0055 /**
0056  * enum nvec_msg_category - Message categories for nvec_msg_alloc()
0057  * @NVEC_MSG_RX: The message is an incoming message (from EC)
0058  * @NVEC_MSG_TX: The message is an outgoing message (to EC)
0059  */
0060 enum nvec_msg_category  {
0061     NVEC_MSG_RX,
0062     NVEC_MSG_TX,
0063 };
0064 
0065 enum nvec_sleep_subcmds {
0066     GLOBAL_EVENTS,
0067     AP_PWR_DOWN,
0068     AP_SUSPEND,
0069 };
0070 
0071 #define CNF_EVENT_REPORTING 0x01
0072 #define GET_FIRMWARE_VERSION 0x15
0073 #define LID_SWITCH BIT(1)
0074 #define PWR_BUTTON BIT(15)
0075 
0076 static struct nvec_chip *nvec_power_handle;
0077 
0078 static const struct mfd_cell nvec_devices[] = {
0079     {
0080         .name = "nvec-kbd",
0081     },
0082     {
0083         .name = "nvec-mouse",
0084     },
0085     {
0086         .name = "nvec-power",
0087         .id = 0,
0088     },
0089     {
0090         .name = "nvec-power",
0091         .id = 1,
0092     },
0093     {
0094         .name = "nvec-paz00",
0095     },
0096 };
0097 
0098 /**
0099  * nvec_register_notifier - Register a notifier with nvec
0100  * @nvec: A &struct nvec_chip
0101  * @nb: The notifier block to register
0102  * @events: Unused
0103  *
0104  * Registers a notifier with @nvec. The notifier will be added to an atomic
0105  * notifier chain that is called for all received messages except those that
0106  * correspond to a request initiated by nvec_write_sync().
0107  */
0108 int nvec_register_notifier(struct nvec_chip *nvec, struct notifier_block *nb,
0109                unsigned int events)
0110 {
0111     return atomic_notifier_chain_register(&nvec->notifier_list, nb);
0112 }
0113 EXPORT_SYMBOL_GPL(nvec_register_notifier);
0114 
0115 /**
0116  * nvec_unregister_notifier - Unregister a notifier with nvec
0117  * @nvec: A &struct nvec_chip
0118  * @nb: The notifier block to unregister
0119  *
0120  * Unregisters a notifier with @nvec. The notifier will be removed from the
0121  * atomic notifier chain.
0122  */
0123 int nvec_unregister_notifier(struct nvec_chip *nvec, struct notifier_block *nb)
0124 {
0125     return atomic_notifier_chain_unregister(&nvec->notifier_list, nb);
0126 }
0127 EXPORT_SYMBOL_GPL(nvec_unregister_notifier);
0128 
0129 /*
0130  * nvec_status_notifier - The final notifier
0131  *
0132  * Prints a message about control events not handled in the notifier
0133  * chain.
0134  */
0135 static int nvec_status_notifier(struct notifier_block *nb,
0136                 unsigned long event_type, void *data)
0137 {
0138     struct nvec_chip *nvec = container_of(nb, struct nvec_chip,
0139                         nvec_status_notifier);
0140     unsigned char *msg = data;
0141 
0142     if (event_type != NVEC_CNTL)
0143         return NOTIFY_DONE;
0144 
0145     dev_warn(nvec->dev, "unhandled msg type %ld\n", event_type);
0146     print_hex_dump(KERN_WARNING, "payload: ", DUMP_PREFIX_NONE, 16, 1,
0147                msg, msg[1] + 2, true);
0148 
0149     return NOTIFY_OK;
0150 }
0151 
0152 /**
0153  * nvec_msg_alloc:
0154  * @nvec: A &struct nvec_chip
0155  * @category: Pool category, see &enum nvec_msg_category
0156  *
0157  * Allocate a single &struct nvec_msg object from the message pool of
0158  * @nvec. The result shall be passed to nvec_msg_free() if no longer
0159  * used.
0160  *
0161  * Outgoing messages are placed in the upper 75% of the pool, keeping the
0162  * lower 25% available for RX buffers only. The reason is to prevent a
0163  * situation where all buffers are full and a message is thus endlessly
0164  * retried because the response could never be processed.
0165  */
0166 static struct nvec_msg *nvec_msg_alloc(struct nvec_chip *nvec,
0167                        enum nvec_msg_category category)
0168 {
0169     int i = (category == NVEC_MSG_TX) ? (NVEC_POOL_SIZE / 4) : 0;
0170 
0171     for (; i < NVEC_POOL_SIZE; i++) {
0172         if (atomic_xchg(&nvec->msg_pool[i].used, 1) == 0) {
0173             dev_vdbg(nvec->dev, "INFO: Allocate %i\n", i);
0174             return &nvec->msg_pool[i];
0175         }
0176     }
0177 
0178     dev_err(nvec->dev, "could not allocate %s buffer\n",
0179         (category == NVEC_MSG_TX) ? "TX" : "RX");
0180 
0181     return NULL;
0182 }
0183 
0184 /**
0185  * nvec_msg_free:
0186  * @nvec: A &struct nvec_chip
0187  * @msg:  A message (must be allocated by nvec_msg_alloc() and belong to @nvec)
0188  *
0189  * Free the given message
0190  */
0191 void nvec_msg_free(struct nvec_chip *nvec, struct nvec_msg *msg)
0192 {
0193     if (msg != &nvec->tx_scratch)
0194         dev_vdbg(nvec->dev, "INFO: Free %ti\n", msg - nvec->msg_pool);
0195     atomic_set(&msg->used, 0);
0196 }
0197 EXPORT_SYMBOL_GPL(nvec_msg_free);
0198 
0199 /**
0200  * nvec_msg_is_event - Return %true if @msg is an event
0201  * @msg: A message
0202  */
0203 static bool nvec_msg_is_event(struct nvec_msg *msg)
0204 {
0205     return msg->data[0] >> 7;
0206 }
0207 
0208 /**
0209  * nvec_msg_size - Get the size of a message
0210  * @msg: The message to get the size for
0211  *
0212  * This only works for received messages, not for outgoing messages.
0213  */
0214 static size_t nvec_msg_size(struct nvec_msg *msg)
0215 {
0216     bool is_event = nvec_msg_is_event(msg);
0217     int event_length = (msg->data[0] & 0x60) >> 5;
0218 
0219     /* for variable size, payload size in byte 1 + count (1) + cmd (1) */
0220     if (!is_event || event_length == NVEC_VAR_SIZE)
0221         return (msg->pos || msg->size) ? (msg->data[1] + 2) : 0;
0222     else if (event_length == NVEC_2BYTES)
0223         return 2;
0224     else if (event_length == NVEC_3BYTES)
0225         return 3;
0226     return 0;
0227 }
0228 
0229 /**
0230  * nvec_gpio_set_value - Set the GPIO value
0231  * @nvec: A &struct nvec_chip
0232  * @value: The value to write (0 or 1)
0233  *
0234  * Like gpio_set_value(), but generating debugging information
0235  */
0236 static void nvec_gpio_set_value(struct nvec_chip *nvec, int value)
0237 {
0238     dev_dbg(nvec->dev, "GPIO changed from %u to %u\n",
0239         gpiod_get_value(nvec->gpiod), value);
0240     gpiod_set_value(nvec->gpiod, value);
0241 }
0242 
0243 /**
0244  * nvec_write_async - Asynchronously write a message to NVEC
0245  * @nvec: An nvec_chip instance
0246  * @data: The message data, starting with the request type
0247  * @size: The size of @data
0248  *
0249  * Queue a single message to be transferred to the embedded controller
0250  * and return immediately.
0251  *
0252  * Returns: 0 on success, a negative error code on failure. If a failure
0253  * occurred, the nvec driver may print an error.
0254  */
0255 int nvec_write_async(struct nvec_chip *nvec, const unsigned char *data,
0256              short size)
0257 {
0258     struct nvec_msg *msg;
0259     unsigned long flags;
0260 
0261     msg = nvec_msg_alloc(nvec, NVEC_MSG_TX);
0262 
0263     if (!msg)
0264         return -ENOMEM;
0265 
0266     msg->data[0] = size;
0267     memcpy(msg->data + 1, data, size);
0268     msg->size = size + 1;
0269 
0270     spin_lock_irqsave(&nvec->tx_lock, flags);
0271     list_add_tail(&msg->node, &nvec->tx_data);
0272     spin_unlock_irqrestore(&nvec->tx_lock, flags);
0273 
0274     schedule_work(&nvec->tx_work);
0275 
0276     return 0;
0277 }
0278 EXPORT_SYMBOL(nvec_write_async);
0279 
0280 /**
0281  * nvec_write_sync - Write a message to nvec and read the response
0282  * @nvec: An &struct nvec_chip
0283  * @data: The data to write
0284  * @size: The size of @data
0285  * @msg:  The response message received
0286  *
0287  * This is similar to nvec_write_async(), but waits for the
0288  * request to be answered before returning. This function
0289  * uses a mutex and can thus not be called from e.g.
0290  * interrupt handlers.
0291  *
0292  * Returns: 0 on success, a negative error code on failure.
0293  * The response message is returned in @msg. Shall be freed
0294  * with nvec_msg_free() once no longer used.
0295  *
0296  */
0297 int nvec_write_sync(struct nvec_chip *nvec,
0298             const unsigned char *data, short size,
0299             struct nvec_msg **msg)
0300 {
0301     mutex_lock(&nvec->sync_write_mutex);
0302 
0303     *msg = NULL;
0304     nvec->sync_write_pending = (data[1] << 8) + data[0];
0305 
0306     if (nvec_write_async(nvec, data, size) < 0) {
0307         mutex_unlock(&nvec->sync_write_mutex);
0308         return -ENOMEM;
0309     }
0310 
0311     dev_dbg(nvec->dev, "nvec_sync_write: 0x%04x\n",
0312         nvec->sync_write_pending);
0313     if (!(wait_for_completion_timeout(&nvec->sync_write,
0314                       msecs_to_jiffies(2000)))) {
0315         dev_warn(nvec->dev,
0316              "timeout waiting for sync write to complete\n");
0317         mutex_unlock(&nvec->sync_write_mutex);
0318         return -ETIMEDOUT;
0319     }
0320 
0321     dev_dbg(nvec->dev, "nvec_sync_write: pong!\n");
0322 
0323     *msg = nvec->last_sync_msg;
0324 
0325     mutex_unlock(&nvec->sync_write_mutex);
0326 
0327     return 0;
0328 }
0329 EXPORT_SYMBOL(nvec_write_sync);
0330 
0331 /**
0332  * nvec_toggle_global_events - enables or disables global event reporting
0333  * @nvec: nvec handle
0334  * @state: true for enable, false for disable
0335  *
0336  * This switches on/off global event reports by the embedded controller.
0337  */
0338 static void nvec_toggle_global_events(struct nvec_chip *nvec, bool state)
0339 {
0340     unsigned char global_events[] = { NVEC_SLEEP, GLOBAL_EVENTS, state };
0341 
0342     nvec_write_async(nvec, global_events, 3);
0343 }
0344 
0345 /**
0346  * nvec_event_mask - fill the command string with event bitfield
0347  * @ev: points to event command string
0348  * @mask: bit to insert into the event mask
0349  *
0350  * Configure event command expects a 32 bit bitfield which describes
0351  * which events to enable. The bitfield has the following structure
0352  * (from highest byte to lowest):
0353  *  system state bits 7-0
0354  *  system state bits 15-8
0355  *  oem system state bits 7-0
0356  *  oem system state bits 15-8
0357  */
0358 static void nvec_event_mask(char *ev, u32 mask)
0359 {
0360     ev[3] = mask >> 16 & 0xff;
0361     ev[4] = mask >> 24 & 0xff;
0362     ev[5] = mask >> 0  & 0xff;
0363     ev[6] = mask >> 8  & 0xff;
0364 }
0365 
0366 /**
0367  * nvec_request_master - Process outgoing messages
0368  * @work: A &struct work_struct (the tx_worker member of &struct nvec_chip)
0369  *
0370  * Processes all outgoing requests by sending the request and awaiting the
0371  * response, then continuing with the next request. Once a request has a
0372  * matching response, it will be freed and removed from the list.
0373  */
0374 static void nvec_request_master(struct work_struct *work)
0375 {
0376     struct nvec_chip *nvec = container_of(work, struct nvec_chip, tx_work);
0377     unsigned long flags;
0378     long err;
0379     struct nvec_msg *msg;
0380 
0381     spin_lock_irqsave(&nvec->tx_lock, flags);
0382     while (!list_empty(&nvec->tx_data)) {
0383         msg = list_first_entry(&nvec->tx_data, struct nvec_msg, node);
0384         spin_unlock_irqrestore(&nvec->tx_lock, flags);
0385         nvec_gpio_set_value(nvec, 0);
0386         err = wait_for_completion_interruptible_timeout(&nvec->ec_transfer,
0387                                 msecs_to_jiffies(5000));
0388 
0389         if (err == 0) {
0390             dev_warn(nvec->dev, "timeout waiting for ec transfer\n");
0391             nvec_gpio_set_value(nvec, 1);
0392             msg->pos = 0;
0393         }
0394 
0395         spin_lock_irqsave(&nvec->tx_lock, flags);
0396 
0397         if (err > 0) {
0398             list_del_init(&msg->node);
0399             nvec_msg_free(nvec, msg);
0400         }
0401     }
0402     spin_unlock_irqrestore(&nvec->tx_lock, flags);
0403 }
0404 
0405 /**
0406  * parse_msg - Print some information and call the notifiers on an RX message
0407  * @nvec: A &struct nvec_chip
0408  * @msg: A message received by @nvec
0409  *
0410  * Paarse some pieces of the message and then call the chain of notifiers
0411  * registered via nvec_register_notifier.
0412  */
0413 static int parse_msg(struct nvec_chip *nvec, struct nvec_msg *msg)
0414 {
0415     if ((msg->data[0] & 1 << 7) == 0 && msg->data[3]) {
0416         dev_err(nvec->dev, "ec responded %*ph\n", 4, msg->data);
0417         return -EINVAL;
0418     }
0419 
0420     if ((msg->data[0] >> 7) == 1 && (msg->data[0] & 0x0f) == 5)
0421         print_hex_dump(KERN_WARNING, "ec system event ",
0422                    DUMP_PREFIX_NONE, 16, 1, msg->data,
0423                    msg->data[1] + 2, true);
0424 
0425     atomic_notifier_call_chain(&nvec->notifier_list, msg->data[0] & 0x8f,
0426                    msg->data);
0427 
0428     return 0;
0429 }
0430 
0431 /**
0432  * nvec_dispatch - Process messages received from the EC
0433  * @work: A &struct work_struct (the tx_worker member of &struct nvec_chip)
0434  *
0435  * Process messages previously received from the EC and put into the RX
0436  * queue of the &struct nvec_chip instance associated with @work.
0437  */
0438 static void nvec_dispatch(struct work_struct *work)
0439 {
0440     struct nvec_chip *nvec = container_of(work, struct nvec_chip, rx_work);
0441     unsigned long flags;
0442     struct nvec_msg *msg;
0443 
0444     spin_lock_irqsave(&nvec->rx_lock, flags);
0445     while (!list_empty(&nvec->rx_data)) {
0446         msg = list_first_entry(&nvec->rx_data, struct nvec_msg, node);
0447         list_del_init(&msg->node);
0448         spin_unlock_irqrestore(&nvec->rx_lock, flags);
0449 
0450         if (nvec->sync_write_pending ==
0451               (msg->data[2] << 8) + msg->data[0]) {
0452             dev_dbg(nvec->dev, "sync write completed!\n");
0453             nvec->sync_write_pending = 0;
0454             nvec->last_sync_msg = msg;
0455             complete(&nvec->sync_write);
0456         } else {
0457             parse_msg(nvec, msg);
0458             nvec_msg_free(nvec, msg);
0459         }
0460         spin_lock_irqsave(&nvec->rx_lock, flags);
0461     }
0462     spin_unlock_irqrestore(&nvec->rx_lock, flags);
0463 }
0464 
0465 /**
0466  * nvec_tx_completed - Complete the current transfer
0467  * @nvec: A &struct nvec_chip
0468  *
0469  * This is called when we have received an END_TRANS on a TX transfer.
0470  */
0471 static void nvec_tx_completed(struct nvec_chip *nvec)
0472 {
0473     /* We got an END_TRANS, let's skip this, maybe there's an event */
0474     if (nvec->tx->pos != nvec->tx->size) {
0475         dev_err(nvec->dev, "premature END_TRANS, resending\n");
0476         nvec->tx->pos = 0;
0477         nvec_gpio_set_value(nvec, 0);
0478     } else {
0479         nvec->state = 0;
0480     }
0481 }
0482 
0483 /**
0484  * nvec_rx_completed - Complete the current transfer
0485  * @nvec: A &struct nvec_chip
0486  *
0487  * This is called when we have received an END_TRANS on a RX transfer.
0488  */
0489 static void nvec_rx_completed(struct nvec_chip *nvec)
0490 {
0491     if (nvec->rx->pos != nvec_msg_size(nvec->rx)) {
0492         dev_err(nvec->dev, "RX incomplete: Expected %u bytes, got %u\n",
0493             (uint)nvec_msg_size(nvec->rx),
0494             (uint)nvec->rx->pos);
0495 
0496         nvec_msg_free(nvec, nvec->rx);
0497         nvec->state = 0;
0498 
0499         /* Battery quirk - Often incomplete, and likes to crash */
0500         if (nvec->rx->data[0] == NVEC_BAT)
0501             complete(&nvec->ec_transfer);
0502 
0503         return;
0504     }
0505 
0506     spin_lock(&nvec->rx_lock);
0507 
0508     /*
0509      * Add the received data to the work list and move the ring buffer
0510      * pointer to the next entry.
0511      */
0512     list_add_tail(&nvec->rx->node, &nvec->rx_data);
0513 
0514     spin_unlock(&nvec->rx_lock);
0515 
0516     nvec->state = 0;
0517 
0518     if (!nvec_msg_is_event(nvec->rx))
0519         complete(&nvec->ec_transfer);
0520 
0521     schedule_work(&nvec->rx_work);
0522 }
0523 
0524 /**
0525  * nvec_invalid_flags - Send an error message about invalid flags and jump
0526  * @nvec: The nvec device
0527  * @status: The status flags
0528  * @reset: Whether we shall jump to state 0.
0529  */
0530 static void nvec_invalid_flags(struct nvec_chip *nvec, unsigned int status,
0531                    bool reset)
0532 {
0533     dev_err(nvec->dev, "unexpected status flags 0x%02x during state %i\n",
0534         status, nvec->state);
0535     if (reset)
0536         nvec->state = 0;
0537 }
0538 
0539 /**
0540  * nvec_tx_set - Set the message to transfer (nvec->tx)
0541  * @nvec: A &struct nvec_chip
0542  *
0543  * Gets the first entry from the tx_data list of @nvec and sets the
0544  * tx member to it. If the tx_data list is empty, this uses the
0545  * tx_scratch message to send a no operation message.
0546  */
0547 static void nvec_tx_set(struct nvec_chip *nvec)
0548 {
0549     spin_lock(&nvec->tx_lock);
0550     if (list_empty(&nvec->tx_data)) {
0551         dev_err(nvec->dev, "empty tx - sending no-op\n");
0552         memcpy(nvec->tx_scratch.data, "\x02\x07\x02", 3);
0553         nvec->tx_scratch.size = 3;
0554         nvec->tx_scratch.pos = 0;
0555         nvec->tx = &nvec->tx_scratch;
0556         list_add_tail(&nvec->tx->node, &nvec->tx_data);
0557     } else {
0558         nvec->tx = list_first_entry(&nvec->tx_data, struct nvec_msg,
0559                         node);
0560         nvec->tx->pos = 0;
0561     }
0562     spin_unlock(&nvec->tx_lock);
0563 
0564     dev_dbg(nvec->dev, "Sending message of length %u, command 0x%x\n",
0565         (uint)nvec->tx->size, nvec->tx->data[1]);
0566 }
0567 
0568 /**
0569  * nvec_interrupt - Interrupt handler
0570  * @irq: The IRQ
0571  * @dev: The nvec device
0572  *
0573  * Interrupt handler that fills our RX buffers and empties our TX
0574  * buffers. This uses a finite state machine with ridiculous amounts
0575  * of error checking, in order to be fairly reliable.
0576  */
0577 static irqreturn_t nvec_interrupt(int irq, void *dev)
0578 {
0579     unsigned long status;
0580     unsigned int received = 0;
0581     unsigned char to_send = 0xff;
0582     const unsigned long irq_mask = I2C_SL_IRQ | END_TRANS | RCVD | RNW;
0583     struct nvec_chip *nvec = dev;
0584     unsigned int state = nvec->state;
0585 
0586     status = readl(nvec->base + I2C_SL_STATUS);
0587 
0588     /* Filter out some errors */
0589     if ((status & irq_mask) == 0 && (status & ~irq_mask) != 0) {
0590         dev_err(nvec->dev, "unexpected irq mask %lx\n", status);
0591         return IRQ_HANDLED;
0592     }
0593     if ((status & I2C_SL_IRQ) == 0) {
0594         dev_err(nvec->dev, "Spurious IRQ\n");
0595         return IRQ_HANDLED;
0596     }
0597 
0598     /* The EC did not request a read, so it send us something, read it */
0599     if ((status & RNW) == 0) {
0600         received = readl(nvec->base + I2C_SL_RCVD);
0601         if (status & RCVD)
0602             writel(0, nvec->base + I2C_SL_RCVD);
0603     }
0604 
0605     if (status == (I2C_SL_IRQ | RCVD))
0606         nvec->state = 0;
0607 
0608     switch (nvec->state) {
0609     case 0:     /* Verify that its a transfer start, the rest later */
0610         if (status != (I2C_SL_IRQ | RCVD))
0611             nvec_invalid_flags(nvec, status, false);
0612         break;
0613     case 1:     /* command byte */
0614         if (status != I2C_SL_IRQ) {
0615             nvec_invalid_flags(nvec, status, true);
0616         } else {
0617             nvec->rx = nvec_msg_alloc(nvec, NVEC_MSG_RX);
0618             /* Should not happen in a normal world */
0619             if (unlikely(!nvec->rx)) {
0620                 nvec->state = 0;
0621                 break;
0622             }
0623             nvec->rx->data[0] = received;
0624             nvec->rx->pos = 1;
0625             nvec->state = 2;
0626         }
0627         break;
0628     case 2:     /* first byte after command */
0629         if (status == (I2C_SL_IRQ | RNW | RCVD)) {
0630             udelay(33);
0631             if (nvec->rx->data[0] != 0x01) {
0632                 dev_err(nvec->dev,
0633                     "Read without prior read command\n");
0634                 nvec->state = 0;
0635                 break;
0636             }
0637             nvec_msg_free(nvec, nvec->rx);
0638             nvec->state = 3;
0639             nvec_tx_set(nvec);
0640             to_send = nvec->tx->data[0];
0641             nvec->tx->pos = 1;
0642         } else if (status == (I2C_SL_IRQ)) {
0643             nvec->rx->data[1] = received;
0644             nvec->rx->pos = 2;
0645             nvec->state = 4;
0646         } else {
0647             nvec_invalid_flags(nvec, status, true);
0648         }
0649         break;
0650     case 3:     /* EC does a block read, we transmit data */
0651         if (status & END_TRANS) {
0652             nvec_tx_completed(nvec);
0653         } else if ((status & RNW) == 0 || (status & RCVD)) {
0654             nvec_invalid_flags(nvec, status, true);
0655         } else if (nvec->tx && nvec->tx->pos < nvec->tx->size) {
0656             to_send = nvec->tx->data[nvec->tx->pos++];
0657         } else {
0658             dev_err(nvec->dev,
0659                 "tx buffer underflow on %p (%u > %u)\n",
0660                 nvec->tx,
0661                 (uint)(nvec->tx ? nvec->tx->pos : 0),
0662                 (uint)(nvec->tx ? nvec->tx->size : 0));
0663             nvec->state = 0;
0664         }
0665         break;
0666     case 4:     /* EC does some write, we read the data */
0667         if ((status & (END_TRANS | RNW)) == END_TRANS)
0668             nvec_rx_completed(nvec);
0669         else if (status & (RNW | RCVD))
0670             nvec_invalid_flags(nvec, status, true);
0671         else if (nvec->rx && nvec->rx->pos < NVEC_MSG_SIZE)
0672             nvec->rx->data[nvec->rx->pos++] = received;
0673         else
0674             dev_err(nvec->dev,
0675                 "RX buffer overflow on %p: Trying to write byte %u of %u\n",
0676                 nvec->rx, nvec->rx ? nvec->rx->pos : 0,
0677                 NVEC_MSG_SIZE);
0678         break;
0679     default:
0680         nvec->state = 0;
0681     }
0682 
0683     /* If we are told that a new transfer starts, verify it */
0684     if ((status & (RCVD | RNW)) == RCVD) {
0685         if (received != nvec->i2c_addr)
0686             dev_err(nvec->dev,
0687                 "received address 0x%02x, expected 0x%02x\n",
0688                 received, nvec->i2c_addr);
0689         nvec->state = 1;
0690     }
0691 
0692     /* Send data if requested, but not on end of transmission */
0693     if ((status & (RNW | END_TRANS)) == RNW)
0694         writel(to_send, nvec->base + I2C_SL_RCVD);
0695 
0696     /* If we have send the first byte */
0697     if (status == (I2C_SL_IRQ | RNW | RCVD))
0698         nvec_gpio_set_value(nvec, 1);
0699 
0700     dev_dbg(nvec->dev,
0701         "Handled: %s 0x%02x, %s 0x%02x in state %u [%s%s%s]\n",
0702         (status & RNW) == 0 ? "received" : "R=",
0703         received,
0704         (status & (RNW | END_TRANS)) ? "sent" : "S=",
0705         to_send,
0706         state,
0707         status & END_TRANS ? " END_TRANS" : "",
0708         status & RCVD ? " RCVD" : "",
0709         status & RNW ? " RNW" : "");
0710 
0711     /*
0712      * TODO: A correct fix needs to be found for this.
0713      *
0714      * We experience less incomplete messages with this delay than without
0715      * it, but we don't know why. Help is appreciated.
0716      */
0717     udelay(100);
0718 
0719     return IRQ_HANDLED;
0720 }
0721 
0722 static void tegra_init_i2c_slave(struct nvec_chip *nvec)
0723 {
0724     u32 val;
0725 
0726     clk_prepare_enable(nvec->i2c_clk);
0727 
0728     reset_control_assert(nvec->rst);
0729     udelay(2);
0730     reset_control_deassert(nvec->rst);
0731 
0732     val = I2C_CNFG_NEW_MASTER_SFM | I2C_CNFG_PACKET_MODE_EN |
0733         (0x2 << I2C_CNFG_DEBOUNCE_CNT_SHIFT);
0734     writel(val, nvec->base + I2C_CNFG);
0735 
0736     clk_set_rate(nvec->i2c_clk, 8 * 80000);
0737 
0738     writel(I2C_SL_NEWSL, nvec->base + I2C_SL_CNFG);
0739     writel(0x1E, nvec->base + I2C_SL_DELAY_COUNT);
0740 
0741     writel(nvec->i2c_addr >> 1, nvec->base + I2C_SL_ADDR1);
0742     writel(0, nvec->base + I2C_SL_ADDR2);
0743 
0744     enable_irq(nvec->irq);
0745 }
0746 
0747 #ifdef CONFIG_PM_SLEEP
0748 static void nvec_disable_i2c_slave(struct nvec_chip *nvec)
0749 {
0750     disable_irq(nvec->irq);
0751     writel(I2C_SL_NEWSL | I2C_SL_NACK, nvec->base + I2C_SL_CNFG);
0752     clk_disable_unprepare(nvec->i2c_clk);
0753 }
0754 #endif
0755 
0756 static void nvec_power_off(void)
0757 {
0758     char ap_pwr_down[] = { NVEC_SLEEP, AP_PWR_DOWN };
0759 
0760     nvec_toggle_global_events(nvec_power_handle, false);
0761     nvec_write_async(nvec_power_handle, ap_pwr_down, 2);
0762 }
0763 
0764 static int tegra_nvec_probe(struct platform_device *pdev)
0765 {
0766     int err, ret;
0767     struct clk *i2c_clk;
0768     struct device *dev = &pdev->dev;
0769     struct nvec_chip *nvec;
0770     struct nvec_msg *msg;
0771     void __iomem *base;
0772     char    get_firmware_version[] = { NVEC_CNTL, GET_FIRMWARE_VERSION },
0773         unmute_speakers[] = { NVEC_OEM0, 0x10, 0x59, 0x95 },
0774         enable_event[7] = { NVEC_SYS, CNF_EVENT_REPORTING, true };
0775 
0776     if (!dev->of_node) {
0777         dev_err(dev, "must be instantiated using device tree\n");
0778         return -ENODEV;
0779     }
0780 
0781     nvec = devm_kzalloc(dev, sizeof(struct nvec_chip), GFP_KERNEL);
0782     if (!nvec)
0783         return -ENOMEM;
0784 
0785     platform_set_drvdata(pdev, nvec);
0786     nvec->dev = dev;
0787 
0788     if (of_property_read_u32(dev->of_node, "slave-addr", &nvec->i2c_addr)) {
0789         dev_err(dev, "no i2c address specified");
0790         return -ENODEV;
0791     }
0792 
0793     base = devm_platform_ioremap_resource(pdev, 0);
0794     if (IS_ERR(base))
0795         return PTR_ERR(base);
0796 
0797     nvec->irq = platform_get_irq(pdev, 0);
0798     if (nvec->irq < 0)
0799         return -ENODEV;
0800 
0801     i2c_clk = devm_clk_get(dev, "div-clk");
0802     if (IS_ERR(i2c_clk)) {
0803         dev_err(dev, "failed to get controller clock\n");
0804         return -ENODEV;
0805     }
0806 
0807     nvec->rst = devm_reset_control_get_exclusive(dev, "i2c");
0808     if (IS_ERR(nvec->rst)) {
0809         dev_err(dev, "failed to get controller reset\n");
0810         return PTR_ERR(nvec->rst);
0811     }
0812 
0813     nvec->base = base;
0814     nvec->i2c_clk = i2c_clk;
0815     nvec->rx = &nvec->msg_pool[0];
0816 
0817     ATOMIC_INIT_NOTIFIER_HEAD(&nvec->notifier_list);
0818 
0819     init_completion(&nvec->sync_write);
0820     init_completion(&nvec->ec_transfer);
0821     mutex_init(&nvec->sync_write_mutex);
0822     spin_lock_init(&nvec->tx_lock);
0823     spin_lock_init(&nvec->rx_lock);
0824     INIT_LIST_HEAD(&nvec->rx_data);
0825     INIT_LIST_HEAD(&nvec->tx_data);
0826     INIT_WORK(&nvec->rx_work, nvec_dispatch);
0827     INIT_WORK(&nvec->tx_work, nvec_request_master);
0828 
0829     nvec->gpiod = devm_gpiod_get(dev, "request", GPIOD_OUT_HIGH);
0830     if (IS_ERR(nvec->gpiod)) {
0831         dev_err(dev, "couldn't request gpio\n");
0832         return PTR_ERR(nvec->gpiod);
0833     }
0834 
0835     err = devm_request_irq(dev, nvec->irq, nvec_interrupt, 0,
0836                    "nvec", nvec);
0837     if (err) {
0838         dev_err(dev, "couldn't request irq\n");
0839         return -ENODEV;
0840     }
0841     disable_irq(nvec->irq);
0842 
0843     tegra_init_i2c_slave(nvec);
0844 
0845     /* enable event reporting */
0846     nvec_toggle_global_events(nvec, true);
0847 
0848     nvec->nvec_status_notifier.notifier_call = nvec_status_notifier;
0849     nvec_register_notifier(nvec, &nvec->nvec_status_notifier, 0);
0850 
0851     nvec_power_handle = nvec;
0852     pm_power_off = nvec_power_off;
0853 
0854     /* Get Firmware Version */
0855     err = nvec_write_sync(nvec, get_firmware_version, 2, &msg);
0856 
0857     if (!err) {
0858         dev_warn(dev,
0859              "ec firmware version %02x.%02x.%02x / %02x\n",
0860              msg->data[4], msg->data[5],
0861              msg->data[6], msg->data[7]);
0862 
0863         nvec_msg_free(nvec, msg);
0864     }
0865 
0866     ret = mfd_add_devices(dev, 0, nvec_devices,
0867                   ARRAY_SIZE(nvec_devices), NULL, 0, NULL);
0868     if (ret)
0869         dev_err(dev, "error adding subdevices\n");
0870 
0871     /* unmute speakers? */
0872     nvec_write_async(nvec, unmute_speakers, 4);
0873 
0874     /* enable lid switch event */
0875     nvec_event_mask(enable_event, LID_SWITCH);
0876     nvec_write_async(nvec, enable_event, 7);
0877 
0878     /* enable power button event */
0879     nvec_event_mask(enable_event, PWR_BUTTON);
0880     nvec_write_async(nvec, enable_event, 7);
0881 
0882     return 0;
0883 }
0884 
0885 static int tegra_nvec_remove(struct platform_device *pdev)
0886 {
0887     struct nvec_chip *nvec = platform_get_drvdata(pdev);
0888 
0889     nvec_toggle_global_events(nvec, false);
0890     mfd_remove_devices(nvec->dev);
0891     nvec_unregister_notifier(nvec, &nvec->nvec_status_notifier);
0892     cancel_work_sync(&nvec->rx_work);
0893     cancel_work_sync(&nvec->tx_work);
0894     /* FIXME: needs check whether nvec is responsible for power off */
0895     pm_power_off = NULL;
0896 
0897     return 0;
0898 }
0899 
0900 #ifdef CONFIG_PM_SLEEP
0901 static int nvec_suspend(struct device *dev)
0902 {
0903     int err;
0904     struct nvec_chip *nvec = dev_get_drvdata(dev);
0905     struct nvec_msg *msg;
0906     char ap_suspend[] = { NVEC_SLEEP, AP_SUSPEND };
0907 
0908     dev_dbg(nvec->dev, "suspending\n");
0909 
0910     /* keep these sync or you'll break suspend */
0911     nvec_toggle_global_events(nvec, false);
0912 
0913     err = nvec_write_sync(nvec, ap_suspend, sizeof(ap_suspend), &msg);
0914     if (!err)
0915         nvec_msg_free(nvec, msg);
0916 
0917     nvec_disable_i2c_slave(nvec);
0918 
0919     return 0;
0920 }
0921 
0922 static int nvec_resume(struct device *dev)
0923 {
0924     struct nvec_chip *nvec = dev_get_drvdata(dev);
0925 
0926     dev_dbg(nvec->dev, "resuming\n");
0927     tegra_init_i2c_slave(nvec);
0928     nvec_toggle_global_events(nvec, true);
0929 
0930     return 0;
0931 }
0932 #endif
0933 
0934 static SIMPLE_DEV_PM_OPS(nvec_pm_ops, nvec_suspend, nvec_resume);
0935 
0936 /* Match table for of_platform binding */
0937 static const struct of_device_id nvidia_nvec_of_match[] = {
0938     { .compatible = "nvidia,nvec", },
0939     {},
0940 };
0941 MODULE_DEVICE_TABLE(of, nvidia_nvec_of_match);
0942 
0943 static struct platform_driver nvec_device_driver = {
0944     .probe   = tegra_nvec_probe,
0945     .remove  = tegra_nvec_remove,
0946     .driver  = {
0947         .name = "nvec",
0948         .pm = &nvec_pm_ops,
0949         .of_match_table = nvidia_nvec_of_match,
0950     }
0951 };
0952 
0953 module_platform_driver(nvec_device_driver);
0954 
0955 MODULE_ALIAS("platform:nvec");
0956 MODULE_DESCRIPTION("NVIDIA compliant embedded controller interface");
0957 MODULE_AUTHOR("Marc Dietrich <marvin24@gmx.de>");
0958 MODULE_LICENSE("GPL");