media/tegra-video/vi.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Copyright (C) 2020 NVIDIA CORPORATION.  All rights reserved.
0004  */
0005
0006 #ifndef __TEGRA_VI_H__
0007 #define __TEGRA_VI_H__
0008
0009 #include <linux/host1x.h>
0010 #include <linux/list.h>
0011
0012 #include <linux/mutex.h>
0013 #include <linux/spinlock.h>
0014 #include <linux/wait.h>
0015
0016 #include <media/media-entity.h>
0017 #include <media/v4l2-async.h>
0018 #include <media/v4l2-ctrls.h>
0019 #include <media/v4l2-device.h>
0020 #include <media/v4l2-dev.h>
0021 #include <media/v4l2-subdev.h>
0022 #include <media/videobuf2-v4l2.h>
0023
0024 #include "csi.h"
0025
0026 #define V4L2_CID_TEGRA_SYNCPT_TIMEOUT_RETRY (V4L2_CTRL_CLASS_CAMERA | 0x1001)
0027
0028 #define TEGRA_MIN_WIDTH     32U
0029 #define TEGRA_MAX_WIDTH     32768U
0030 #define TEGRA_MIN_HEIGHT    32U
0031 #define TEGRA_MAX_HEIGHT    32768U
0032
0033 #define TEGRA_DEF_WIDTH     1920
0034 #define TEGRA_DEF_HEIGHT    1080
0035 #define TEGRA_IMAGE_FORMAT_DEF  32
0036
0037 #define MAX_FORMAT_NUM      64
0038 #define SURFACE_ALIGN_BYTES 64
0039
0040 enum tegra_vi_pg_mode {
0041     TEGRA_VI_PG_DISABLED = 0,
0042     TEGRA_VI_PG_DIRECT,
0043     TEGRA_VI_PG_PATCH,
0044 };
0045
0046 /**
0047  * struct tegra_vi_ops - Tegra VI operations
0048  * @vi_start_streaming: starts media pipeline, subdevice streaming, sets up
0049  *      VI for capture and runs capture start and capture finish
0050  *      kthreads for capturing frames to buffer and returns them back.
0051  * @vi_stop_streaming: stops media pipeline and subdevice streaming and returns
0052  *      back any queued buffers.
0053  */
0054 struct tegra_vi_ops {
0055     int (*vi_start_streaming)(struct vb2_queue *vq, u32 count);
0056     void (*vi_stop_streaming)(struct vb2_queue *vq);
0057 };
0058
0059 /**
0060  * struct tegra_vi_soc - NVIDIA Tegra Video Input SoC structure
0061  *
0062  * @video_formats: supported video formats
0063  * @nformats: total video formats
0064  * @ops: vi operations
0065  * @hw_revision: VI hw_revision
0066  * @vi_max_channels: supported max streaming channels
0067  * @vi_max_clk_hz: VI clock max frequency
0068  */
0069 struct tegra_vi_soc {
0070     const struct tegra_video_format *video_formats;
0071     const unsigned int nformats;
0072     const struct tegra_vi_ops *ops;
0073     u32 hw_revision;
0074     unsigned int vi_max_channels;
0075     unsigned int vi_max_clk_hz;
0076 };
0077
0078 /**
0079  * struct tegra_vi - NVIDIA Tegra Video Input device structure
0080  *
0081  * @dev: device struct
0082  * @client: host1x_client struct
0083  * @iomem: register base
0084  * @clk: main clock for VI block
0085  * @vdd: vdd regulator for VI hardware, normally it is avdd_dsi_csi
0086  * @soc: pointer to SoC data structure
0087  * @ops: vi operations
0088  * @vi_chans: list head for VI channels
0089  */
0090 struct tegra_vi {
0091     struct device *dev;
0092     struct host1x_client client;
0093     void __iomem *iomem;
0094     struct clk *clk;
0095     struct regulator *vdd;
0096     const struct tegra_vi_soc *soc;
0097     const struct tegra_vi_ops *ops;
0098     struct list_head vi_chans;
0099 };
0100
0101 /**
0102  * struct tegra_vi_graph_entity - Entity in the video graph
0103  *
0104  * @asd: subdev asynchronous registration information
0105  * @entity: media entity from the corresponding V4L2 subdev
0106  * @subdev: V4L2 subdev
0107  */
0108 struct tegra_vi_graph_entity {
0109     struct v4l2_async_subdev asd;
0110     struct media_entity *entity;
0111     struct v4l2_subdev *subdev;
0112 };
0113
0114 /**
0115  * struct tegra_vi_channel - Tegra video channel
0116  *
0117  * @list: list head for this entry
0118  * @video: V4L2 video device associated with the video channel
0119  * @video_lock: protects the @format and @queue fields
0120  * @pad: media pad for the video device entity
0121  *
0122  * @vi: Tegra video input device structure
0123  * @frame_start_sp: host1x syncpoint pointer to synchronize programmed capture
0124  *      start condition with hardware frame start events through host1x
0125  *      syncpoint counters.
0126  * @mw_ack_sp: host1x syncpoint pointer to synchronize programmed memory write
0127  *      ack trigger condition with hardware memory write done at end of
0128  *      frame through host1x syncpoint counters.
0129  * @sp_incr_lock: protects cpu syncpoint increment.
0130  *
0131  * @kthread_start_capture: kthread to start capture of single frame when
0132  *      vb buffer is available. This thread programs VI CSI hardware
0133  *      for single frame capture and waits for frame start event from
0134  *      the hardware. On receiving frame start event, it wakes up
0135  *      kthread_finish_capture thread to wait for finishing frame data
0136  *      write to the memory. In case of missing frame start event, this
0137  *      thread returns buffer back to vb with VB2_BUF_STATE_ERROR.
0138  * @start_wait: waitqueue for starting frame capture when buffer is available.
0139  * @kthread_finish_capture: kthread to finish the buffer capture and return to.
0140  *      This thread is woken up by kthread_start_capture on receiving
0141  *      frame start event from the hardware and this thread waits for
0142  *      MW_ACK_DONE event which indicates completion of writing frame
0143  *      data to the memory. On receiving MW_ACK_DONE event, buffer is
0144  *      returned back to vb with VB2_BUF_STATE_DONE and in case of
0145  *      missing MW_ACK_DONE event, buffer is returned back to vb with
0146  *      VB2_BUF_STATE_ERROR.
0147  * @done_wait: waitqueue for finishing capture data writes to memory.
0148  *
0149  * @format: active V4L2 pixel format
0150  * @fmtinfo: format information corresponding to the active @format
0151  * @queue: vb2 buffers queue
0152  * @sequence: V4L2 buffers sequence number
0153  *
0154  * @capture: list of queued buffers for capture
0155  * @start_lock: protects the capture queued list
0156  * @done: list of capture done queued buffers
0157  * @done_lock: protects the capture done queue list
0158  *
0159  * @portnos: VI channel port numbers
0160  * @totalports: total number of ports used for this channel
0161  * @numgangports: number of ports combined together as a gang for capture
0162  * @of_node: device node of VI channel
0163  *
0164  * @ctrl_handler: V4L2 control handler of this video channel
0165  * @syncpt_timeout_retry: syncpt timeout retry count for the capture
0166  * @fmts_bitmap: a bitmap for supported formats matching v4l2 subdev formats
0167  * @tpg_fmts_bitmap: a bitmap for supported TPG formats
0168  * @pg_mode: test pattern generator mode (disabled/direct/patch)
0169  * @notifier: V4L2 asynchronous subdevs notifier
0170  */
0171 struct tegra_vi_channel {
0172     struct list_head list;
0173     struct video_device video;
0174     /* protects the @format and @queue fields */
0175     struct mutex video_lock;
0176     struct media_pad pad;
0177
0178     struct tegra_vi *vi;
0179     struct host1x_syncpt *frame_start_sp[GANG_PORTS_MAX];
0180     struct host1x_syncpt *mw_ack_sp[GANG_PORTS_MAX];
0181     /* protects the cpu syncpoint increment */
0182     spinlock_t sp_incr_lock[GANG_PORTS_MAX];
0183
0184     struct task_struct *kthread_start_capture;
0185     wait_queue_head_t start_wait;
0186     struct task_struct *kthread_finish_capture;
0187     wait_queue_head_t done_wait;
0188
0189     struct v4l2_pix_format format;
0190     const struct tegra_video_format *fmtinfo;
0191     struct vb2_queue queue;
0192     u32 sequence;
0193
0194     struct list_head capture;
0195     /* protects the capture queued list */
0196     spinlock_t start_lock;
0197     struct list_head done;
0198     /* protects the capture done queue list */
0199     spinlock_t done_lock;
0200
0201     unsigned char portnos[GANG_PORTS_MAX];
0202     u8 totalports;
0203     u8 numgangports;
0204     struct device_node *of_node;
0205
0206     struct v4l2_ctrl_handler ctrl_handler;
0207     unsigned int syncpt_timeout_retry;
0208     DECLARE_BITMAP(fmts_bitmap, MAX_FORMAT_NUM);
0209     DECLARE_BITMAP(tpg_fmts_bitmap, MAX_FORMAT_NUM);
0210     enum tegra_vi_pg_mode pg_mode;
0211
0212     struct v4l2_async_notifier notifier;
0213 };
0214
0215 /**
0216  * struct tegra_channel_buffer - video channel buffer
0217  *
0218  * @buf: vb2 buffer base object
0219  * @queue: buffer list entry in the channel queued buffers list
0220  * @chan: channel that uses the buffer
0221  * @addr: Tegra IOVA buffer address for VI output
0222  * @mw_ack_sp_thresh: MW_ACK_DONE syncpoint threshold corresponding
0223  *            to the capture buffer.
0224  */
0225 struct tegra_channel_buffer {
0226     struct vb2_v4l2_buffer buf;
0227     struct list_head queue;
0228     struct tegra_vi_channel *chan;
0229     dma_addr_t addr;
0230     u32 mw_ack_sp_thresh[GANG_PORTS_MAX];
0231 };
0232
0233 /*
0234  * VI channel input data type enum.
0235  * These data type enum value gets programmed into corresponding Tegra VI
0236  * channel register bits.
0237  */
0238 enum tegra_image_dt {
0239     TEGRA_IMAGE_DT_YUV420_8 = 24,
0240     TEGRA_IMAGE_DT_YUV420_10,
0241
0242     TEGRA_IMAGE_DT_YUV420CSPS_8 = 28,
0243     TEGRA_IMAGE_DT_YUV420CSPS_10,
0244     TEGRA_IMAGE_DT_YUV422_8,
0245     TEGRA_IMAGE_DT_YUV422_10,
0246     TEGRA_IMAGE_DT_RGB444,
0247     TEGRA_IMAGE_DT_RGB555,
0248     TEGRA_IMAGE_DT_RGB565,
0249     TEGRA_IMAGE_DT_RGB666,
0250     TEGRA_IMAGE_DT_RGB888,
0251
0252     TEGRA_IMAGE_DT_RAW6 = 40,
0253     TEGRA_IMAGE_DT_RAW7,
0254     TEGRA_IMAGE_DT_RAW8,
0255     TEGRA_IMAGE_DT_RAW10,
0256     TEGRA_IMAGE_DT_RAW12,
0257     TEGRA_IMAGE_DT_RAW14,
0258 };
0259
0260 /**
0261  * struct tegra_video_format - Tegra video format description
0262  *
0263  * @img_dt: image data type
0264  * @bit_width: format width in bits per component
0265  * @code: media bus format code
0266  * @bpp: bytes per pixel (when stored in memory)
0267  * @img_fmt: image format
0268  * @fourcc: V4L2 pixel format FCC identifier
0269  */
0270 struct tegra_video_format {
0271     enum tegra_image_dt img_dt;
0272     unsigned int bit_width;
0273     unsigned int code;
0274     unsigned int bpp;
0275     u32 img_fmt;
0276     u32 fourcc;
0277 };
0278
0279 #if defined(CONFIG_ARCH_TEGRA_210_SOC)
0280 extern const struct tegra_vi_soc tegra210_vi_soc;
0281 #endif
0282
0283 struct v4l2_subdev *
0284 tegra_channel_get_remote_csi_subdev(struct tegra_vi_channel *chan);
0285 struct v4l2_subdev *
0286 tegra_channel_get_remote_source_subdev(struct tegra_vi_channel *chan);
0287 int tegra_channel_set_stream(struct tegra_vi_channel *chan, bool on);
0288 void tegra_channel_release_buffers(struct tegra_vi_channel *chan,
0289                    enum vb2_buffer_state state);
0290 void tegra_channels_cleanup(struct tegra_vi *vi);
0291 #endif