media/tegra-video/csi.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Copyright (C) 2020 NVIDIA CORPORATION.  All rights reserved.
0004  */
0005
0006 #ifndef __TEGRA_CSI_H__
0007 #define __TEGRA_CSI_H__
0008
0009 #include <media/media-entity.h>
0010 #include <media/v4l2-async.h>
0011 #include <media/v4l2-subdev.h>
0012
0013 /*
0014  * Each CSI brick supports max of 4 lanes that can be used as either
0015  * one x4 port using both CILA and CILB partitions of a CSI brick or can
0016  * be used as two x2 ports with one x2 from CILA and the other x2 from
0017  * CILB.
0018  */
0019 #define CSI_PORTS_PER_BRICK 2
0020 #define CSI_LANES_PER_BRICK 4
0021
0022 /* Maximum 2 CSI x4 ports can be ganged up for streaming */
0023 #define GANG_PORTS_MAX  2
0024
0025 /* each CSI channel can have one sink and one source pads */
0026 #define TEGRA_CSI_PADS_NUM  2
0027
0028 enum tegra_csi_cil_port {
0029     PORT_A = 0,
0030     PORT_B,
0031 };
0032
0033 enum tegra_csi_block {
0034     CSI_CIL_AB = 0,
0035     CSI_CIL_CD,
0036     CSI_CIL_EF,
0037 };
0038
0039 struct tegra_csi;
0040
0041 /**
0042  * struct tegra_csi_channel - Tegra CSI channel
0043  *
0044  * @list: list head for this entry
0045  * @subdev: V4L2 subdevice associated with this channel
0046  * @pads: media pads for the subdevice entity
0047  * @numpads: number of pads.
0048  * @csi: Tegra CSI device structure
0049  * @of_node: csi device tree node
0050  * @numgangports: number of immediate ports ganged up to meet the
0051  *             channel bus-width
0052  * @numlanes: number of lanes used per port
0053  * @csi_port_nums: CSI channel port numbers
0054  * @pg_mode: test pattern generator mode for channel
0055  * @format: active format of the channel
0056  * @framerate: active framerate for TPG
0057  * @h_blank: horizontal blanking for TPG active format
0058  * @v_blank: vertical blanking for TPG active format
0059  * @mipi: mipi device for corresponding csi channel pads
0060  * @pixel_rate: active pixel rate from the sensor on this channel
0061  */
0062 struct tegra_csi_channel {
0063     struct list_head list;
0064     struct v4l2_subdev subdev;
0065     struct media_pad pads[TEGRA_CSI_PADS_NUM];
0066     unsigned int numpads;
0067     struct tegra_csi *csi;
0068     struct device_node *of_node;
0069     u8 numgangports;
0070     unsigned int numlanes;
0071     u8 csi_port_nums[GANG_PORTS_MAX];
0072     u8 pg_mode;
0073     struct v4l2_mbus_framefmt format;
0074     unsigned int framerate;
0075     unsigned int h_blank;
0076     unsigned int v_blank;
0077     struct tegra_mipi_device *mipi;
0078     unsigned int pixel_rate;
0079 };
0080
0081 /**
0082  * struct tpg_framerate - Tegra CSI TPG framerate configuration
0083  *
0084  * @frmsize: frame resolution
0085  * @code: media bus format code
0086  * @h_blank: horizontal blanking used for TPG
0087  * @v_blank: vertical blanking interval used for TPG
0088  * @framerate: framerate achieved with the corresponding blanking intervals,
0089  *      format and resolution.
0090  */
0091 struct tpg_framerate {
0092     struct v4l2_frmsize_discrete frmsize;
0093     u32 code;
0094     unsigned int h_blank;
0095     unsigned int v_blank;
0096     unsigned int framerate;
0097 };
0098
0099 /**
0100  * struct tegra_csi_ops - Tegra CSI operations
0101  *
0102  * @csi_start_streaming: programs csi hardware to enable streaming.
0103  * @csi_stop_streaming: programs csi hardware to disable streaming.
0104  * @csi_err_recover: csi hardware block recovery in case of any capture errors
0105  *      due to missing source stream or due to improper csi input from
0106  *      the external source.
0107  */
0108 struct tegra_csi_ops {
0109     int (*csi_start_streaming)(struct tegra_csi_channel *csi_chan);
0110     void (*csi_stop_streaming)(struct tegra_csi_channel *csi_chan);
0111     void (*csi_err_recover)(struct tegra_csi_channel *csi_chan);
0112 };
0113
0114 /**
0115  * struct tegra_csi_soc - NVIDIA Tegra CSI SoC structure
0116  *
0117  * @ops: csi hardware operations
0118  * @csi_max_channels: supported max streaming channels
0119  * @clk_names: csi and cil clock names
0120  * @num_clks: total clocks count
0121  * @tpg_frmrate_table: csi tpg frame rate table with blanking intervals
0122  * @tpg_frmrate_table_size: size of frame rate table
0123  */
0124 struct tegra_csi_soc {
0125     const struct tegra_csi_ops *ops;
0126     unsigned int csi_max_channels;
0127     const char * const *clk_names;
0128     unsigned int num_clks;
0129     const struct tpg_framerate *tpg_frmrate_table;
0130     unsigned int tpg_frmrate_table_size;
0131 };
0132
0133 /**
0134  * struct tegra_csi - NVIDIA Tegra CSI device structure
0135  *
0136  * @dev: device struct
0137  * @client: host1x_client struct
0138  * @iomem: register base
0139  * @clks: clock for CSI and CIL
0140  * @soc: pointer to SoC data structure
0141  * @ops: csi operations
0142  * @csi_chans: list head for CSI channels
0143  */
0144 struct tegra_csi {
0145     struct device *dev;
0146     struct host1x_client client;
0147     void __iomem *iomem;
0148     struct clk_bulk_data *clks;
0149     const struct tegra_csi_soc *soc;
0150     const struct tegra_csi_ops *ops;
0151     struct list_head csi_chans;
0152 };
0153
0154 #if defined(CONFIG_ARCH_TEGRA_210_SOC)
0155 extern const struct tegra_csi_soc tegra210_csi_soc;
0156 #endif
0157
0158 void tegra_csi_error_recover(struct v4l2_subdev *subdev);
0159 void tegra_csi_calc_settle_time(struct tegra_csi_channel *csi_chan,
0160                 u8 csi_port_num,
0161                 u8 *clk_settle_time,
0162                 u8 *ths_settle_time);
0163 #endif