media/omap4iss/iss.h

0001 /* SPDX-License-Identifier: GPL-2.0+ */
0002 /*
0003  * TI OMAP4 ISS V4L2 Driver
0004  *
0005  * Copyright (C) 2012 Texas Instruments.
0006  *
0007  * Author: Sergio Aguirre <sergio.a.aguirre@gmail.com>
0008  */
0009
0010 #ifndef _OMAP4_ISS_H_
0011 #define _OMAP4_ISS_H_
0012
0013 #include <media/v4l2-device.h>
0014 #include <media/v4l2-mc.h>
0015
0016 #include <linux/device.h>
0017 #include <linux/io.h>
0018 #include <linux/platform_device.h>
0019 #include <linux/wait.h>
0020
0021 #include <linux/platform_data/media/omap4iss.h>
0022
0023 #include "iss_regs.h"
0024 #include "iss_csiphy.h"
0025 #include "iss_csi2.h"
0026 #include "iss_ipipeif.h"
0027 #include "iss_ipipe.h"
0028 #include "iss_resizer.h"
0029
0030 struct regmap;
0031
0032 #define to_iss_device(ptr_module)               \
0033     container_of(ptr_module, struct iss_device, ptr_module)
0034 #define to_device(ptr_module)                       \
0035     (to_iss_device(ptr_module)->dev)
0036
0037 enum iss_mem_resources {
0038     OMAP4_ISS_MEM_TOP,
0039     OMAP4_ISS_MEM_CSI2_A_REGS1,
0040     OMAP4_ISS_MEM_CAMERARX_CORE1,
0041     OMAP4_ISS_MEM_CSI2_B_REGS1,
0042     OMAP4_ISS_MEM_CAMERARX_CORE2,
0043     OMAP4_ISS_MEM_BTE,
0044     OMAP4_ISS_MEM_ISP_SYS1,
0045     OMAP4_ISS_MEM_ISP_RESIZER,
0046     OMAP4_ISS_MEM_ISP_IPIPE,
0047     OMAP4_ISS_MEM_ISP_ISIF,
0048     OMAP4_ISS_MEM_ISP_IPIPEIF,
0049     OMAP4_ISS_MEM_LAST,
0050 };
0051
0052 enum iss_subclk_resource {
0053     OMAP4_ISS_SUBCLK_SIMCOP     = (1 << 0),
0054     OMAP4_ISS_SUBCLK_ISP        = (1 << 1),
0055     OMAP4_ISS_SUBCLK_CSI2_A     = (1 << 2),
0056     OMAP4_ISS_SUBCLK_CSI2_B     = (1 << 3),
0057     OMAP4_ISS_SUBCLK_CCP2       = (1 << 4),
0058 };
0059
0060 enum iss_isp_subclk_resource {
0061     OMAP4_ISS_ISP_SUBCLK_BL     = (1 << 0),
0062     OMAP4_ISS_ISP_SUBCLK_ISIF   = (1 << 1),
0063     OMAP4_ISS_ISP_SUBCLK_H3A    = (1 << 2),
0064     OMAP4_ISS_ISP_SUBCLK_RSZ    = (1 << 3),
0065     OMAP4_ISS_ISP_SUBCLK_IPIPE  = (1 << 4),
0066     OMAP4_ISS_ISP_SUBCLK_IPIPEIF    = (1 << 5),
0067 };
0068
0069 /*
0070  * struct iss_reg - Structure for ISS register values.
0071  * @reg: 32-bit Register address.
0072  * @val: 32-bit Register value.
0073  */
0074 struct iss_reg {
0075     enum iss_mem_resources mmio_range;
0076     u32 reg;
0077     u32 val;
0078 };
0079
0080 /*
0081  * struct iss_device - ISS device structure.
0082  * @syscon: Regmap for the syscon register space
0083  * @crashed: Crashed entities
0084  */
0085 struct iss_device {
0086     struct v4l2_device v4l2_dev;
0087     struct media_device media_dev;
0088     struct device *dev;
0089     u32 revision;
0090
0091     /* platform HW resources */
0092     struct iss_platform_data *pdata;
0093     unsigned int irq_num;
0094
0095     struct resource *res[OMAP4_ISS_MEM_LAST];
0096     void __iomem *regs[OMAP4_ISS_MEM_LAST];
0097     struct regmap *syscon;
0098
0099     u64 raw_dmamask;
0100
0101     struct mutex iss_mutex; /* For handling ref_count field */
0102     struct media_entity_enum crashed;
0103     int has_context;
0104     int ref_count;
0105
0106     struct clk *iss_fck;
0107     struct clk *iss_ctrlclk;
0108
0109     /* ISS modules */
0110     struct iss_csi2_device csi2a;
0111     struct iss_csi2_device csi2b;
0112     struct iss_csiphy csiphy1;
0113     struct iss_csiphy csiphy2;
0114     struct iss_ipipeif_device ipipeif;
0115     struct iss_ipipe_device ipipe;
0116     struct iss_resizer_device resizer;
0117
0118     unsigned int subclk_resources;
0119     unsigned int isp_subclk_resources;
0120 };
0121
0122 int omap4iss_get_external_info(struct iss_pipeline *pipe,
0123                    struct media_link *link);
0124
0125 int omap4iss_module_sync_idle(struct media_entity *me, wait_queue_head_t *wait,
0126                   atomic_t *stopping);
0127
0128 int omap4iss_module_sync_is_stopping(wait_queue_head_t *wait,
0129                      atomic_t *stopping);
0130
0131 int omap4iss_pipeline_set_stream(struct iss_pipeline *pipe,
0132                  enum iss_pipeline_stream_state state);
0133 void omap4iss_pipeline_cancel_stream(struct iss_pipeline *pipe);
0134
0135 void omap4iss_configure_bridge(struct iss_device *iss,
0136                    enum ipipeif_input_entity input);
0137
0138 struct iss_device *omap4iss_get(struct iss_device *iss);
0139 void omap4iss_put(struct iss_device *iss);
0140 int omap4iss_subclk_enable(struct iss_device *iss,
0141                enum iss_subclk_resource res);
0142 int omap4iss_subclk_disable(struct iss_device *iss,
0143                 enum iss_subclk_resource res);
0144 void omap4iss_isp_subclk_enable(struct iss_device *iss,
0145                 enum iss_isp_subclk_resource res);
0146 void omap4iss_isp_subclk_disable(struct iss_device *iss,
0147                  enum iss_isp_subclk_resource res);
0148
0149 int omap4iss_register_entities(struct platform_device *pdev,
0150                    struct v4l2_device *v4l2_dev);
0151 void omap4iss_unregister_entities(struct platform_device *pdev);
0152
0153 /*
0154  * iss_reg_read - Read the value of an OMAP4 ISS register
0155  * @iss: the ISS device
0156  * @res: memory resource in which the register is located
0157  * @offset: register offset in the memory resource
0158  *
0159  * Return the register value.
0160  */
0161 static inline
0162 u32 iss_reg_read(struct iss_device *iss, enum iss_mem_resources res,
0163          u32 offset)
0164 {
0165     return readl(iss->regs[res] + offset);
0166 }
0167
0168 /*
0169  * iss_reg_write - Write a value to an OMAP4 ISS register
0170  * @iss: the ISS device
0171  * @res: memory resource in which the register is located
0172  * @offset: register offset in the memory resource
0173  * @value: value to be written
0174  */
0175 static inline
0176 void iss_reg_write(struct iss_device *iss, enum iss_mem_resources res,
0177            u32 offset, u32 value)
0178 {
0179     writel(value, iss->regs[res] + offset);
0180 }
0181
0182 /*
0183  * iss_reg_clr - Clear bits in an OMAP4 ISS register
0184  * @iss: the ISS device
0185  * @res: memory resource in which the register is located
0186  * @offset: register offset in the memory resource
0187  * @clr: bit mask to be cleared
0188  */
0189 static inline
0190 void iss_reg_clr(struct iss_device *iss, enum iss_mem_resources res,
0191          u32 offset, u32 clr)
0192 {
0193     u32 v = iss_reg_read(iss, res, offset);
0194
0195     iss_reg_write(iss, res, offset, v & ~clr);
0196 }
0197
0198 /*
0199  * iss_reg_set - Set bits in an OMAP4 ISS register
0200  * @iss: the ISS device
0201  * @res: memory resource in which the register is located
0202  * @offset: register offset in the memory resource
0203  * @set: bit mask to be set
0204  */
0205 static inline
0206 void iss_reg_set(struct iss_device *iss, enum iss_mem_resources res,
0207          u32 offset, u32 set)
0208 {
0209     u32 v = iss_reg_read(iss, res, offset);
0210
0211     iss_reg_write(iss, res, offset, v | set);
0212 }
0213
0214 /*
0215  * iss_reg_update - Clear and set bits in an OMAP4 ISS register
0216  * @iss: the ISS device
0217  * @res: memory resource in which the register is located
0218  * @offset: register offset in the memory resource
0219  * @clr: bit mask to be cleared
0220  * @set: bit mask to be set
0221  *
0222  * Clear the clr mask first and then set the set mask.
0223  */
0224 static inline
0225 void iss_reg_update(struct iss_device *iss, enum iss_mem_resources res,
0226             u32 offset, u32 clr, u32 set)
0227 {
0228     u32 v = iss_reg_read(iss, res, offset);
0229
0230     iss_reg_write(iss, res, offset, (v & ~clr) | set);
0231 }
0232
0233 #define iss_poll_condition_timeout(cond, timeout, min_ival, max_ival)   \
0234 ({                                  \
0235     unsigned long __timeout = jiffies + usecs_to_jiffies(timeout);  \
0236     unsigned int __min_ival = (min_ival);               \
0237     unsigned int __max_ival = (max_ival);               \
0238     bool __cond;                            \
0239     while (!(__cond = (cond))) {                    \
0240         if (time_after(jiffies, __timeout))         \
0241             break;                      \
0242         usleep_range(__min_ival, __max_ival);           \
0243     }                               \
0244     !__cond;                            \
0245 })
0246
0247 #endif /* _OMAP4_ISS_H_ */