media/ipu3/ipu3-css.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /* Copyright (C) 2018 Intel Corporation */
0003
0004 #ifndef __IPU3_CSS_H
0005 #define __IPU3_CSS_H
0006
0007 #include <linux/videodev2.h>
0008 #include <linux/types.h>
0009
0010 #include "ipu3-abi.h"
0011 #include "ipu3-css-pool.h"
0012
0013 /* 2 stages for split isp pipeline, 1 for scaling */
0014 #define IMGU_NUM_SP         2
0015 #define IMGU_MAX_PIPELINE_NUM       20
0016 #define IMGU_MAX_PIPE_NUM       2
0017
0018 /* For DVS etc., format FRAME_FMT_YUV420_16 */
0019 #define IPU3_CSS_AUX_FRAME_REF      0
0020 /* For temporal noise reduction DVS etc., format FRAME_FMT_YUV_LINE */
0021 #define IPU3_CSS_AUX_FRAME_TNR      1
0022 #define IPU3_CSS_AUX_FRAME_TYPES    2   /* REF and TNR */
0023 #define IPU3_CSS_AUX_FRAMES     2   /* 2 for REF and 2 for TNR */
0024
0025 #define IPU3_CSS_QUEUE_IN       0
0026 #define IPU3_CSS_QUEUE_PARAMS       1
0027 #define IPU3_CSS_QUEUE_OUT      2
0028 #define IPU3_CSS_QUEUE_VF       3
0029 #define IPU3_CSS_QUEUE_STAT_3A      4
0030 #define IPU3_CSS_QUEUES         5
0031
0032 #define IPU3_CSS_RECT_EFFECTIVE     0   /* Effective resolution */
0033 #define IPU3_CSS_RECT_BDS       1   /* Resolution after BDS */
0034 #define IPU3_CSS_RECT_ENVELOPE      2   /* DVS envelope size */
0035 #define IPU3_CSS_RECT_GDC       3   /* gdc output res */
0036 #define IPU3_CSS_RECTS          4   /* number of rects */
0037
0038 #define IA_CSS_BINARY_MODE_PRIMARY  2
0039 #define IA_CSS_BINARY_MODE_VIDEO    3
0040 #define IPU3_CSS_DEFAULT_BINARY     3   /* default binary index */
0041
0042 /*
0043  * The pipe id type, distinguishes the kind of pipes that
0044  * can be run in parallel.
0045  */
0046 enum imgu_css_pipe_id {
0047     IPU3_CSS_PIPE_ID_PREVIEW,
0048     IPU3_CSS_PIPE_ID_COPY,
0049     IPU3_CSS_PIPE_ID_VIDEO,
0050     IPU3_CSS_PIPE_ID_CAPTURE,
0051     IPU3_CSS_PIPE_ID_YUVPP,
0052     IPU3_CSS_PIPE_ID_ACC,
0053     IPU3_CSS_PIPE_ID_NUM
0054 };
0055
0056 struct imgu_css_resolution {
0057     u32 w;
0058     u32 h;
0059 };
0060
0061 enum imgu_css_buffer_state {
0062     IPU3_CSS_BUFFER_NEW,    /* Not yet queued */
0063     IPU3_CSS_BUFFER_QUEUED, /* Queued, waiting to be filled */
0064     IPU3_CSS_BUFFER_DONE,   /* Finished processing, removed from queue */
0065     IPU3_CSS_BUFFER_FAILED, /* Was not processed, removed from queue */
0066 };
0067
0068 struct imgu_css_buffer {
0069     /* Private fields: user doesn't touch */
0070     dma_addr_t daddr;
0071     unsigned int queue;
0072     enum imgu_css_buffer_state state;
0073     struct list_head list;
0074     u8 queue_pos;
0075     unsigned int pipe;
0076 };
0077
0078 struct imgu_css_format {
0079     u32 pixelformat;
0080     enum v4l2_colorspace colorspace;
0081     enum imgu_abi_frame_format frame_format;
0082     enum imgu_abi_bayer_order bayer_order;
0083     enum imgu_abi_osys_format osys_format;
0084     enum imgu_abi_osys_tiling osys_tiling;
0085     u8 bit_depth;       /* Effective bits per pixel */
0086     u8 chroma_decim;    /* Chroma plane decimation, 0=no chroma plane */
0087     u8 width_align;     /* Alignment requirement for width_pad */
0088     u8 flags;
0089 };
0090
0091 struct imgu_css_queue {
0092     union {
0093         struct v4l2_pix_format_mplane mpix;
0094         struct v4l2_meta_format meta;
0095
0096     } fmt;
0097     const struct imgu_css_format *css_fmt;
0098     unsigned int width_pad;
0099     struct list_head bufs;
0100 };
0101
0102 struct imgu_css_pipe {
0103     enum imgu_css_pipe_id pipe_id;
0104     unsigned int bindex;
0105
0106     struct imgu_css_queue queue[IPU3_CSS_QUEUES];
0107     struct v4l2_rect rect[IPU3_CSS_RECTS];
0108
0109     bool vf_output_en;
0110     /* Protect access to queue[IPU3_CSS_QUEUES] */
0111     spinlock_t qlock;
0112
0113     /* Data structures shared with IMGU and driver, always allocated */
0114     struct imgu_css_map sp_ddr_ptrs;
0115     struct imgu_css_map xmem_sp_stage_ptrs[IPU3_CSS_PIPE_ID_NUM]
0116                         [IMGU_ABI_MAX_STAGES];
0117     struct imgu_css_map xmem_isp_stage_ptrs[IPU3_CSS_PIPE_ID_NUM]
0118                         [IMGU_ABI_MAX_STAGES];
0119
0120     /*
0121      * Data structures shared with IMGU and driver, binary specific.
0122      * PARAM_CLASS_CONFIG and PARAM_CLASS_STATE parameters.
0123      */
0124     struct imgu_css_map binary_params_cs[IMGU_ABI_PARAM_CLASS_NUM - 1]
0125                         [IMGU_ABI_NUM_MEMORIES];
0126
0127     struct {
0128         struct imgu_css_map mem[IPU3_CSS_AUX_FRAMES];
0129         unsigned int width;
0130         unsigned int height;
0131         unsigned int bytesperline;
0132         unsigned int bytesperpixel;
0133     } aux_frames[IPU3_CSS_AUX_FRAME_TYPES];
0134
0135     struct {
0136         struct imgu_css_pool parameter_set_info;
0137         struct imgu_css_pool acc;
0138         struct imgu_css_pool gdc;
0139         struct imgu_css_pool obgrid;
0140         /* PARAM_CLASS_PARAM parameters for binding while streaming */
0141         struct imgu_css_pool binary_params_p[IMGU_ABI_NUM_MEMORIES];
0142     } pool;
0143
0144     struct imgu_css_map abi_buffers[IPU3_CSS_QUEUES]
0145                     [IMGU_ABI_HOST2SP_BUFQ_SIZE];
0146 };
0147
0148 /* IPU3 Camera Sub System structure */
0149 struct imgu_css {
0150     struct device *dev;
0151     void __iomem *base;
0152     const struct firmware *fw;
0153     struct imgu_fw_header *fwp;
0154     int iomem_length;
0155     int fw_bl, fw_sp[IMGU_NUM_SP];  /* Indices of bl and SP binaries */
0156     struct imgu_css_map *binary;    /* fw binaries mapped to device */
0157     bool streaming;     /* true when streaming is enabled */
0158
0159     struct imgu_css_pipe pipes[IMGU_MAX_PIPE_NUM];
0160     struct imgu_css_map xmem_sp_group_ptrs;
0161
0162     /* enabled pipe(s) */
0163     DECLARE_BITMAP(enabled_pipes, IMGU_MAX_PIPE_NUM);
0164 };
0165
0166 /******************* css v4l *******************/
0167 int imgu_css_init(struct device *dev, struct imgu_css *css,
0168           void __iomem *base, int length);
0169 void imgu_css_cleanup(struct imgu_css *css);
0170 int imgu_css_fmt_try(struct imgu_css *css,
0171              struct v4l2_pix_format_mplane *fmts[IPU3_CSS_QUEUES],
0172              struct v4l2_rect *rects[IPU3_CSS_RECTS],
0173              unsigned int pipe);
0174 int imgu_css_fmt_set(struct imgu_css *css,
0175              struct v4l2_pix_format_mplane *fmts[IPU3_CSS_QUEUES],
0176              struct v4l2_rect *rects[IPU3_CSS_RECTS],
0177              unsigned int pipe);
0178 int imgu_css_meta_fmt_set(struct v4l2_meta_format *fmt);
0179 int imgu_css_buf_queue(struct imgu_css *css, unsigned int pipe,
0180                struct imgu_css_buffer *b);
0181 struct imgu_css_buffer *imgu_css_buf_dequeue(struct imgu_css *css);
0182 int imgu_css_start_streaming(struct imgu_css *css);
0183 void imgu_css_stop_streaming(struct imgu_css *css);
0184 bool imgu_css_queue_empty(struct imgu_css *css);
0185 bool imgu_css_is_streaming(struct imgu_css *css);
0186 bool imgu_css_pipe_queue_empty(struct imgu_css *css, unsigned int pipe);
0187
0188 /******************* css hw *******************/
0189 int imgu_css_set_powerup(struct device *dev, void __iomem *base,
0190              unsigned int freq);
0191 void imgu_css_set_powerdown(struct device *dev, void __iomem *base);
0192 int imgu_css_irq_ack(struct imgu_css *css);
0193
0194 /******************* set parameters ************/
0195 int imgu_css_set_parameters(struct imgu_css *css, unsigned int pipe,
0196                 struct ipu3_uapi_params *set_params);
0197
0198 /******************* auxiliary helpers *******************/
0199 static inline enum imgu_css_buffer_state
0200 imgu_css_buf_state(struct imgu_css_buffer *b)
0201 {
0202     return b->state;
0203 }
0204
0205 /* Initialize given buffer. May be called several times. */
0206 static inline void imgu_css_buf_init(struct imgu_css_buffer *b,
0207                      unsigned int queue, dma_addr_t daddr)
0208 {
0209     b->state = IPU3_CSS_BUFFER_NEW;
0210     b->queue = queue;
0211     b->daddr = daddr;
0212 }
0213 #endif