media/ipu3/ipu3-css-fw.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /* Copyright (C) 2018 Intel Corporation */
0003
0004 #ifndef __IPU3_CSS_FW_H
0005 #define __IPU3_CSS_FW_H
0006
0007 /******************* Firmware file definitions *******************/
0008
0009 #define IMGU_FW_NAME        "intel/ipu3-fw.bin"
0010 #define IMGU_FW_NAME_20161208   \
0011     "intel/irci_irci_ecr-master_20161208_0213_20170112_1500.bin"
0012
0013 typedef u32 imgu_fw_ptr;
0014
0015 enum imgu_fw_type {
0016     IMGU_FW_SP_FIRMWARE,    /* Firmware for the SP */
0017     IMGU_FW_SP1_FIRMWARE,   /* Firmware for the SP1 */
0018     IMGU_FW_ISP_FIRMWARE,   /* Firmware for the ISP */
0019     IMGU_FW_BOOTLOADER_FIRMWARE,    /* Firmware for the BootLoader */
0020     IMGU_FW_ACC_FIRMWARE    /* Firmware for accelerations */
0021 };
0022
0023 enum imgu_fw_acc_type {
0024     IMGU_FW_ACC_NONE,   /* Normal binary */
0025     IMGU_FW_ACC_OUTPUT, /* Accelerator stage on output frame */
0026     IMGU_FW_ACC_VIEWFINDER, /* Accelerator stage on viewfinder frame */
0027     IMGU_FW_ACC_STANDALONE, /* Stand-alone acceleration */
0028 };
0029
0030 struct imgu_fw_isp_parameter {
0031     u32 offset;     /* Offset in isp_<mem> config, params, etc. */
0032     u32 size;       /* Disabled if 0 */
0033 };
0034
0035 struct imgu_fw_param_memory_offsets {
0036     struct {
0037         struct imgu_fw_isp_parameter lin;   /* lin_vmem_params */
0038         struct imgu_fw_isp_parameter tnr3;  /* tnr3_vmem_params */
0039         struct imgu_fw_isp_parameter xnr3;  /* xnr3_vmem_params */
0040     } vmem;
0041     struct {
0042         struct imgu_fw_isp_parameter tnr;
0043         struct imgu_fw_isp_parameter tnr3;  /* tnr3_params */
0044         struct imgu_fw_isp_parameter xnr3;  /* xnr3_params */
0045         struct imgu_fw_isp_parameter plane_io_config;   /* 192 bytes */
0046         struct imgu_fw_isp_parameter rgbir; /* rgbir_params */
0047     } dmem;
0048 };
0049
0050 struct imgu_fw_config_memory_offsets {
0051     struct {
0052         struct imgu_fw_isp_parameter iterator;
0053         struct imgu_fw_isp_parameter dvs;
0054         struct imgu_fw_isp_parameter output;
0055         struct imgu_fw_isp_parameter raw;
0056         struct imgu_fw_isp_parameter input_yuv;
0057         struct imgu_fw_isp_parameter tnr;
0058         struct imgu_fw_isp_parameter tnr3;
0059         struct imgu_fw_isp_parameter ref;
0060     } dmem;
0061 };
0062
0063 struct imgu_fw_state_memory_offsets {
0064     struct {
0065         struct imgu_fw_isp_parameter tnr;
0066         struct imgu_fw_isp_parameter tnr3;
0067         struct imgu_fw_isp_parameter ref;
0068     } dmem;
0069 };
0070
0071 union imgu_fw_all_memory_offsets {
0072     struct {
0073         u64 imgu_fw_mem_offsets[3]; /* params, config, state */
0074     } offsets;
0075     struct {
0076         u64 ptr;
0077     } array[IMGU_ABI_PARAM_CLASS_NUM];
0078 };
0079
0080 struct imgu_fw_binary_xinfo {
0081     /* Part that is of interest to the SP. */
0082     struct imgu_abi_binary_info sp;
0083
0084     /* Rest of the binary info, only interesting to the host. */
0085     u32 type;   /* enum imgu_fw_acc_type */
0086
0087     u32 num_output_formats __aligned(8);
0088     u32 output_formats[IMGU_ABI_FRAME_FORMAT_NUM];  /* enum frame_format */
0089
0090     /* number of supported vf formats */
0091     u32 num_vf_formats __aligned(8);
0092     /* types of supported vf formats */
0093     u32 vf_formats[IMGU_ABI_FRAME_FORMAT_NUM];  /* enum frame_format */
0094     u8 num_output_pins;
0095     imgu_fw_ptr xmem_addr;
0096
0097     u64 imgu_fw_blob_descr_ptr __aligned(8);
0098     u32 blob_index __aligned(8);
0099     union imgu_fw_all_memory_offsets mem_offsets __aligned(8);
0100     struct imgu_fw_binary_xinfo *next __aligned(8);
0101 };
0102
0103 struct imgu_fw_sp_info {
0104     u32 init_dmem_data; /* data sect config, stored to dmem */
0105     u32 per_frame_data; /* Per frame data, stored to dmem */
0106     u32 group;      /* Per pipeline data, loaded by dma */
0107     u32 output;     /* SP output data, loaded by dmem */
0108     u32 host_sp_queue;  /* Host <-> SP queues */
0109     u32 host_sp_com;    /* Host <-> SP commands */
0110     u32 isp_started;    /* P'ed from sensor thread, csim only */
0111     u32 sw_state;       /* Polled from css, enum imgu_abi_sp_swstate */
0112     u32 host_sp_queues_initialized; /* Polled from the SP */
0113     u32 sleep_mode;     /* different mode to halt SP */
0114     u32 invalidate_tlb; /* inform SP to invalidate mmu TLB */
0115     u32 debug_buffer_ddr_address;   /* the addr of DDR debug queue */
0116
0117     /* input system perf count array */
0118     u32 perf_counter_input_system_error;
0119     u32 threads_stack;  /* sp thread's stack pointers */
0120     u32 threads_stack_size; /* sp thread's stack sizes */
0121     u32 curr_binary_id; /* current binary id */
0122     u32 raw_copy_line_count;    /* raw copy line counter */
0123     u32 ddr_parameter_address;  /* acc param ddrptr, sp dmem */
0124     u32 ddr_parameter_size; /* acc param size, sp dmem */
0125     /* Entry functions */
0126     u32 sp_entry;       /* The SP entry function */
0127     u32 tagger_frames_addr; /* Base address of tagger state */
0128 };
0129
0130 struct imgu_fw_bl_info {
0131     u32 num_dma_cmds;   /* Number of cmds sent by CSS */
0132     u32 dma_cmd_list;   /* Dma command list sent by CSS */
0133     u32 sw_state;       /* Polled from css, enum imgu_abi_bl_swstate */
0134     /* Entry functions */
0135     u32 bl_entry;       /* The SP entry function */
0136 };
0137
0138 struct imgu_fw_acc_info {
0139     u32 per_frame_data; /* Dummy for now */
0140 };
0141
0142 union imgu_fw_union {
0143     struct imgu_fw_binary_xinfo isp;    /* ISP info */
0144     struct imgu_fw_sp_info sp;  /* SP info */
0145     struct imgu_fw_sp_info sp1; /* SP1 info */
0146     struct imgu_fw_bl_info bl;  /* Bootloader info */
0147     struct imgu_fw_acc_info acc;    /* Accelerator info */
0148 };
0149
0150 struct imgu_fw_info {
0151     size_t header_size; /* size of fw header */
0152     u32 type __aligned(8);  /* enum imgu_fw_type */
0153
0154     union imgu_fw_union info;   /* Binary info */
0155     struct imgu_abi_blob_info blob; /* Blob info */
0156     /* Dynamic part */
0157     u64 next;
0158
0159     u32 loaded __aligned(8);    /* Firmware has been loaded */
0160     const u64 isp_code __aligned(8);    /* ISP pointer to code */
0161     /* Firmware handle between user space and kernel */
0162     u32 handle __aligned(8);
0163     /* Sections to copy from/to ISP */
0164     struct imgu_abi_isp_param_segments mem_initializers;
0165     /* Initializer for local ISP memories */
0166 };
0167
0168 struct imgu_fw_bi_file_h {
0169     char version[64];   /* branch tag + week day + time */
0170     int binary_nr;      /* Number of binaries */
0171     unsigned int h_size;    /* sizeof(struct imgu_fw_bi_file_h) */
0172 };
0173
0174 struct imgu_fw_header {
0175     struct imgu_fw_bi_file_h file_header;
0176     struct imgu_fw_info binary_header[];    /* binary_nr items */
0177 };
0178
0179 /******************* Firmware functions *******************/
0180
0181 int imgu_css_fw_init(struct imgu_css *css);
0182 void imgu_css_fw_cleanup(struct imgu_css *css);
0183
0184 unsigned int imgu_css_fw_obgrid_size(const struct imgu_fw_info *bi);
0185 void *imgu_css_fw_pipeline_params(struct imgu_css *css, unsigned int pipe,
0186                   enum imgu_abi_param_class cls,
0187                   enum imgu_abi_memories mem,
0188                   struct imgu_fw_isp_parameter *par,
0189                   size_t par_size, void *binary_params);
0190
0191 #endif