media/hantro/hantro.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * Hantro VPU codec driver
0004  *
0005  * Copyright 2018 Google LLC.
0006  *  Tomasz Figa <tfiga@chromium.org>
0007  *
0008  * Based on s5p-mfc driver by Samsung Electronics Co., Ltd.
0009  * Copyright (C) 2011 Samsung Electronics Co., Ltd.
0010  */
0011
0012 #ifndef HANTRO_H_
0013 #define HANTRO_H_
0014
0015 #include <linux/platform_device.h>
0016 #include <linux/videodev2.h>
0017 #include <linux/wait.h>
0018 #include <linux/clk.h>
0019 #include <linux/reset.h>
0020
0021 #include <media/v4l2-ctrls.h>
0022 #include <media/v4l2-device.h>
0023 #include <media/v4l2-ioctl.h>
0024 #include <media/v4l2-mem2mem.h>
0025 #include <media/videobuf2-core.h>
0026 #include <media/videobuf2-dma-contig.h>
0027
0028 #include "hantro_hw.h"
0029
0030 struct hantro_ctx;
0031 struct hantro_codec_ops;
0032 struct hantro_postproc_ops;
0033
0034 #define HANTRO_JPEG_ENCODER BIT(0)
0035 #define HANTRO_ENCODERS     0x0000ffff
0036 #define HANTRO_MPEG2_DECODER    BIT(16)
0037 #define HANTRO_VP8_DECODER  BIT(17)
0038 #define HANTRO_H264_DECODER BIT(18)
0039 #define HANTRO_HEVC_DECODER BIT(19)
0040 #define HANTRO_VP9_DECODER  BIT(20)
0041 #define HANTRO_DECODERS     0xffff0000
0042
0043 /**
0044  * struct hantro_irq - irq handler and name
0045  *
0046  * @name:           irq name for device tree lookup
0047  * @handler:            interrupt handler
0048  */
0049 struct hantro_irq {
0050     const char *name;
0051     irqreturn_t (*handler)(int irq, void *priv);
0052 };
0053
0054 /**
0055  * struct hantro_variant - information about VPU hardware variant
0056  *
0057  * @enc_offset:         Offset from VPU base to encoder registers.
0058  * @dec_offset:         Offset from VPU base to decoder registers.
0059  * @enc_fmts:           Encoder formats.
0060  * @num_enc_fmts:       Number of encoder formats.
0061  * @dec_fmts:           Decoder formats.
0062  * @num_dec_fmts:       Number of decoder formats.
0063  * @postproc_fmts:      Post-processor formats.
0064  * @num_postproc_fmts:      Number of post-processor formats.
0065  * @postproc_ops:       Post-processor ops.
0066  * @codec:          Supported codecs
0067  * @codec_ops:          Codec ops.
0068  * @init:           Initialize hardware, optional.
0069  * @runtime_resume:     reenable hardware after power gating, optional.
0070  * @irqs:           array of irq names and interrupt handlers
0071  * @num_irqs:           number of irqs in the array
0072  * @clk_names:          array of clock names
0073  * @num_clocks:         number of clocks in the array
0074  * @reg_names:          array of register range names
0075  * @num_regs:           number of register range names in the array
0076  * @double_buffer:      core needs double buffering
0077  * @legacy_regs:        core uses legacy register set
0078  * @late_postproc:      postproc must be set up at the end of the job
0079  */
0080 struct hantro_variant {
0081     unsigned int enc_offset;
0082     unsigned int dec_offset;
0083     const struct hantro_fmt *enc_fmts;
0084     unsigned int num_enc_fmts;
0085     const struct hantro_fmt *dec_fmts;
0086     unsigned int num_dec_fmts;
0087     const struct hantro_fmt *postproc_fmts;
0088     unsigned int num_postproc_fmts;
0089     const struct hantro_postproc_ops *postproc_ops;
0090     unsigned int codec;
0091     const struct hantro_codec_ops *codec_ops;
0092     int (*init)(struct hantro_dev *vpu);
0093     int (*runtime_resume)(struct hantro_dev *vpu);
0094     const struct hantro_irq *irqs;
0095     int num_irqs;
0096     const char * const *clk_names;
0097     int num_clocks;
0098     const char * const *reg_names;
0099     int num_regs;
0100     unsigned int double_buffer : 1;
0101     unsigned int legacy_regs : 1;
0102     unsigned int late_postproc : 1;
0103 };
0104
0105 /**
0106  * enum hantro_codec_mode - codec operating mode.
0107  * @HANTRO_MODE_NONE:  No operating mode. Used for RAW video formats.
0108  * @HANTRO_MODE_JPEG_ENC: JPEG encoder.
0109  * @HANTRO_MODE_H264_DEC: H264 decoder.
0110  * @HANTRO_MODE_MPEG2_DEC: MPEG-2 decoder.
0111  * @HANTRO_MODE_VP8_DEC: VP8 decoder.
0112  * @HANTRO_MODE_HEVC_DEC: HEVC decoder.
0113  * @HANTRO_MODE_VP9_DEC: VP9 decoder.
0114  */
0115 enum hantro_codec_mode {
0116     HANTRO_MODE_NONE = -1,
0117     HANTRO_MODE_JPEG_ENC,
0118     HANTRO_MODE_H264_DEC,
0119     HANTRO_MODE_MPEG2_DEC,
0120     HANTRO_MODE_VP8_DEC,
0121     HANTRO_MODE_HEVC_DEC,
0122     HANTRO_MODE_VP9_DEC,
0123 };
0124
0125 /*
0126  * struct hantro_ctrl - helper type to declare supported controls
0127  * @codec:  codec id this control belong to (HANTRO_JPEG_ENCODER, etc.)
0128  * @cfg:    control configuration
0129  */
0130 struct hantro_ctrl {
0131     unsigned int codec;
0132     struct v4l2_ctrl_config cfg;
0133 };
0134
0135 /*
0136  * struct hantro_func - Hantro VPU functionality
0137  *
0138  * @id:         processing functionality ID (can be
0139  *          %MEDIA_ENT_F_PROC_VIDEO_ENCODER or
0140  *          %MEDIA_ENT_F_PROC_VIDEO_DECODER)
0141  * @vdev:       &struct video_device that exposes the encoder or
0142  *          decoder functionality
0143  * @source_pad:     &struct media_pad with the source pad.
0144  * @sink:       &struct media_entity pointer with the sink entity
0145  * @sink_pad:       &struct media_pad with the sink pad.
0146  * @proc:       &struct media_entity pointer with the M2M device itself.
0147  * @proc_pads:      &struct media_pad with the @proc pads.
0148  * @intf_devnode:   &struct media_intf devnode pointer with the interface
0149  *          with controls the M2M device.
0150  *
0151  * Contains everything needed to attach the video device to the media device.
0152  */
0153 struct hantro_func {
0154     unsigned int id;
0155     struct video_device vdev;
0156     struct media_pad source_pad;
0157     struct media_entity sink;
0158     struct media_pad sink_pad;
0159     struct media_entity proc;
0160     struct media_pad proc_pads[2];
0161     struct media_intf_devnode *intf_devnode;
0162 };
0163
0164 static inline struct hantro_func *
0165 hantro_vdev_to_func(struct video_device *vdev)
0166 {
0167     return container_of(vdev, struct hantro_func, vdev);
0168 }
0169
0170 /**
0171  * struct hantro_dev - driver data
0172  * @v4l2_dev:       V4L2 device to register video devices for.
0173  * @m2m_dev:        mem2mem device associated to this device.
0174  * @mdev:       media device associated to this device.
0175  * @encoder:        encoder functionality.
0176  * @decoder:        decoder functionality.
0177  * @pdev:       Pointer to VPU platform device.
0178  * @dev:        Pointer to device for convenient logging using
0179  *          dev_ macros.
0180  * @clocks:     Array of clock handles.
0181  * @resets:     Array of reset handles.
0182  * @reg_bases:      Mapped addresses of VPU registers.
0183  * @enc_base:       Mapped address of VPU encoder register for convenience.
0184  * @dec_base:       Mapped address of VPU decoder register for convenience.
0185  * @ctrl_base:      Mapped address of VPU control block.
0186  * @vpu_mutex:      Mutex to synchronize V4L2 calls.
0187  * @irqlock:        Spinlock to synchronize access to data structures
0188  *          shared with interrupt handlers.
0189  * @variant:        Hardware variant-specific parameters.
0190  * @watchdog_work:  Delayed work for hardware timeout handling.
0191  */
0192 struct hantro_dev {
0193     struct v4l2_device v4l2_dev;
0194     struct v4l2_m2m_dev *m2m_dev;
0195     struct media_device mdev;
0196     struct hantro_func *encoder;
0197     struct hantro_func *decoder;
0198     struct platform_device *pdev;
0199     struct device *dev;
0200     struct clk_bulk_data *clocks;
0201     struct reset_control *resets;
0202     void __iomem **reg_bases;
0203     void __iomem *enc_base;
0204     void __iomem *dec_base;
0205     void __iomem *ctrl_base;
0206
0207     struct mutex vpu_mutex; /* video_device lock */
0208     spinlock_t irqlock;
0209     const struct hantro_variant *variant;
0210     struct delayed_work watchdog_work;
0211 };
0212
0213 /**
0214  * struct hantro_ctx - Context (instance) private data.
0215  *
0216  * @dev:        VPU driver data to which the context belongs.
0217  * @fh:         V4L2 file handler.
0218  * @is_encoder:     Decoder or encoder context?
0219  *
0220  * @sequence_cap:       Sequence counter for capture queue
0221  * @sequence_out:       Sequence counter for output queue
0222  *
0223  * @vpu_src_fmt:    Descriptor of active source format.
0224  * @src_fmt:        V4L2 pixel format of active source format.
0225  * @vpu_dst_fmt:    Descriptor of active destination format.
0226  * @dst_fmt:        V4L2 pixel format of active destination format.
0227  *
0228  * @ctrl_handler:   Control handler used to register controls.
0229  * @jpeg_quality:   User-specified JPEG compression quality.
0230  * @bit_depth:      Bit depth of current frame
0231  *
0232  * @codec_ops:      Set of operations related to codec mode.
0233  * @postproc:       Post-processing context.
0234  * @h264_dec:       H.264-decoding context.
0235  * @jpeg_enc:       JPEG-encoding context.
0236  * @mpeg2_dec:      MPEG-2-decoding context.
0237  * @vp8_dec:        VP8-decoding context.
0238  * @hevc_dec:       HEVC-decoding context.
0239  * @vp9_dec:        VP9-decoding context.
0240  */
0241 struct hantro_ctx {
0242     struct hantro_dev *dev;
0243     struct v4l2_fh fh;
0244     bool is_encoder;
0245
0246     u32 sequence_cap;
0247     u32 sequence_out;
0248
0249     const struct hantro_fmt *vpu_src_fmt;
0250     struct v4l2_pix_format_mplane src_fmt;
0251     const struct hantro_fmt *vpu_dst_fmt;
0252     struct v4l2_pix_format_mplane dst_fmt;
0253
0254     struct v4l2_ctrl_handler ctrl_handler;
0255     int jpeg_quality;
0256     int bit_depth;
0257
0258     const struct hantro_codec_ops *codec_ops;
0259     struct hantro_postproc_ctx postproc;
0260
0261     /* Specific for particular codec modes. */
0262     union {
0263         struct hantro_h264_dec_hw_ctx h264_dec;
0264         struct hantro_mpeg2_dec_hw_ctx mpeg2_dec;
0265         struct hantro_vp8_dec_hw_ctx vp8_dec;
0266         struct hantro_hevc_dec_hw_ctx hevc_dec;
0267         struct hantro_vp9_dec_hw_ctx vp9_dec;
0268     };
0269 };
0270
0271 /**
0272  * struct hantro_fmt - information about supported video formats.
0273  * @name:   Human readable name of the format.
0274  * @fourcc: FourCC code of the format. See V4L2_PIX_FMT_*.
0275  * @codec_mode: Codec mode related to this format. See
0276  *      enum hantro_codec_mode.
0277  * @header_size: Optional header size. Currently used by JPEG encoder.
0278  * @max_depth:  Maximum depth, for bitstream formats
0279  * @enc_fmt:    Format identifier for encoder registers.
0280  * @frmsize:    Supported range of frame sizes (only for bitstream formats).
0281  * @postprocessed: Indicates if this format needs the post-processor.
0282  * @match_depth: Indicates if format bit depth must match video bit depth
0283  */
0284 struct hantro_fmt {
0285     char *name;
0286     u32 fourcc;
0287     enum hantro_codec_mode codec_mode;
0288     int header_size;
0289     int max_depth;
0290     enum hantro_enc_fmt enc_fmt;
0291     struct v4l2_frmsize_stepwise frmsize;
0292     bool postprocessed;
0293     bool match_depth;
0294 };
0295
0296 struct hantro_reg {
0297     u32 base;
0298     u32 shift;
0299     u32 mask;
0300 };
0301
0302 struct hantro_postproc_regs {
0303     struct hantro_reg pipeline_en;
0304     struct hantro_reg max_burst;
0305     struct hantro_reg clk_gate;
0306     struct hantro_reg out_swap32;
0307     struct hantro_reg out_endian;
0308     struct hantro_reg out_luma_base;
0309     struct hantro_reg input_width;
0310     struct hantro_reg input_height;
0311     struct hantro_reg output_width;
0312     struct hantro_reg output_height;
0313     struct hantro_reg input_fmt;
0314     struct hantro_reg output_fmt;
0315     struct hantro_reg orig_width;
0316     struct hantro_reg display_width;
0317 };
0318
0319 struct hantro_vp9_decoded_buffer_info {
0320     /* Info needed when the decoded frame serves as a reference frame. */
0321     unsigned short width;
0322     unsigned short height;
0323     u32 bit_depth : 4;
0324 };
0325
0326 struct hantro_decoded_buffer {
0327     /* Must be the first field in this struct. */
0328     struct v4l2_m2m_buffer base;
0329
0330     union {
0331         struct hantro_vp9_decoded_buffer_info vp9;
0332     };
0333 };
0334
0335 /* Logging helpers */
0336
0337 /**
0338  * DOC: hantro_debug: Module parameter to control level of debugging messages.
0339  *
0340  * Level of debugging messages can be controlled by bits of
0341  * module parameter called "debug". Meaning of particular
0342  * bits is as follows:
0343  *
0344  * bit 0 - global information: mode, size, init, release
0345  * bit 1 - each run start/result information
0346  * bit 2 - contents of small controls from userspace
0347  * bit 3 - contents of big controls from userspace
0348  * bit 4 - detail fmt, ctrl, buffer q/dq information
0349  * bit 5 - detail function enter/leave trace information
0350  * bit 6 - register write/read information
0351  */
0352 extern int hantro_debug;
0353
0354 #define vpu_debug(level, fmt, args...)              \
0355     do {                            \
0356         if (hantro_debug & BIT(level))      \
0357             pr_info("%s:%d: " fmt,                  \
0358                  __func__, __LINE__, ##args);   \
0359     } while (0)
0360
0361 #define vpu_err(fmt, args...)                   \
0362     pr_err("%s:%d: " fmt, __func__, __LINE__, ##args)
0363
0364 /* Structure access helpers. */
0365 static inline struct hantro_ctx *fh_to_ctx(struct v4l2_fh *fh)
0366 {
0367     return container_of(fh, struct hantro_ctx, fh);
0368 }
0369
0370 /* Register accessors. */
0371 static inline void vepu_write_relaxed(struct hantro_dev *vpu,
0372                       u32 val, u32 reg)
0373 {
0374     vpu_debug(6, "0x%04x = 0x%08x\n", reg / 4, val);
0375     writel_relaxed(val, vpu->enc_base + reg);
0376 }
0377
0378 static inline void vepu_write(struct hantro_dev *vpu, u32 val, u32 reg)
0379 {
0380     vpu_debug(6, "0x%04x = 0x%08x\n", reg / 4, val);
0381     writel(val, vpu->enc_base + reg);
0382 }
0383
0384 static inline u32 vepu_read(struct hantro_dev *vpu, u32 reg)
0385 {
0386     u32 val = readl(vpu->enc_base + reg);
0387
0388     vpu_debug(6, "0x%04x = 0x%08x\n", reg / 4, val);
0389     return val;
0390 }
0391
0392 static inline void vdpu_write_relaxed(struct hantro_dev *vpu,
0393                       u32 val, u32 reg)
0394 {
0395     vpu_debug(6, "0x%04x = 0x%08x\n", reg / 4, val);
0396     writel_relaxed(val, vpu->dec_base + reg);
0397 }
0398
0399 static inline void vdpu_write(struct hantro_dev *vpu, u32 val, u32 reg)
0400 {
0401     vpu_debug(6, "0x%04x = 0x%08x\n", reg / 4, val);
0402     writel(val, vpu->dec_base + reg);
0403 }
0404
0405 static inline void hantro_write_addr(struct hantro_dev *vpu,
0406                      unsigned long offset,
0407                      dma_addr_t addr)
0408 {
0409     vdpu_write(vpu, addr & 0xffffffff, offset);
0410 }
0411
0412 static inline u32 vdpu_read(struct hantro_dev *vpu, u32 reg)
0413 {
0414     u32 val = readl(vpu->dec_base + reg);
0415
0416     vpu_debug(6, "0x%04x = 0x%08x\n", reg / 4, val);
0417     return val;
0418 }
0419
0420 static inline u32 vdpu_read_mask(struct hantro_dev *vpu,
0421                  const struct hantro_reg *reg,
0422                  u32 val)
0423 {
0424     u32 v;
0425
0426     v = vdpu_read(vpu, reg->base);
0427     v &= ~(reg->mask << reg->shift);
0428     v |= ((val & reg->mask) << reg->shift);
0429     return v;
0430 }
0431
0432 static inline void hantro_reg_write(struct hantro_dev *vpu,
0433                     const struct hantro_reg *reg,
0434                     u32 val)
0435 {
0436     vdpu_write_relaxed(vpu, vdpu_read_mask(vpu, reg, val), reg->base);
0437 }
0438
0439 static inline void hantro_reg_write_s(struct hantro_dev *vpu,
0440                       const struct hantro_reg *reg,
0441                       u32 val)
0442 {
0443     vdpu_write(vpu, vdpu_read_mask(vpu, reg, val), reg->base);
0444 }
0445
0446 void *hantro_get_ctrl(struct hantro_ctx *ctx, u32 id);
0447 dma_addr_t hantro_get_ref(struct hantro_ctx *ctx, u64 ts);
0448
0449 static inline struct vb2_v4l2_buffer *
0450 hantro_get_src_buf(struct hantro_ctx *ctx)
0451 {
0452     return v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx);
0453 }
0454
0455 static inline struct vb2_v4l2_buffer *
0456 hantro_get_dst_buf(struct hantro_ctx *ctx)
0457 {
0458     return v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
0459 }
0460
0461 bool hantro_needs_postproc(const struct hantro_ctx *ctx,
0462                const struct hantro_fmt *fmt);
0463
0464 static inline dma_addr_t
0465 hantro_get_dec_buf_addr(struct hantro_ctx *ctx, struct vb2_buffer *vb)
0466 {
0467     if (hantro_needs_postproc(ctx, ctx->vpu_dst_fmt))
0468         return ctx->postproc.dec_q[vb->index].dma;
0469     return vb2_dma_contig_plane_dma_addr(vb, 0);
0470 }
0471
0472 static inline struct hantro_decoded_buffer *
0473 vb2_to_hantro_decoded_buf(struct vb2_buffer *buf)
0474 {
0475     return container_of(buf, struct hantro_decoded_buffer, base.vb.vb2_buf);
0476 }
0477
0478 void hantro_postproc_disable(struct hantro_ctx *ctx);
0479 void hantro_postproc_enable(struct hantro_ctx *ctx);
0480 void hantro_postproc_free(struct hantro_ctx *ctx);
0481 int hantro_postproc_alloc(struct hantro_ctx *ctx);
0482 int hanto_postproc_enum_framesizes(struct hantro_ctx *ctx,
0483                    struct v4l2_frmsizeenum *fsize);
0484
0485 #endif /* HANTRO_H_ */