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0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * ad2s1210.c support for the ADI Resolver to Digital Converters: AD2S1210
0004  *
0005  * Copyright (c) 2010-2010 Analog Devices Inc.
0006  */
0007 #include <linux/types.h>
0008 #include <linux/mutex.h>
0009 #include <linux/device.h>
0010 #include <linux/spi/spi.h>
0011 #include <linux/slab.h>
0012 #include <linux/sysfs.h>
0013 #include <linux/delay.h>
0014 #include <linux/gpio/consumer.h>
0015 #include <linux/module.h>
0016 
0017 #include <linux/iio/iio.h>
0018 #include <linux/iio/sysfs.h>
0019 
0020 #define DRV_NAME "ad2s1210"
0021 
0022 #define AD2S1210_DEF_CONTROL        0x7E
0023 
0024 #define AD2S1210_MSB_IS_HIGH        0x80
0025 #define AD2S1210_MSB_IS_LOW     0x7F
0026 #define AD2S1210_PHASE_LOCK_RANGE_44    0x20
0027 #define AD2S1210_ENABLE_HYSTERESIS  0x10
0028 #define AD2S1210_SET_ENRES1     0x08
0029 #define AD2S1210_SET_ENRES0     0x04
0030 #define AD2S1210_SET_RES1       0x02
0031 #define AD2S1210_SET_RES0       0x01
0032 
0033 #define AD2S1210_SET_RESOLUTION     (AD2S1210_SET_RES1 | AD2S1210_SET_RES0)
0034 
0035 #define AD2S1210_REG_POSITION       0x80
0036 #define AD2S1210_REG_VELOCITY       0x82
0037 #define AD2S1210_REG_LOS_THRD       0x88
0038 #define AD2S1210_REG_DOS_OVR_THRD   0x89
0039 #define AD2S1210_REG_DOS_MIS_THRD   0x8A
0040 #define AD2S1210_REG_DOS_RST_MAX_THRD   0x8B
0041 #define AD2S1210_REG_DOS_RST_MIN_THRD   0x8C
0042 #define AD2S1210_REG_LOT_HIGH_THRD  0x8D
0043 #define AD2S1210_REG_LOT_LOW_THRD   0x8E
0044 #define AD2S1210_REG_EXCIT_FREQ     0x91
0045 #define AD2S1210_REG_CONTROL        0x92
0046 #define AD2S1210_REG_SOFT_RESET     0xF0
0047 #define AD2S1210_REG_FAULT      0xFF
0048 
0049 #define AD2S1210_MIN_CLKIN  6144000
0050 #define AD2S1210_MAX_CLKIN  10240000
0051 #define AD2S1210_MIN_EXCIT  2000
0052 #define AD2S1210_MAX_EXCIT  20000
0053 #define AD2S1210_MIN_FCW    0x4
0054 #define AD2S1210_MAX_FCW    0x50
0055 
0056 #define AD2S1210_DEF_EXCIT  10000
0057 
0058 enum ad2s1210_mode {
0059     MOD_POS = 0,
0060     MOD_VEL,
0061     MOD_CONFIG,
0062     MOD_RESERVED,
0063 };
0064 
0065 enum ad2s1210_gpios {
0066     AD2S1210_SAMPLE,
0067     AD2S1210_A0,
0068     AD2S1210_A1,
0069     AD2S1210_RES0,
0070     AD2S1210_RES1,
0071 };
0072 
0073 struct ad2s1210_gpio {
0074     const char *name;
0075     unsigned long flags;
0076 };
0077 
0078 static const struct ad2s1210_gpio gpios[] = {
0079     [AD2S1210_SAMPLE] = { .name = "adi,sample", .flags = GPIOD_OUT_LOW },
0080     [AD2S1210_A0] = { .name = "adi,a0", .flags = GPIOD_OUT_LOW },
0081     [AD2S1210_A1] = { .name = "adi,a1", .flags = GPIOD_OUT_LOW },
0082     [AD2S1210_RES0] = { .name = "adi,res0", .flags = GPIOD_OUT_LOW },
0083     [AD2S1210_RES1] = { .name = "adi,res1", .flags = GPIOD_OUT_LOW },
0084 };
0085 
0086 static const unsigned int ad2s1210_resolution_value[] = { 10, 12, 14, 16 };
0087 
0088 struct ad2s1210_state {
0089     struct mutex lock;
0090     struct spi_device *sdev;
0091     struct gpio_desc *gpios[5];
0092     unsigned int fclkin;
0093     unsigned int fexcit;
0094     bool hysteresis;
0095     u8 resolution;
0096     enum ad2s1210_mode mode;
0097     u8 rx[2] ____cacheline_aligned;
0098     u8 tx[2] ____cacheline_aligned;
0099 };
0100 
0101 static const int ad2s1210_mode_vals[4][2] = {
0102     [MOD_POS] = { 0, 0 },
0103     [MOD_VEL] = { 0, 1 },
0104     [MOD_CONFIG] = { 1, 0 },
0105 };
0106 
0107 static inline void ad2s1210_set_mode(enum ad2s1210_mode mode,
0108                      struct ad2s1210_state *st)
0109 {
0110     gpiod_set_value(st->gpios[AD2S1210_A0], ad2s1210_mode_vals[mode][0]);
0111     gpiod_set_value(st->gpios[AD2S1210_A1], ad2s1210_mode_vals[mode][1]);
0112     st->mode = mode;
0113 }
0114 
0115 /* write 1 bytes (address or data) to the chip */
0116 static int ad2s1210_config_write(struct ad2s1210_state *st, u8 data)
0117 {
0118     int ret;
0119 
0120     ad2s1210_set_mode(MOD_CONFIG, st);
0121     st->tx[0] = data;
0122     ret = spi_write(st->sdev, st->tx, 1);
0123     if (ret < 0)
0124         return ret;
0125 
0126     return 0;
0127 }
0128 
0129 /* read value from one of the registers */
0130 static int ad2s1210_config_read(struct ad2s1210_state *st,
0131                 unsigned char address)
0132 {
0133     struct spi_transfer xfers[] = {
0134         {
0135             .len = 1,
0136             .rx_buf = &st->rx[0],
0137             .tx_buf = &st->tx[0],
0138             .cs_change = 1,
0139         }, {
0140             .len = 1,
0141             .rx_buf = &st->rx[1],
0142             .tx_buf = &st->tx[1],
0143         },
0144     };
0145     int ret = 0;
0146 
0147     ad2s1210_set_mode(MOD_CONFIG, st);
0148     st->tx[0] = address | AD2S1210_MSB_IS_HIGH;
0149     st->tx[1] = AD2S1210_REG_FAULT;
0150     ret = spi_sync_transfer(st->sdev, xfers, 2);
0151     if (ret < 0)
0152         return ret;
0153 
0154     return st->rx[1];
0155 }
0156 
0157 static inline
0158 int ad2s1210_update_frequency_control_word(struct ad2s1210_state *st)
0159 {
0160     int ret;
0161     unsigned char fcw;
0162 
0163     fcw = (unsigned char)(st->fexcit * (1 << 15) / st->fclkin);
0164     if (fcw < AD2S1210_MIN_FCW || fcw > AD2S1210_MAX_FCW) {
0165         dev_err(&st->sdev->dev, "ad2s1210: FCW out of range\n");
0166         return -ERANGE;
0167     }
0168 
0169     ret = ad2s1210_config_write(st, AD2S1210_REG_EXCIT_FREQ);
0170     if (ret < 0)
0171         return ret;
0172 
0173     return ad2s1210_config_write(st, fcw);
0174 }
0175 
0176 static const int ad2s1210_res_pins[4][2] = {
0177     { 0, 0 }, {0, 1}, {1, 0}, {1, 1}
0178 };
0179 
0180 static inline void ad2s1210_set_resolution_pin(struct ad2s1210_state *st)
0181 {
0182     gpiod_set_value(st->gpios[AD2S1210_RES0],
0183             ad2s1210_res_pins[(st->resolution - 10) / 2][0]);
0184     gpiod_set_value(st->gpios[AD2S1210_RES1],
0185             ad2s1210_res_pins[(st->resolution - 10) / 2][1]);
0186 }
0187 
0188 static inline int ad2s1210_soft_reset(struct ad2s1210_state *st)
0189 {
0190     int ret;
0191 
0192     ret = ad2s1210_config_write(st, AD2S1210_REG_SOFT_RESET);
0193     if (ret < 0)
0194         return ret;
0195 
0196     return ad2s1210_config_write(st, 0x0);
0197 }
0198 
0199 static ssize_t ad2s1210_show_fclkin(struct device *dev,
0200                     struct device_attribute *attr,
0201                     char *buf)
0202 {
0203     struct ad2s1210_state *st = iio_priv(dev_to_iio_dev(dev));
0204 
0205     return sprintf(buf, "%u\n", st->fclkin);
0206 }
0207 
0208 static ssize_t ad2s1210_store_fclkin(struct device *dev,
0209                      struct device_attribute *attr,
0210                      const char *buf,
0211                      size_t len)
0212 {
0213     struct ad2s1210_state *st = iio_priv(dev_to_iio_dev(dev));
0214     unsigned int fclkin;
0215     int ret;
0216 
0217     ret = kstrtouint(buf, 10, &fclkin);
0218     if (ret)
0219         return ret;
0220     if (fclkin < AD2S1210_MIN_CLKIN || fclkin > AD2S1210_MAX_CLKIN) {
0221         dev_err(dev, "ad2s1210: fclkin out of range\n");
0222         return -EINVAL;
0223     }
0224 
0225     mutex_lock(&st->lock);
0226     st->fclkin = fclkin;
0227 
0228     ret = ad2s1210_update_frequency_control_word(st);
0229     if (ret < 0)
0230         goto error_ret;
0231     ret = ad2s1210_soft_reset(st);
0232 error_ret:
0233     mutex_unlock(&st->lock);
0234 
0235     return ret < 0 ? ret : len;
0236 }
0237 
0238 static ssize_t ad2s1210_show_fexcit(struct device *dev,
0239                     struct device_attribute *attr,
0240                     char *buf)
0241 {
0242     struct ad2s1210_state *st = iio_priv(dev_to_iio_dev(dev));
0243 
0244     return sprintf(buf, "%u\n", st->fexcit);
0245 }
0246 
0247 static ssize_t ad2s1210_store_fexcit(struct device *dev,
0248                      struct device_attribute *attr,
0249                      const char *buf, size_t len)
0250 {
0251     struct ad2s1210_state *st = iio_priv(dev_to_iio_dev(dev));
0252     unsigned int fexcit;
0253     int ret;
0254 
0255     ret = kstrtouint(buf, 10, &fexcit);
0256     if (ret < 0)
0257         return ret;
0258     if (fexcit < AD2S1210_MIN_EXCIT || fexcit > AD2S1210_MAX_EXCIT) {
0259         dev_err(dev,
0260             "ad2s1210: excitation frequency out of range\n");
0261         return -EINVAL;
0262     }
0263     mutex_lock(&st->lock);
0264     st->fexcit = fexcit;
0265     ret = ad2s1210_update_frequency_control_word(st);
0266     if (ret < 0)
0267         goto error_ret;
0268     ret = ad2s1210_soft_reset(st);
0269 error_ret:
0270     mutex_unlock(&st->lock);
0271 
0272     return ret < 0 ? ret : len;
0273 }
0274 
0275 static ssize_t ad2s1210_show_control(struct device *dev,
0276                      struct device_attribute *attr,
0277                      char *buf)
0278 {
0279     struct ad2s1210_state *st = iio_priv(dev_to_iio_dev(dev));
0280     int ret;
0281 
0282     mutex_lock(&st->lock);
0283     ret = ad2s1210_config_read(st, AD2S1210_REG_CONTROL);
0284     mutex_unlock(&st->lock);
0285     return ret < 0 ? ret : sprintf(buf, "0x%x\n", ret);
0286 }
0287 
0288 static ssize_t ad2s1210_store_control(struct device *dev,
0289                       struct device_attribute *attr,
0290                       const char *buf, size_t len)
0291 {
0292     struct ad2s1210_state *st = iio_priv(dev_to_iio_dev(dev));
0293     unsigned char udata;
0294     unsigned char data;
0295     int ret;
0296 
0297     ret = kstrtou8(buf, 16, &udata);
0298     if (ret)
0299         return -EINVAL;
0300 
0301     mutex_lock(&st->lock);
0302     ret = ad2s1210_config_write(st, AD2S1210_REG_CONTROL);
0303     if (ret < 0)
0304         goto error_ret;
0305     data = udata & AD2S1210_MSB_IS_LOW;
0306     ret = ad2s1210_config_write(st, data);
0307     if (ret < 0)
0308         goto error_ret;
0309 
0310     ret = ad2s1210_config_read(st, AD2S1210_REG_CONTROL);
0311     if (ret < 0)
0312         goto error_ret;
0313     if (ret & AD2S1210_MSB_IS_HIGH) {
0314         ret = -EIO;
0315         dev_err(dev,
0316             "ad2s1210: write control register fail\n");
0317         goto error_ret;
0318     }
0319     st->resolution =
0320         ad2s1210_resolution_value[data & AD2S1210_SET_RESOLUTION];
0321     ad2s1210_set_resolution_pin(st);
0322     ret = len;
0323     st->hysteresis = !!(data & AD2S1210_ENABLE_HYSTERESIS);
0324 
0325 error_ret:
0326     mutex_unlock(&st->lock);
0327     return ret;
0328 }
0329 
0330 static ssize_t ad2s1210_show_resolution(struct device *dev,
0331                     struct device_attribute *attr,
0332                     char *buf)
0333 {
0334     struct ad2s1210_state *st = iio_priv(dev_to_iio_dev(dev));
0335 
0336     return sprintf(buf, "%d\n", st->resolution);
0337 }
0338 
0339 static ssize_t ad2s1210_store_resolution(struct device *dev,
0340                      struct device_attribute *attr,
0341                      const char *buf, size_t len)
0342 {
0343     struct ad2s1210_state *st = iio_priv(dev_to_iio_dev(dev));
0344     unsigned char data;
0345     unsigned char udata;
0346     int ret;
0347 
0348     ret = kstrtou8(buf, 10, &udata);
0349     if (ret || udata < 10 || udata > 16) {
0350         dev_err(dev, "ad2s1210: resolution out of range\n");
0351         return -EINVAL;
0352     }
0353     mutex_lock(&st->lock);
0354     ret = ad2s1210_config_read(st, AD2S1210_REG_CONTROL);
0355     if (ret < 0)
0356         goto error_ret;
0357     data = ret;
0358     data &= ~AD2S1210_SET_RESOLUTION;
0359     data |= (udata - 10) >> 1;
0360     ret = ad2s1210_config_write(st, AD2S1210_REG_CONTROL);
0361     if (ret < 0)
0362         goto error_ret;
0363     ret = ad2s1210_config_write(st, data & AD2S1210_MSB_IS_LOW);
0364     if (ret < 0)
0365         goto error_ret;
0366     ret = ad2s1210_config_read(st, AD2S1210_REG_CONTROL);
0367     if (ret < 0)
0368         goto error_ret;
0369     data = ret;
0370     if (data & AD2S1210_MSB_IS_HIGH) {
0371         ret = -EIO;
0372         dev_err(dev, "ad2s1210: setting resolution fail\n");
0373         goto error_ret;
0374     }
0375     st->resolution =
0376         ad2s1210_resolution_value[data & AD2S1210_SET_RESOLUTION];
0377     ad2s1210_set_resolution_pin(st);
0378     ret = len;
0379 error_ret:
0380     mutex_unlock(&st->lock);
0381     return ret;
0382 }
0383 
0384 /* read the fault register since last sample */
0385 static ssize_t ad2s1210_show_fault(struct device *dev,
0386                    struct device_attribute *attr, char *buf)
0387 {
0388     struct ad2s1210_state *st = iio_priv(dev_to_iio_dev(dev));
0389     int ret;
0390 
0391     mutex_lock(&st->lock);
0392     ret = ad2s1210_config_read(st, AD2S1210_REG_FAULT);
0393     mutex_unlock(&st->lock);
0394 
0395     return ret ? ret : sprintf(buf, "0x%x\n", ret);
0396 }
0397 
0398 static ssize_t ad2s1210_clear_fault(struct device *dev,
0399                     struct device_attribute *attr,
0400                     const char *buf,
0401                     size_t len)
0402 {
0403     struct ad2s1210_state *st = iio_priv(dev_to_iio_dev(dev));
0404     int ret;
0405 
0406     mutex_lock(&st->lock);
0407     gpiod_set_value(st->gpios[AD2S1210_SAMPLE], 0);
0408     /* delay (2 * tck + 20) nano seconds */
0409     udelay(1);
0410     gpiod_set_value(st->gpios[AD2S1210_SAMPLE], 1);
0411     ret = ad2s1210_config_read(st, AD2S1210_REG_FAULT);
0412     if (ret < 0)
0413         goto error_ret;
0414     gpiod_set_value(st->gpios[AD2S1210_SAMPLE], 0);
0415     gpiod_set_value(st->gpios[AD2S1210_SAMPLE], 1);
0416 error_ret:
0417     mutex_unlock(&st->lock);
0418 
0419     return ret < 0 ? ret : len;
0420 }
0421 
0422 static ssize_t ad2s1210_show_reg(struct device *dev,
0423                  struct device_attribute *attr,
0424                  char *buf)
0425 {
0426     struct ad2s1210_state *st = iio_priv(dev_to_iio_dev(dev));
0427     struct iio_dev_attr *iattr = to_iio_dev_attr(attr);
0428     int ret;
0429 
0430     mutex_lock(&st->lock);
0431     ret = ad2s1210_config_read(st, iattr->address);
0432     mutex_unlock(&st->lock);
0433 
0434     return ret < 0 ? ret : sprintf(buf, "%d\n", ret);
0435 }
0436 
0437 static ssize_t ad2s1210_store_reg(struct device *dev,
0438                   struct device_attribute *attr,
0439                   const char *buf, size_t len)
0440 {
0441     struct ad2s1210_state *st = iio_priv(dev_to_iio_dev(dev));
0442     unsigned char data;
0443     int ret;
0444     struct iio_dev_attr *iattr = to_iio_dev_attr(attr);
0445 
0446     ret = kstrtou8(buf, 10, &data);
0447     if (ret)
0448         return -EINVAL;
0449     mutex_lock(&st->lock);
0450     ret = ad2s1210_config_write(st, iattr->address);
0451     if (ret < 0)
0452         goto error_ret;
0453     ret = ad2s1210_config_write(st, data & AD2S1210_MSB_IS_LOW);
0454 error_ret:
0455     mutex_unlock(&st->lock);
0456     return ret < 0 ? ret : len;
0457 }
0458 
0459 static int ad2s1210_read_raw(struct iio_dev *indio_dev,
0460                  struct iio_chan_spec const *chan,
0461                  int *val,
0462                  int *val2,
0463                  long m)
0464 {
0465     struct ad2s1210_state *st = iio_priv(indio_dev);
0466     u16 negative;
0467     int ret = 0;
0468     u16 pos;
0469     s16 vel;
0470 
0471     mutex_lock(&st->lock);
0472     gpiod_set_value(st->gpios[AD2S1210_SAMPLE], 0);
0473     /* delay (6 * tck + 20) nano seconds */
0474     udelay(1);
0475 
0476     switch (chan->type) {
0477     case IIO_ANGL:
0478         ad2s1210_set_mode(MOD_POS, st);
0479         break;
0480     case IIO_ANGL_VEL:
0481         ad2s1210_set_mode(MOD_VEL, st);
0482         break;
0483     default:
0484         ret = -EINVAL;
0485         break;
0486     }
0487     if (ret < 0)
0488         goto error_ret;
0489     ret = spi_read(st->sdev, st->rx, 2);
0490     if (ret < 0)
0491         goto error_ret;
0492 
0493     switch (chan->type) {
0494     case IIO_ANGL:
0495         pos = be16_to_cpup((__be16 *)st->rx);
0496         if (st->hysteresis)
0497             pos >>= 16 - st->resolution;
0498         *val = pos;
0499         ret = IIO_VAL_INT;
0500         break;
0501     case IIO_ANGL_VEL:
0502         vel = be16_to_cpup((__be16 *)st->rx);
0503         vel >>= 16 - st->resolution;
0504         if (vel & 0x8000) {
0505             negative = (0xffff >> st->resolution) << st->resolution;
0506             vel |= negative;
0507         }
0508         *val = vel;
0509         ret = IIO_VAL_INT;
0510         break;
0511     default:
0512         mutex_unlock(&st->lock);
0513         return -EINVAL;
0514     }
0515 
0516 error_ret:
0517     gpiod_set_value(st->gpios[AD2S1210_SAMPLE], 1);
0518     /* delay (2 * tck + 20) nano seconds */
0519     udelay(1);
0520     mutex_unlock(&st->lock);
0521     return ret;
0522 }
0523 
0524 static IIO_DEVICE_ATTR(fclkin, 0644,
0525                ad2s1210_show_fclkin, ad2s1210_store_fclkin, 0);
0526 static IIO_DEVICE_ATTR(fexcit, 0644,
0527                ad2s1210_show_fexcit,    ad2s1210_store_fexcit, 0);
0528 static IIO_DEVICE_ATTR(control, 0644,
0529                ad2s1210_show_control, ad2s1210_store_control, 0);
0530 static IIO_DEVICE_ATTR(bits, 0644,
0531                ad2s1210_show_resolution, ad2s1210_store_resolution, 0);
0532 static IIO_DEVICE_ATTR(fault, 0644,
0533                ad2s1210_show_fault, ad2s1210_clear_fault, 0);
0534 
0535 static IIO_DEVICE_ATTR(los_thrd, 0644,
0536                ad2s1210_show_reg, ad2s1210_store_reg,
0537                AD2S1210_REG_LOS_THRD);
0538 static IIO_DEVICE_ATTR(dos_ovr_thrd, 0644,
0539                ad2s1210_show_reg, ad2s1210_store_reg,
0540                AD2S1210_REG_DOS_OVR_THRD);
0541 static IIO_DEVICE_ATTR(dos_mis_thrd, 0644,
0542                ad2s1210_show_reg, ad2s1210_store_reg,
0543                AD2S1210_REG_DOS_MIS_THRD);
0544 static IIO_DEVICE_ATTR(dos_rst_max_thrd, 0644,
0545                ad2s1210_show_reg, ad2s1210_store_reg,
0546                AD2S1210_REG_DOS_RST_MAX_THRD);
0547 static IIO_DEVICE_ATTR(dos_rst_min_thrd, 0644,
0548                ad2s1210_show_reg, ad2s1210_store_reg,
0549                AD2S1210_REG_DOS_RST_MIN_THRD);
0550 static IIO_DEVICE_ATTR(lot_high_thrd, 0644,
0551                ad2s1210_show_reg, ad2s1210_store_reg,
0552                AD2S1210_REG_LOT_HIGH_THRD);
0553 static IIO_DEVICE_ATTR(lot_low_thrd, 0644,
0554                ad2s1210_show_reg, ad2s1210_store_reg,
0555                AD2S1210_REG_LOT_LOW_THRD);
0556 
0557 static const struct iio_chan_spec ad2s1210_channels[] = {
0558     {
0559         .type = IIO_ANGL,
0560         .indexed = 1,
0561         .channel = 0,
0562         .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
0563     }, {
0564         .type = IIO_ANGL_VEL,
0565         .indexed = 1,
0566         .channel = 0,
0567         .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
0568     }
0569 };
0570 
0571 static struct attribute *ad2s1210_attributes[] = {
0572     &iio_dev_attr_fclkin.dev_attr.attr,
0573     &iio_dev_attr_fexcit.dev_attr.attr,
0574     &iio_dev_attr_control.dev_attr.attr,
0575     &iio_dev_attr_bits.dev_attr.attr,
0576     &iio_dev_attr_fault.dev_attr.attr,
0577     &iio_dev_attr_los_thrd.dev_attr.attr,
0578     &iio_dev_attr_dos_ovr_thrd.dev_attr.attr,
0579     &iio_dev_attr_dos_mis_thrd.dev_attr.attr,
0580     &iio_dev_attr_dos_rst_max_thrd.dev_attr.attr,
0581     &iio_dev_attr_dos_rst_min_thrd.dev_attr.attr,
0582     &iio_dev_attr_lot_high_thrd.dev_attr.attr,
0583     &iio_dev_attr_lot_low_thrd.dev_attr.attr,
0584     NULL,
0585 };
0586 
0587 static const struct attribute_group ad2s1210_attribute_group = {
0588     .attrs = ad2s1210_attributes,
0589 };
0590 
0591 static int ad2s1210_initial(struct ad2s1210_state *st)
0592 {
0593     unsigned char data;
0594     int ret;
0595 
0596     mutex_lock(&st->lock);
0597     ad2s1210_set_resolution_pin(st);
0598 
0599     ret = ad2s1210_config_write(st, AD2S1210_REG_CONTROL);
0600     if (ret < 0)
0601         goto error_ret;
0602     data = AD2S1210_DEF_CONTROL & ~(AD2S1210_SET_RESOLUTION);
0603     data |= (st->resolution - 10) >> 1;
0604     ret = ad2s1210_config_write(st, data);
0605     if (ret < 0)
0606         goto error_ret;
0607     ret = ad2s1210_config_read(st, AD2S1210_REG_CONTROL);
0608     if (ret < 0)
0609         goto error_ret;
0610 
0611     if (ret & AD2S1210_MSB_IS_HIGH) {
0612         ret = -EIO;
0613         goto error_ret;
0614     }
0615 
0616     ret = ad2s1210_update_frequency_control_word(st);
0617     if (ret < 0)
0618         goto error_ret;
0619     ret = ad2s1210_soft_reset(st);
0620 error_ret:
0621     mutex_unlock(&st->lock);
0622     return ret;
0623 }
0624 
0625 static const struct iio_info ad2s1210_info = {
0626     .read_raw = ad2s1210_read_raw,
0627     .attrs = &ad2s1210_attribute_group,
0628 };
0629 
0630 static int ad2s1210_setup_gpios(struct ad2s1210_state *st)
0631 {
0632     struct spi_device *spi = st->sdev;
0633     int i, ret;
0634 
0635     for (i = 0; i < ARRAY_SIZE(gpios); i++) {
0636         st->gpios[i] = devm_gpiod_get(&spi->dev, gpios[i].name,
0637                           gpios[i].flags);
0638         if (IS_ERR(st->gpios[i])) {
0639             ret = PTR_ERR(st->gpios[i]);
0640             dev_err(&spi->dev,
0641                 "ad2s1210: failed to request %s GPIO: %d\n",
0642                 gpios[i].name, ret);
0643             return ret;
0644         }
0645     }
0646 
0647     return 0;
0648 }
0649 
0650 static int ad2s1210_probe(struct spi_device *spi)
0651 {
0652     struct iio_dev *indio_dev;
0653     struct ad2s1210_state *st;
0654     int ret;
0655 
0656     indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
0657     if (!indio_dev)
0658         return -ENOMEM;
0659     st = iio_priv(indio_dev);
0660     ret = ad2s1210_setup_gpios(st);
0661     if (ret < 0)
0662         return ret;
0663 
0664     spi_set_drvdata(spi, indio_dev);
0665 
0666     mutex_init(&st->lock);
0667     st->sdev = spi;
0668     st->hysteresis = true;
0669     st->mode = MOD_CONFIG;
0670     st->resolution = 12;
0671     st->fexcit = AD2S1210_DEF_EXCIT;
0672 
0673     indio_dev->info = &ad2s1210_info;
0674     indio_dev->modes = INDIO_DIRECT_MODE;
0675     indio_dev->channels = ad2s1210_channels;
0676     indio_dev->num_channels = ARRAY_SIZE(ad2s1210_channels);
0677     indio_dev->name = spi_get_device_id(spi)->name;
0678 
0679     ret = devm_iio_device_register(&spi->dev, indio_dev);
0680     if (ret)
0681         return ret;
0682 
0683     st->fclkin = spi->max_speed_hz;
0684     spi->mode = SPI_MODE_3;
0685     spi_setup(spi);
0686     ad2s1210_initial(st);
0687 
0688     return 0;
0689 }
0690 
0691 static const struct of_device_id ad2s1210_of_match[] = {
0692     { .compatible = "adi,ad2s1210", },
0693     { }
0694 };
0695 MODULE_DEVICE_TABLE(of, ad2s1210_of_match);
0696 
0697 static const struct spi_device_id ad2s1210_id[] = {
0698     { "ad2s1210" },
0699     {}
0700 };
0701 MODULE_DEVICE_TABLE(spi, ad2s1210_id);
0702 
0703 static struct spi_driver ad2s1210_driver = {
0704     .driver = {
0705         .name = DRV_NAME,
0706         .of_match_table = of_match_ptr(ad2s1210_of_match),
0707     },
0708     .probe = ad2s1210_probe,
0709     .id_table = ad2s1210_id,
0710 };
0711 module_spi_driver(ad2s1210_driver);
0712 
0713 MODULE_AUTHOR("Graff Yang <graff.yang@gmail.com>");
0714 MODULE_DESCRIPTION("Analog Devices AD2S1210 Resolver to Digital SPI driver");
0715 MODULE_LICENSE("GPL v2");
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