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0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * AD9833/AD9834/AD9837/AD9838 SPI DDS driver
0004  *
0005  * Copyright 2010-2011 Analog Devices Inc.
0006  */
0007 
0008 #include <linux/clk.h>
0009 #include <linux/interrupt.h>
0010 #include <linux/workqueue.h>
0011 #include <linux/device.h>
0012 #include <linux/kernel.h>
0013 #include <linux/slab.h>
0014 #include <linux/sysfs.h>
0015 #include <linux/list.h>
0016 #include <linux/spi/spi.h>
0017 #include <linux/regulator/consumer.h>
0018 #include <linux/err.h>
0019 #include <linux/module.h>
0020 #include <asm/div64.h>
0021 
0022 #include <linux/iio/iio.h>
0023 #include <linux/iio/sysfs.h>
0024 #include "dds.h"
0025 
0026 #include "ad9834.h"
0027 
0028 /* Registers */
0029 
0030 #define AD9834_REG_CMD      0
0031 #define AD9834_REG_FREQ0    BIT(14)
0032 #define AD9834_REG_FREQ1    BIT(15)
0033 #define AD9834_REG_PHASE0   (BIT(15) | BIT(14))
0034 #define AD9834_REG_PHASE1   (BIT(15) | BIT(14) | BIT(13))
0035 
0036 /* Command Control Bits */
0037 
0038 #define AD9834_B28      BIT(13)
0039 #define AD9834_HLB      BIT(12)
0040 #define AD9834_FSEL     BIT(11)
0041 #define AD9834_PSEL     BIT(10)
0042 #define AD9834_PIN_SW       BIT(9)
0043 #define AD9834_RESET        BIT(8)
0044 #define AD9834_SLEEP1       BIT(7)
0045 #define AD9834_SLEEP12      BIT(6)
0046 #define AD9834_OPBITEN      BIT(5)
0047 #define AD9834_SIGN_PIB     BIT(4)
0048 #define AD9834_DIV2     BIT(3)
0049 #define AD9834_MODE     BIT(1)
0050 
0051 #define AD9834_FREQ_BITS    28
0052 #define AD9834_PHASE_BITS   12
0053 
0054 #define RES_MASK(bits)  (BIT(bits) - 1)
0055 
0056 /**
0057  * struct ad9834_state - driver instance specific data
0058  * @spi:        spi_device
0059  * @mclk:       external master clock
0060  * @control:        cached control word
0061  * @devid:      device id
0062  * @xfer:       default spi transfer
0063  * @msg:        default spi message
0064  * @freq_xfer:      tuning word spi transfer
0065  * @freq_msg:       tuning word spi message
0066  * @lock:       protect sensor state
0067  * @data:       spi transmit buffer
0068  * @freq_data:      tuning word spi transmit buffer
0069  */
0070 
0071 struct ad9834_state {
0072     struct spi_device       *spi;
0073     struct clk          *mclk;
0074     unsigned short          control;
0075     unsigned short          devid;
0076     struct spi_transfer     xfer;
0077     struct spi_message      msg;
0078     struct spi_transfer     freq_xfer[2];
0079     struct spi_message      freq_msg;
0080     struct mutex                    lock;   /* protect sensor state */
0081 
0082     /*
0083      * DMA (thus cache coherency maintenance) requires the
0084      * transfer buffers to live in their own cache lines.
0085      */
0086     __be16              data ____cacheline_aligned;
0087     __be16              freq_data[2];
0088 };
0089 
0090 /*
0091  * ad9834_supported_device_ids:
0092  */
0093 
0094 enum ad9834_supported_device_ids {
0095     ID_AD9833,
0096     ID_AD9834,
0097     ID_AD9837,
0098     ID_AD9838,
0099 };
0100 
0101 static unsigned int ad9834_calc_freqreg(unsigned long mclk, unsigned long fout)
0102 {
0103     unsigned long long freqreg = (u64)fout * (u64)BIT(AD9834_FREQ_BITS);
0104 
0105     do_div(freqreg, mclk);
0106     return freqreg;
0107 }
0108 
0109 static int ad9834_write_frequency(struct ad9834_state *st,
0110                   unsigned long addr, unsigned long fout)
0111 {
0112     unsigned long clk_freq;
0113     unsigned long regval;
0114 
0115     clk_freq = clk_get_rate(st->mclk);
0116 
0117     if (fout > (clk_freq / 2))
0118         return -EINVAL;
0119 
0120     regval = ad9834_calc_freqreg(clk_freq, fout);
0121 
0122     st->freq_data[0] = cpu_to_be16(addr | (regval &
0123                        RES_MASK(AD9834_FREQ_BITS / 2)));
0124     st->freq_data[1] = cpu_to_be16(addr | ((regval >>
0125                        (AD9834_FREQ_BITS / 2)) &
0126                        RES_MASK(AD9834_FREQ_BITS / 2)));
0127 
0128     return spi_sync(st->spi, &st->freq_msg);
0129 }
0130 
0131 static int ad9834_write_phase(struct ad9834_state *st,
0132                   unsigned long addr, unsigned long phase)
0133 {
0134     if (phase > BIT(AD9834_PHASE_BITS))
0135         return -EINVAL;
0136     st->data = cpu_to_be16(addr | phase);
0137 
0138     return spi_sync(st->spi, &st->msg);
0139 }
0140 
0141 static ssize_t ad9834_write(struct device *dev,
0142                 struct device_attribute *attr,
0143                 const char *buf,
0144                 size_t len)
0145 {
0146     struct iio_dev *indio_dev = dev_to_iio_dev(dev);
0147     struct ad9834_state *st = iio_priv(indio_dev);
0148     struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
0149     int ret;
0150     unsigned long val;
0151 
0152     ret = kstrtoul(buf, 10, &val);
0153     if (ret)
0154         return ret;
0155 
0156     mutex_lock(&st->lock);
0157     switch ((u32)this_attr->address) {
0158     case AD9834_REG_FREQ0:
0159     case AD9834_REG_FREQ1:
0160         ret = ad9834_write_frequency(st, this_attr->address, val);
0161         break;
0162     case AD9834_REG_PHASE0:
0163     case AD9834_REG_PHASE1:
0164         ret = ad9834_write_phase(st, this_attr->address, val);
0165         break;
0166     case AD9834_OPBITEN:
0167         if (st->control & AD9834_MODE) {
0168             ret = -EINVAL;  /* AD9843 reserved mode */
0169             break;
0170         }
0171 
0172         if (val)
0173             st->control |= AD9834_OPBITEN;
0174         else
0175             st->control &= ~AD9834_OPBITEN;
0176 
0177         st->data = cpu_to_be16(AD9834_REG_CMD | st->control);
0178         ret = spi_sync(st->spi, &st->msg);
0179         break;
0180     case AD9834_PIN_SW:
0181         if (val)
0182             st->control |= AD9834_PIN_SW;
0183         else
0184             st->control &= ~AD9834_PIN_SW;
0185         st->data = cpu_to_be16(AD9834_REG_CMD | st->control);
0186         ret = spi_sync(st->spi, &st->msg);
0187         break;
0188     case AD9834_FSEL:
0189     case AD9834_PSEL:
0190         if (!val) {
0191             st->control &= ~(this_attr->address | AD9834_PIN_SW);
0192         } else if (val == 1) {
0193             st->control |= this_attr->address;
0194             st->control &= ~AD9834_PIN_SW;
0195         } else {
0196             ret = -EINVAL;
0197             break;
0198         }
0199         st->data = cpu_to_be16(AD9834_REG_CMD | st->control);
0200         ret = spi_sync(st->spi, &st->msg);
0201         break;
0202     case AD9834_RESET:
0203         if (val)
0204             st->control &= ~AD9834_RESET;
0205         else
0206             st->control |= AD9834_RESET;
0207 
0208         st->data = cpu_to_be16(AD9834_REG_CMD | st->control);
0209         ret = spi_sync(st->spi, &st->msg);
0210         break;
0211     default:
0212         ret = -ENODEV;
0213     }
0214     mutex_unlock(&st->lock);
0215 
0216     return ret ? ret : len;
0217 }
0218 
0219 static ssize_t ad9834_store_wavetype(struct device *dev,
0220                      struct device_attribute *attr,
0221                      const char *buf,
0222                      size_t len)
0223 {
0224     struct iio_dev *indio_dev = dev_to_iio_dev(dev);
0225     struct ad9834_state *st = iio_priv(indio_dev);
0226     struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
0227     int ret = 0;
0228     bool is_ad9833_7 = (st->devid == ID_AD9833) || (st->devid == ID_AD9837);
0229 
0230     mutex_lock(&st->lock);
0231 
0232     switch ((u32)this_attr->address) {
0233     case 0:
0234         if (sysfs_streq(buf, "sine")) {
0235             st->control &= ~AD9834_MODE;
0236             if (is_ad9833_7)
0237                 st->control &= ~AD9834_OPBITEN;
0238         } else if (sysfs_streq(buf, "triangle")) {
0239             if (is_ad9833_7) {
0240                 st->control &= ~AD9834_OPBITEN;
0241                 st->control |= AD9834_MODE;
0242             } else if (st->control & AD9834_OPBITEN) {
0243                 ret = -EINVAL;  /* AD9843 reserved mode */
0244             } else {
0245                 st->control |= AD9834_MODE;
0246             }
0247         } else if (is_ad9833_7 && sysfs_streq(buf, "square")) {
0248             st->control &= ~AD9834_MODE;
0249             st->control |= AD9834_OPBITEN;
0250         } else {
0251             ret = -EINVAL;
0252         }
0253 
0254         break;
0255     case 1:
0256         if (sysfs_streq(buf, "square") &&
0257             !(st->control & AD9834_MODE)) {
0258             st->control &= ~AD9834_MODE;
0259             st->control |= AD9834_OPBITEN;
0260         } else {
0261             ret = -EINVAL;
0262         }
0263         break;
0264     default:
0265         ret = -EINVAL;
0266         break;
0267     }
0268 
0269     if (!ret) {
0270         st->data = cpu_to_be16(AD9834_REG_CMD | st->control);
0271         ret = spi_sync(st->spi, &st->msg);
0272     }
0273     mutex_unlock(&st->lock);
0274 
0275     return ret ? ret : len;
0276 }
0277 
0278 static
0279 ssize_t ad9834_show_out0_wavetype_available(struct device *dev,
0280                         struct device_attribute *attr,
0281                         char *buf)
0282 {
0283     struct iio_dev *indio_dev = dev_to_iio_dev(dev);
0284     struct ad9834_state *st = iio_priv(indio_dev);
0285     char *str;
0286 
0287     if (st->devid == ID_AD9833 || st->devid == ID_AD9837)
0288         str = "sine triangle square";
0289     else if (st->control & AD9834_OPBITEN)
0290         str = "sine";
0291     else
0292         str = "sine triangle";
0293 
0294     return sprintf(buf, "%s\n", str);
0295 }
0296 
0297 static IIO_DEVICE_ATTR(out_altvoltage0_out0_wavetype_available, 0444,
0298                ad9834_show_out0_wavetype_available, NULL, 0);
0299 
0300 static
0301 ssize_t ad9834_show_out1_wavetype_available(struct device *dev,
0302                         struct device_attribute *attr,
0303                         char *buf)
0304 {
0305     struct iio_dev *indio_dev = dev_to_iio_dev(dev);
0306     struct ad9834_state *st = iio_priv(indio_dev);
0307     char *str;
0308 
0309     if (st->control & AD9834_MODE)
0310         str = "";
0311     else
0312         str = "square";
0313 
0314     return sprintf(buf, "%s\n", str);
0315 }
0316 
0317 static IIO_DEVICE_ATTR(out_altvoltage0_out1_wavetype_available, 0444,
0318                ad9834_show_out1_wavetype_available, NULL, 0);
0319 
0320 /*
0321  * see dds.h for further information
0322  */
0323 
0324 static IIO_DEV_ATTR_FREQ(0, 0, 0200, NULL, ad9834_write, AD9834_REG_FREQ0);
0325 static IIO_DEV_ATTR_FREQ(0, 1, 0200, NULL, ad9834_write, AD9834_REG_FREQ1);
0326 static IIO_DEV_ATTR_FREQSYMBOL(0, 0200, NULL, ad9834_write, AD9834_FSEL);
0327 static IIO_CONST_ATTR_FREQ_SCALE(0, "1"); /* 1Hz */
0328 
0329 static IIO_DEV_ATTR_PHASE(0, 0, 0200, NULL, ad9834_write, AD9834_REG_PHASE0);
0330 static IIO_DEV_ATTR_PHASE(0, 1, 0200, NULL, ad9834_write, AD9834_REG_PHASE1);
0331 static IIO_DEV_ATTR_PHASESYMBOL(0, 0200, NULL, ad9834_write, AD9834_PSEL);
0332 static IIO_CONST_ATTR_PHASE_SCALE(0, "0.0015339808"); /* 2PI/2^12 rad*/
0333 
0334 static IIO_DEV_ATTR_PINCONTROL_EN(0, 0200, NULL,
0335     ad9834_write, AD9834_PIN_SW);
0336 static IIO_DEV_ATTR_OUT_ENABLE(0, 0200, NULL, ad9834_write, AD9834_RESET);
0337 static IIO_DEV_ATTR_OUTY_ENABLE(0, 1, 0200, NULL,
0338     ad9834_write, AD9834_OPBITEN);
0339 static IIO_DEV_ATTR_OUT_WAVETYPE(0, 0, ad9834_store_wavetype, 0);
0340 static IIO_DEV_ATTR_OUT_WAVETYPE(0, 1, ad9834_store_wavetype, 1);
0341 
0342 static struct attribute *ad9834_attributes[] = {
0343     &iio_dev_attr_out_altvoltage0_frequency0.dev_attr.attr,
0344     &iio_dev_attr_out_altvoltage0_frequency1.dev_attr.attr,
0345     &iio_const_attr_out_altvoltage0_frequency_scale.dev_attr.attr,
0346     &iio_dev_attr_out_altvoltage0_phase0.dev_attr.attr,
0347     &iio_dev_attr_out_altvoltage0_phase1.dev_attr.attr,
0348     &iio_const_attr_out_altvoltage0_phase_scale.dev_attr.attr,
0349     &iio_dev_attr_out_altvoltage0_pincontrol_en.dev_attr.attr,
0350     &iio_dev_attr_out_altvoltage0_frequencysymbol.dev_attr.attr,
0351     &iio_dev_attr_out_altvoltage0_phasesymbol.dev_attr.attr,
0352     &iio_dev_attr_out_altvoltage0_out_enable.dev_attr.attr,
0353     &iio_dev_attr_out_altvoltage0_out1_enable.dev_attr.attr,
0354     &iio_dev_attr_out_altvoltage0_out0_wavetype.dev_attr.attr,
0355     &iio_dev_attr_out_altvoltage0_out1_wavetype.dev_attr.attr,
0356     &iio_dev_attr_out_altvoltage0_out0_wavetype_available.dev_attr.attr,
0357     &iio_dev_attr_out_altvoltage0_out1_wavetype_available.dev_attr.attr,
0358     NULL,
0359 };
0360 
0361 static struct attribute *ad9833_attributes[] = {
0362     &iio_dev_attr_out_altvoltage0_frequency0.dev_attr.attr,
0363     &iio_dev_attr_out_altvoltage0_frequency1.dev_attr.attr,
0364     &iio_const_attr_out_altvoltage0_frequency_scale.dev_attr.attr,
0365     &iio_dev_attr_out_altvoltage0_phase0.dev_attr.attr,
0366     &iio_dev_attr_out_altvoltage0_phase1.dev_attr.attr,
0367     &iio_const_attr_out_altvoltage0_phase_scale.dev_attr.attr,
0368     &iio_dev_attr_out_altvoltage0_frequencysymbol.dev_attr.attr,
0369     &iio_dev_attr_out_altvoltage0_phasesymbol.dev_attr.attr,
0370     &iio_dev_attr_out_altvoltage0_out_enable.dev_attr.attr,
0371     &iio_dev_attr_out_altvoltage0_out0_wavetype.dev_attr.attr,
0372     &iio_dev_attr_out_altvoltage0_out0_wavetype_available.dev_attr.attr,
0373     NULL,
0374 };
0375 
0376 static const struct attribute_group ad9834_attribute_group = {
0377     .attrs = ad9834_attributes,
0378 };
0379 
0380 static const struct attribute_group ad9833_attribute_group = {
0381     .attrs = ad9833_attributes,
0382 };
0383 
0384 static const struct iio_info ad9834_info = {
0385     .attrs = &ad9834_attribute_group,
0386 };
0387 
0388 static const struct iio_info ad9833_info = {
0389     .attrs = &ad9833_attribute_group,
0390 };
0391 
0392 static void ad9834_disable_reg(void *data)
0393 {
0394     struct regulator *reg = data;
0395 
0396     regulator_disable(reg);
0397 }
0398 
0399 static void ad9834_disable_clk(void *data)
0400 {
0401     struct clk *clk = data;
0402 
0403     clk_disable_unprepare(clk);
0404 }
0405 
0406 static int ad9834_probe(struct spi_device *spi)
0407 {
0408     struct ad9834_state *st;
0409     struct iio_dev *indio_dev;
0410     struct regulator *reg;
0411     int ret;
0412 
0413     reg = devm_regulator_get(&spi->dev, "avdd");
0414     if (IS_ERR(reg))
0415         return PTR_ERR(reg);
0416 
0417     ret = regulator_enable(reg);
0418     if (ret) {
0419         dev_err(&spi->dev, "Failed to enable specified AVDD supply\n");
0420         return ret;
0421     }
0422 
0423     ret = devm_add_action_or_reset(&spi->dev, ad9834_disable_reg, reg);
0424     if (ret)
0425         return ret;
0426 
0427     indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
0428     if (!indio_dev) {
0429         ret = -ENOMEM;
0430         return ret;
0431     }
0432     st = iio_priv(indio_dev);
0433     mutex_init(&st->lock);
0434     st->mclk = devm_clk_get(&spi->dev, NULL);
0435     if (IS_ERR(st->mclk)) {
0436         ret = PTR_ERR(st->mclk);
0437         return ret;
0438     }
0439 
0440     ret = clk_prepare_enable(st->mclk);
0441     if (ret) {
0442         dev_err(&spi->dev, "Failed to enable master clock\n");
0443         return ret;
0444     }
0445 
0446     ret = devm_add_action_or_reset(&spi->dev, ad9834_disable_clk, st->mclk);
0447     if (ret)
0448         return ret;
0449 
0450     st->spi = spi;
0451     st->devid = spi_get_device_id(spi)->driver_data;
0452     indio_dev->name = spi_get_device_id(spi)->name;
0453     switch (st->devid) {
0454     case ID_AD9833:
0455     case ID_AD9837:
0456         indio_dev->info = &ad9833_info;
0457         break;
0458     default:
0459         indio_dev->info = &ad9834_info;
0460         break;
0461     }
0462     indio_dev->modes = INDIO_DIRECT_MODE;
0463 
0464     /* Setup default messages */
0465 
0466     st->xfer.tx_buf = &st->data;
0467     st->xfer.len = 2;
0468 
0469     spi_message_init(&st->msg);
0470     spi_message_add_tail(&st->xfer, &st->msg);
0471 
0472     st->freq_xfer[0].tx_buf = &st->freq_data[0];
0473     st->freq_xfer[0].len = 2;
0474     st->freq_xfer[0].cs_change = 1;
0475     st->freq_xfer[1].tx_buf = &st->freq_data[1];
0476     st->freq_xfer[1].len = 2;
0477 
0478     spi_message_init(&st->freq_msg);
0479     spi_message_add_tail(&st->freq_xfer[0], &st->freq_msg);
0480     spi_message_add_tail(&st->freq_xfer[1], &st->freq_msg);
0481 
0482     st->control = AD9834_B28 | AD9834_RESET;
0483     st->control |= AD9834_DIV2;
0484 
0485     if (st->devid == ID_AD9834)
0486         st->control |= AD9834_SIGN_PIB;
0487 
0488     st->data = cpu_to_be16(AD9834_REG_CMD | st->control);
0489     ret = spi_sync(st->spi, &st->msg);
0490     if (ret) {
0491         dev_err(&spi->dev, "device init failed\n");
0492         return ret;
0493     }
0494 
0495     ret = ad9834_write_frequency(st, AD9834_REG_FREQ0, 1000000);
0496     if (ret)
0497         return ret;
0498 
0499     ret = ad9834_write_frequency(st, AD9834_REG_FREQ1, 5000000);
0500     if (ret)
0501         return ret;
0502 
0503     ret = ad9834_write_phase(st, AD9834_REG_PHASE0, 512);
0504     if (ret)
0505         return ret;
0506 
0507     ret = ad9834_write_phase(st, AD9834_REG_PHASE1, 1024);
0508     if (ret)
0509         return ret;
0510 
0511     return devm_iio_device_register(&spi->dev, indio_dev);
0512 }
0513 
0514 static const struct spi_device_id ad9834_id[] = {
0515     {"ad9833", ID_AD9833},
0516     {"ad9834", ID_AD9834},
0517     {"ad9837", ID_AD9837},
0518     {"ad9838", ID_AD9838},
0519     {}
0520 };
0521 MODULE_DEVICE_TABLE(spi, ad9834_id);
0522 
0523 static const struct of_device_id ad9834_of_match[] = {
0524     {.compatible = "adi,ad9833"},
0525     {.compatible = "adi,ad9834"},
0526     {.compatible = "adi,ad9837"},
0527     {.compatible = "adi,ad9838"},
0528     {}
0529 };
0530 
0531 MODULE_DEVICE_TABLE(of, ad9834_of_match);
0532 
0533 static struct spi_driver ad9834_driver = {
0534     .driver = {
0535         .name   = "ad9834",
0536         .of_match_table = ad9834_of_match
0537     },
0538     .probe      = ad9834_probe,
0539     .id_table   = ad9834_id,
0540 };
0541 module_spi_driver(ad9834_driver);
0542 
0543 MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>");
0544 MODULE_DESCRIPTION("Analog Devices AD9833/AD9834/AD9837/AD9838 DDS");
0545 MODULE_LICENSE("GPL v2");
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