iio/frequency/ad9832.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * AD9832 SPI DDS driver
0004  *
0005  * Copyright 2011 Analog Devices Inc.
0006  */
0007
0008 #include <asm/div64.h>
0009
0010 #include <linux/clk.h>
0011 #include <linux/device.h>
0012 #include <linux/err.h>
0013 #include <linux/kernel.h>
0014 #include <linux/module.h>
0015 #include <linux/regulator/consumer.h>
0016 #include <linux/slab.h>
0017 #include <linux/spi/spi.h>
0018 #include <linux/sysfs.h>
0019
0020 #include <linux/iio/iio.h>
0021 #include <linux/iio/sysfs.h>
0022
0023 #include "ad9832.h"
0024
0025 #include "dds.h"
0026
0027 /* Registers */
0028
0029 #define AD9832_FREQ0LL      0x0
0030 #define AD9832_FREQ0HL      0x1
0031 #define AD9832_FREQ0LM      0x2
0032 #define AD9832_FREQ0HM      0x3
0033 #define AD9832_FREQ1LL      0x4
0034 #define AD9832_FREQ1HL      0x5
0035 #define AD9832_FREQ1LM      0x6
0036 #define AD9832_FREQ1HM      0x7
0037 #define AD9832_PHASE0L      0x8
0038 #define AD9832_PHASE0H      0x9
0039 #define AD9832_PHASE1L      0xA
0040 #define AD9832_PHASE1H      0xB
0041 #define AD9832_PHASE2L      0xC
0042 #define AD9832_PHASE2H      0xD
0043 #define AD9832_PHASE3L      0xE
0044 #define AD9832_PHASE3H      0xF
0045
0046 #define AD9832_PHASE_SYM    0x10
0047 #define AD9832_FREQ_SYM     0x11
0048 #define AD9832_PINCTRL_EN   0x12
0049 #define AD9832_OUTPUT_EN    0x13
0050
0051 /* Command Control Bits */
0052
0053 #define AD9832_CMD_PHA8BITSW    0x1
0054 #define AD9832_CMD_PHA16BITSW   0x0
0055 #define AD9832_CMD_FRE8BITSW    0x3
0056 #define AD9832_CMD_FRE16BITSW   0x2
0057 #define AD9832_CMD_FPSELECT 0x6
0058 #define AD9832_CMD_SYNCSELSRC   0x8
0059 #define AD9832_CMD_SLEEPRESCLR  0xC
0060
0061 #define AD9832_FREQ     BIT(11)
0062 #define AD9832_PHASE(x)     (((x) & 3) << 9)
0063 #define AD9832_SYNC     BIT(13)
0064 #define AD9832_SELSRC       BIT(12)
0065 #define AD9832_SLEEP        BIT(13)
0066 #define AD9832_RESET        BIT(12)
0067 #define AD9832_CLR      BIT(11)
0068 #define CMD_SHIFT       12
0069 #define ADD_SHIFT       8
0070 #define AD9832_FREQ_BITS    32
0071 #define AD9832_PHASE_BITS   12
0072 #define RES_MASK(bits)      ((1 << (bits)) - 1)
0073
0074 /**
0075  * struct ad9832_state - driver instance specific data
0076  * @spi:        spi_device
0077  * @avdd:       supply regulator for the analog section
0078  * @dvdd:       supply regulator for the digital section
0079  * @mclk:       external master clock
0080  * @ctrl_fp:        cached frequency/phase control word
0081  * @ctrl_ss:        cached sync/selsrc control word
0082  * @ctrl_src:       cached sleep/reset/clr word
0083  * @xfer:       default spi transfer
0084  * @msg:        default spi message
0085  * @freq_xfer:      tuning word spi transfer
0086  * @freq_msg:       tuning word spi message
0087  * @phase_xfer:     tuning word spi transfer
0088  * @phase_msg:      tuning word spi message
0089  * @lock:       protect sensor state
0090  * @data:       spi transmit buffer
0091  * @phase_data:     tuning word spi transmit buffer
0092  * @freq_data:      tuning word spi transmit buffer
0093  */
0094
0095 struct ad9832_state {
0096     struct spi_device       *spi;
0097     struct regulator        *avdd;
0098     struct regulator        *dvdd;
0099     struct clk          *mclk;
0100     unsigned short          ctrl_fp;
0101     unsigned short          ctrl_ss;
0102     unsigned short          ctrl_src;
0103     struct spi_transfer     xfer;
0104     struct spi_message      msg;
0105     struct spi_transfer     freq_xfer[4];
0106     struct spi_message      freq_msg;
0107     struct spi_transfer     phase_xfer[2];
0108     struct spi_message      phase_msg;
0109     struct mutex            lock;   /* protect sensor state */
0110     /*
0111      * DMA (thus cache coherency maintenance) requires the
0112      * transfer buffers to live in their own cache lines.
0113      */
0114     union {
0115         __be16          freq_data[4]____cacheline_aligned;
0116         __be16          phase_data[2];
0117         __be16          data;
0118     };
0119 };
0120
0121 static unsigned long ad9832_calc_freqreg(unsigned long mclk, unsigned long fout)
0122 {
0123     unsigned long long freqreg = (u64)fout *
0124                      (u64)((u64)1L << AD9832_FREQ_BITS);
0125     do_div(freqreg, mclk);
0126     return freqreg;
0127 }
0128
0129 static int ad9832_write_frequency(struct ad9832_state *st,
0130                   unsigned int addr, unsigned long fout)
0131 {
0132     unsigned long regval;
0133
0134     if (fout > (clk_get_rate(st->mclk) / 2))
0135         return -EINVAL;
0136
0137     regval = ad9832_calc_freqreg(clk_get_rate(st->mclk), fout);
0138
0139     st->freq_data[0] = cpu_to_be16((AD9832_CMD_FRE8BITSW << CMD_SHIFT) |
0140                     (addr << ADD_SHIFT) |
0141                     ((regval >> 24) & 0xFF));
0142     st->freq_data[1] = cpu_to_be16((AD9832_CMD_FRE16BITSW << CMD_SHIFT) |
0143                     ((addr - 1) << ADD_SHIFT) |
0144                     ((regval >> 16) & 0xFF));
0145     st->freq_data[2] = cpu_to_be16((AD9832_CMD_FRE8BITSW << CMD_SHIFT) |
0146                     ((addr - 2) << ADD_SHIFT) |
0147                     ((regval >> 8) & 0xFF));
0148     st->freq_data[3] = cpu_to_be16((AD9832_CMD_FRE16BITSW << CMD_SHIFT) |
0149                     ((addr - 3) << ADD_SHIFT) |
0150                     ((regval >> 0) & 0xFF));
0151
0152     return spi_sync(st->spi, &st->freq_msg);
0153 }
0154
0155 static int ad9832_write_phase(struct ad9832_state *st,
0156                   unsigned long addr, unsigned long phase)
0157 {
0158     if (phase > BIT(AD9832_PHASE_BITS))
0159         return -EINVAL;
0160
0161     st->phase_data[0] = cpu_to_be16((AD9832_CMD_PHA8BITSW << CMD_SHIFT) |
0162                     (addr << ADD_SHIFT) |
0163                     ((phase >> 8) & 0xFF));
0164     st->phase_data[1] = cpu_to_be16((AD9832_CMD_PHA16BITSW << CMD_SHIFT) |
0165                     ((addr - 1) << ADD_SHIFT) |
0166                     (phase & 0xFF));
0167
0168     return spi_sync(st->spi, &st->phase_msg);
0169 }
0170
0171 static ssize_t ad9832_write(struct device *dev, struct device_attribute *attr,
0172                 const char *buf, size_t len)
0173 {
0174     struct iio_dev *indio_dev = dev_to_iio_dev(dev);
0175     struct ad9832_state *st = iio_priv(indio_dev);
0176     struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
0177     int ret;
0178     unsigned long val;
0179
0180     ret = kstrtoul(buf, 10, &val);
0181     if (ret)
0182         goto error_ret;
0183
0184     mutex_lock(&st->lock);
0185     switch ((u32)this_attr->address) {
0186     case AD9832_FREQ0HM:
0187     case AD9832_FREQ1HM:
0188         ret = ad9832_write_frequency(st, this_attr->address, val);
0189         break;
0190     case AD9832_PHASE0H:
0191     case AD9832_PHASE1H:
0192     case AD9832_PHASE2H:
0193     case AD9832_PHASE3H:
0194         ret = ad9832_write_phase(st, this_attr->address, val);
0195         break;
0196     case AD9832_PINCTRL_EN:
0197         if (val)
0198             st->ctrl_ss &= ~AD9832_SELSRC;
0199         else
0200             st->ctrl_ss |= AD9832_SELSRC;
0201         st->data = cpu_to_be16((AD9832_CMD_SYNCSELSRC << CMD_SHIFT) |
0202                     st->ctrl_ss);
0203         ret = spi_sync(st->spi, &st->msg);
0204         break;
0205     case AD9832_FREQ_SYM:
0206         if (val == 1) {
0207             st->ctrl_fp |= AD9832_FREQ;
0208         } else if (val == 0) {
0209             st->ctrl_fp &= ~AD9832_FREQ;
0210         } else {
0211             ret = -EINVAL;
0212             break;
0213         }
0214         st->data = cpu_to_be16((AD9832_CMD_FPSELECT << CMD_SHIFT) |
0215                     st->ctrl_fp);
0216         ret = spi_sync(st->spi, &st->msg);
0217         break;
0218     case AD9832_PHASE_SYM:
0219         if (val > 3) {
0220             ret = -EINVAL;
0221             break;
0222         }
0223
0224         st->ctrl_fp &= ~AD9832_PHASE(3);
0225         st->ctrl_fp |= AD9832_PHASE(val);
0226
0227         st->data = cpu_to_be16((AD9832_CMD_FPSELECT << CMD_SHIFT) |
0228                     st->ctrl_fp);
0229         ret = spi_sync(st->spi, &st->msg);
0230         break;
0231     case AD9832_OUTPUT_EN:
0232         if (val)
0233             st->ctrl_src &= ~(AD9832_RESET | AD9832_SLEEP |
0234                     AD9832_CLR);
0235         else
0236             st->ctrl_src |= AD9832_RESET;
0237
0238         st->data = cpu_to_be16((AD9832_CMD_SLEEPRESCLR << CMD_SHIFT) |
0239                     st->ctrl_src);
0240         ret = spi_sync(st->spi, &st->msg);
0241         break;
0242     default:
0243         ret = -ENODEV;
0244     }
0245     mutex_unlock(&st->lock);
0246
0247 error_ret:
0248     return ret ? ret : len;
0249 }
0250
0251 /*
0252  * see dds.h for further information
0253  */
0254
0255 static IIO_DEV_ATTR_FREQ(0, 0, 0200, NULL, ad9832_write, AD9832_FREQ0HM);
0256 static IIO_DEV_ATTR_FREQ(0, 1, 0200, NULL, ad9832_write, AD9832_FREQ1HM);
0257 static IIO_DEV_ATTR_FREQSYMBOL(0, 0200, NULL, ad9832_write, AD9832_FREQ_SYM);
0258 static IIO_CONST_ATTR_FREQ_SCALE(0, "1"); /* 1Hz */
0259
0260 static IIO_DEV_ATTR_PHASE(0, 0, 0200, NULL, ad9832_write, AD9832_PHASE0H);
0261 static IIO_DEV_ATTR_PHASE(0, 1, 0200, NULL, ad9832_write, AD9832_PHASE1H);
0262 static IIO_DEV_ATTR_PHASE(0, 2, 0200, NULL, ad9832_write, AD9832_PHASE2H);
0263 static IIO_DEV_ATTR_PHASE(0, 3, 0200, NULL, ad9832_write, AD9832_PHASE3H);
0264 static IIO_DEV_ATTR_PHASESYMBOL(0, 0200, NULL,
0265                 ad9832_write, AD9832_PHASE_SYM);
0266 static IIO_CONST_ATTR_PHASE_SCALE(0, "0.0015339808"); /* 2PI/2^12 rad*/
0267
0268 static IIO_DEV_ATTR_PINCONTROL_EN(0, 0200, NULL,
0269                 ad9832_write, AD9832_PINCTRL_EN);
0270 static IIO_DEV_ATTR_OUT_ENABLE(0, 0200, NULL,
0271                 ad9832_write, AD9832_OUTPUT_EN);
0272
0273 static struct attribute *ad9832_attributes[] = {
0274     &iio_dev_attr_out_altvoltage0_frequency0.dev_attr.attr,
0275     &iio_dev_attr_out_altvoltage0_frequency1.dev_attr.attr,
0276     &iio_const_attr_out_altvoltage0_frequency_scale.dev_attr.attr,
0277     &iio_dev_attr_out_altvoltage0_phase0.dev_attr.attr,
0278     &iio_dev_attr_out_altvoltage0_phase1.dev_attr.attr,
0279     &iio_dev_attr_out_altvoltage0_phase2.dev_attr.attr,
0280     &iio_dev_attr_out_altvoltage0_phase3.dev_attr.attr,
0281     &iio_const_attr_out_altvoltage0_phase_scale.dev_attr.attr,
0282     &iio_dev_attr_out_altvoltage0_pincontrol_en.dev_attr.attr,
0283     &iio_dev_attr_out_altvoltage0_frequencysymbol.dev_attr.attr,
0284     &iio_dev_attr_out_altvoltage0_phasesymbol.dev_attr.attr,
0285     &iio_dev_attr_out_altvoltage0_out_enable.dev_attr.attr,
0286     NULL,
0287 };
0288
0289 static const struct attribute_group ad9832_attribute_group = {
0290     .attrs = ad9832_attributes,
0291 };
0292
0293 static const struct iio_info ad9832_info = {
0294     .attrs = &ad9832_attribute_group,
0295 };
0296
0297 static void ad9832_reg_disable(void *reg)
0298 {
0299     regulator_disable(reg);
0300 }
0301
0302 static void ad9832_clk_disable(void *clk)
0303 {
0304     clk_disable_unprepare(clk);
0305 }
0306
0307 static int ad9832_probe(struct spi_device *spi)
0308 {
0309     struct ad9832_platform_data *pdata = dev_get_platdata(&spi->dev);
0310     struct iio_dev *indio_dev;
0311     struct ad9832_state *st;
0312     int ret;
0313
0314     if (!pdata) {
0315         dev_dbg(&spi->dev, "no platform data?\n");
0316         return -ENODEV;
0317     }
0318
0319     indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
0320     if (!indio_dev)
0321         return -ENOMEM;
0322
0323     st = iio_priv(indio_dev);
0324
0325     st->avdd = devm_regulator_get(&spi->dev, "avdd");
0326     if (IS_ERR(st->avdd))
0327         return PTR_ERR(st->avdd);
0328
0329     ret = regulator_enable(st->avdd);
0330     if (ret) {
0331         dev_err(&spi->dev, "Failed to enable specified AVDD supply\n");
0332         return ret;
0333     }
0334
0335     ret = devm_add_action_or_reset(&spi->dev, ad9832_reg_disable, st->avdd);
0336     if (ret)
0337         return ret;
0338
0339     st->dvdd = devm_regulator_get(&spi->dev, "dvdd");
0340     if (IS_ERR(st->dvdd))
0341         return PTR_ERR(st->dvdd);
0342
0343     ret = regulator_enable(st->dvdd);
0344     if (ret) {
0345         dev_err(&spi->dev, "Failed to enable specified DVDD supply\n");
0346         return ret;
0347     }
0348
0349     ret = devm_add_action_or_reset(&spi->dev, ad9832_reg_disable, st->dvdd);
0350     if (ret)
0351         return ret;
0352
0353     st->mclk = devm_clk_get(&spi->dev, "mclk");
0354     if (IS_ERR(st->mclk))
0355         return PTR_ERR(st->mclk);
0356
0357     ret = clk_prepare_enable(st->mclk);
0358     if (ret < 0)
0359         return ret;
0360
0361     ret = devm_add_action_or_reset(&spi->dev, ad9832_clk_disable, st->mclk);
0362     if (ret)
0363         return ret;
0364
0365     st->spi = spi;
0366     mutex_init(&st->lock);
0367
0368     indio_dev->name = spi_get_device_id(spi)->name;
0369     indio_dev->info = &ad9832_info;
0370     indio_dev->modes = INDIO_DIRECT_MODE;
0371
0372     /* Setup default messages */
0373
0374     st->xfer.tx_buf = &st->data;
0375     st->xfer.len = 2;
0376
0377     spi_message_init(&st->msg);
0378     spi_message_add_tail(&st->xfer, &st->msg);
0379
0380     st->freq_xfer[0].tx_buf = &st->freq_data[0];
0381     st->freq_xfer[0].len = 2;
0382     st->freq_xfer[0].cs_change = 1;
0383     st->freq_xfer[1].tx_buf = &st->freq_data[1];
0384     st->freq_xfer[1].len = 2;
0385     st->freq_xfer[1].cs_change = 1;
0386     st->freq_xfer[2].tx_buf = &st->freq_data[2];
0387     st->freq_xfer[2].len = 2;
0388     st->freq_xfer[2].cs_change = 1;
0389     st->freq_xfer[3].tx_buf = &st->freq_data[3];
0390     st->freq_xfer[3].len = 2;
0391
0392     spi_message_init(&st->freq_msg);
0393     spi_message_add_tail(&st->freq_xfer[0], &st->freq_msg);
0394     spi_message_add_tail(&st->freq_xfer[1], &st->freq_msg);
0395     spi_message_add_tail(&st->freq_xfer[2], &st->freq_msg);
0396     spi_message_add_tail(&st->freq_xfer[3], &st->freq_msg);
0397
0398     st->phase_xfer[0].tx_buf = &st->phase_data[0];
0399     st->phase_xfer[0].len = 2;
0400     st->phase_xfer[0].cs_change = 1;
0401     st->phase_xfer[1].tx_buf = &st->phase_data[1];
0402     st->phase_xfer[1].len = 2;
0403
0404     spi_message_init(&st->phase_msg);
0405     spi_message_add_tail(&st->phase_xfer[0], &st->phase_msg);
0406     spi_message_add_tail(&st->phase_xfer[1], &st->phase_msg);
0407
0408     st->ctrl_src = AD9832_SLEEP | AD9832_RESET | AD9832_CLR;
0409     st->data = cpu_to_be16((AD9832_CMD_SLEEPRESCLR << CMD_SHIFT) |
0410                     st->ctrl_src);
0411     ret = spi_sync(st->spi, &st->msg);
0412     if (ret) {
0413         dev_err(&spi->dev, "device init failed\n");
0414         return ret;
0415     }
0416
0417     ret = ad9832_write_frequency(st, AD9832_FREQ0HM, pdata->freq0);
0418     if (ret)
0419         return ret;
0420
0421     ret = ad9832_write_frequency(st, AD9832_FREQ1HM, pdata->freq1);
0422     if (ret)
0423         return ret;
0424
0425     ret = ad9832_write_phase(st, AD9832_PHASE0H, pdata->phase0);
0426     if (ret)
0427         return ret;
0428
0429     ret = ad9832_write_phase(st, AD9832_PHASE1H, pdata->phase1);
0430     if (ret)
0431         return ret;
0432
0433     ret = ad9832_write_phase(st, AD9832_PHASE2H, pdata->phase2);
0434     if (ret)
0435         return ret;
0436
0437     ret = ad9832_write_phase(st, AD9832_PHASE3H, pdata->phase3);
0438     if (ret)
0439         return ret;
0440
0441     return devm_iio_device_register(&spi->dev, indio_dev);
0442 }
0443
0444 static const struct spi_device_id ad9832_id[] = {
0445     {"ad9832", 0},
0446     {"ad9835", 0},
0447     {}
0448 };
0449 MODULE_DEVICE_TABLE(spi, ad9832_id);
0450
0451 static struct spi_driver ad9832_driver = {
0452     .driver = {
0453         .name   = "ad9832",
0454     },
0455     .probe      = ad9832_probe,
0456     .id_table   = ad9832_id,
0457 };
0458 module_spi_driver(ad9832_driver);
0459
0460 MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>");
0461 MODULE_DESCRIPTION("Analog Devices AD9832/AD9835 DDS");
0462 MODULE_LICENSE("GPL v2");