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0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * AD7746 capacitive sensor driver supporting AD7745, AD7746 and AD7747
0004  *
0005  * Copyright 2011 Analog Devices Inc.
0006  */
0007 
0008 #include <linux/delay.h>
0009 #include <linux/device.h>
0010 #include <linux/i2c.h>
0011 #include <linux/interrupt.h>
0012 #include <linux/kernel.h>
0013 #include <linux/module.h>
0014 #include <linux/slab.h>
0015 #include <linux/stat.h>
0016 #include <linux/sysfs.h>
0017 
0018 #include <linux/iio/iio.h>
0019 #include <linux/iio/sysfs.h>
0020 
0021 /*
0022  * AD7746 Register Definition
0023  */
0024 
0025 #define AD7746_REG_STATUS       0
0026 #define AD7746_REG_CAP_DATA_HIGH    1
0027 #define AD7746_REG_VT_DATA_HIGH     4
0028 #define AD7746_REG_CAP_SETUP        7
0029 #define AD7746_REG_VT_SETUP     8
0030 #define AD7746_REG_EXC_SETUP        9
0031 #define AD7746_REG_CFG          10
0032 #define AD7746_REG_CAPDACA      11
0033 #define AD7746_REG_CAPDACB      12
0034 #define AD7746_REG_CAP_OFFH     13
0035 #define AD7746_REG_CAP_GAINH        15
0036 #define AD7746_REG_VOLT_GAINH       17
0037 
0038 /* Status Register Bit Designations (AD7746_REG_STATUS) */
0039 #define AD7746_STATUS_EXCERR        BIT(3)
0040 #define AD7746_STATUS_RDY       BIT(2)
0041 #define AD7746_STATUS_RDYVT     BIT(1)
0042 #define AD7746_STATUS_RDYCAP        BIT(0)
0043 
0044 /* Capacitive Channel Setup Register Bit Designations (AD7746_REG_CAP_SETUP) */
0045 #define AD7746_CAPSETUP_CAPEN       BIT(7)
0046 #define AD7746_CAPSETUP_CIN2        BIT(6) /* AD7746 only */
0047 #define AD7746_CAPSETUP_CAPDIFF     BIT(5)
0048 #define AD7746_CAPSETUP_CACHOP      BIT(0)
0049 
0050 /* Voltage/Temperature Setup Register Bit Designations (AD7746_REG_VT_SETUP) */
0051 #define AD7746_VTSETUP_VTEN     (1 << 7)
0052 #define AD7746_VTSETUP_VTMD_INT_TEMP    (0 << 5)
0053 #define AD7746_VTSETUP_VTMD_EXT_TEMP    (1 << 5)
0054 #define AD7746_VTSETUP_VTMD_VDD_MON (2 << 5)
0055 #define AD7746_VTSETUP_VTMD_EXT_VIN (3 << 5)
0056 #define AD7746_VTSETUP_EXTREF       BIT(4)
0057 #define AD7746_VTSETUP_VTSHORT      BIT(1)
0058 #define AD7746_VTSETUP_VTCHOP       BIT(0)
0059 
0060 /* Excitation Setup Register Bit Designations (AD7746_REG_EXC_SETUP) */
0061 #define AD7746_EXCSETUP_CLKCTRL     BIT(7)
0062 #define AD7746_EXCSETUP_EXCON       BIT(6)
0063 #define AD7746_EXCSETUP_EXCB        BIT(5)
0064 #define AD7746_EXCSETUP_NEXCB       BIT(4)
0065 #define AD7746_EXCSETUP_EXCA        BIT(3)
0066 #define AD7746_EXCSETUP_NEXCA       BIT(2)
0067 #define AD7746_EXCSETUP_EXCLVL(x)   (((x) & 0x3) << 0)
0068 
0069 /* Config Register Bit Designations (AD7746_REG_CFG) */
0070 #define AD7746_CONF_VTFS_SHIFT      6
0071 #define AD7746_CONF_CAPFS_SHIFT     3
0072 #define AD7746_CONF_VTFS_MASK       GENMASK(7, 6)
0073 #define AD7746_CONF_CAPFS_MASK      GENMASK(5, 3)
0074 #define AD7746_CONF_MODE_IDLE       (0 << 0)
0075 #define AD7746_CONF_MODE_CONT_CONV  (1 << 0)
0076 #define AD7746_CONF_MODE_SINGLE_CONV    (2 << 0)
0077 #define AD7746_CONF_MODE_PWRDN      (3 << 0)
0078 #define AD7746_CONF_MODE_OFFS_CAL   (5 << 0)
0079 #define AD7746_CONF_MODE_GAIN_CAL   (6 << 0)
0080 
0081 /* CAPDAC Register Bit Designations (AD7746_REG_CAPDACx) */
0082 #define AD7746_CAPDAC_DACEN     BIT(7)
0083 #define AD7746_CAPDAC_DACP(x)       ((x) & 0x7F)
0084 
0085 struct ad7746_chip_info {
0086     struct i2c_client *client;
0087     struct mutex lock; /* protect sensor state */
0088     /*
0089      * Capacitive channel digital filter setup;
0090      * conversion time/update rate setup per channel
0091      */
0092     u8  config;
0093     u8  cap_setup;
0094     u8  vt_setup;
0095     u8  capdac[2][2];
0096     s8  capdac_set;
0097 
0098     union {
0099         __be32 d32;
0100         u8 d8[4];
0101     } data ____cacheline_aligned;
0102 };
0103 
0104 enum ad7746_chan {
0105     VIN,
0106     VIN_VDD,
0107     TEMP_INT,
0108     TEMP_EXT,
0109     CIN1,
0110     CIN1_DIFF,
0111     CIN2,
0112     CIN2_DIFF,
0113 };
0114 
0115 static const struct iio_chan_spec ad7746_channels[] = {
0116     [VIN] = {
0117         .type = IIO_VOLTAGE,
0118         .indexed = 1,
0119         .channel = 0,
0120         .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
0121         .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) |
0122             BIT(IIO_CHAN_INFO_SAMP_FREQ),
0123         .address = AD7746_REG_VT_DATA_HIGH << 8 |
0124             AD7746_VTSETUP_VTMD_EXT_VIN,
0125     },
0126     [VIN_VDD] = {
0127         .type = IIO_VOLTAGE,
0128         .indexed = 1,
0129         .channel = 1,
0130         .extend_name = "supply",
0131         .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
0132         .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) |
0133             BIT(IIO_CHAN_INFO_SAMP_FREQ),
0134         .address = AD7746_REG_VT_DATA_HIGH << 8 |
0135             AD7746_VTSETUP_VTMD_VDD_MON,
0136     },
0137     [TEMP_INT] = {
0138         .type = IIO_TEMP,
0139         .indexed = 1,
0140         .channel = 0,
0141         .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED),
0142         .address = AD7746_REG_VT_DATA_HIGH << 8 |
0143             AD7746_VTSETUP_VTMD_INT_TEMP,
0144     },
0145     [TEMP_EXT] = {
0146         .type = IIO_TEMP,
0147         .indexed = 1,
0148         .channel = 1,
0149         .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED),
0150         .address = AD7746_REG_VT_DATA_HIGH << 8 |
0151             AD7746_VTSETUP_VTMD_EXT_TEMP,
0152     },
0153     [CIN1] = {
0154         .type = IIO_CAPACITANCE,
0155         .indexed = 1,
0156         .channel = 0,
0157         .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
0158         BIT(IIO_CHAN_INFO_CALIBSCALE) | BIT(IIO_CHAN_INFO_OFFSET),
0159         .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_CALIBBIAS) |
0160         BIT(IIO_CHAN_INFO_SCALE) | BIT(IIO_CHAN_INFO_SAMP_FREQ),
0161         .address = AD7746_REG_CAP_DATA_HIGH << 8,
0162     },
0163     [CIN1_DIFF] = {
0164         .type = IIO_CAPACITANCE,
0165         .differential = 1,
0166         .indexed = 1,
0167         .channel = 0,
0168         .channel2 = 2,
0169         .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
0170         BIT(IIO_CHAN_INFO_CALIBSCALE) | BIT(IIO_CHAN_INFO_OFFSET),
0171         .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_CALIBBIAS) |
0172         BIT(IIO_CHAN_INFO_SCALE) | BIT(IIO_CHAN_INFO_SAMP_FREQ),
0173         .address = AD7746_REG_CAP_DATA_HIGH << 8 |
0174             AD7746_CAPSETUP_CAPDIFF
0175     },
0176     [CIN2] = {
0177         .type = IIO_CAPACITANCE,
0178         .indexed = 1,
0179         .channel = 1,
0180         .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
0181         BIT(IIO_CHAN_INFO_CALIBSCALE) | BIT(IIO_CHAN_INFO_OFFSET),
0182         .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_CALIBBIAS) |
0183         BIT(IIO_CHAN_INFO_SCALE) | BIT(IIO_CHAN_INFO_SAMP_FREQ),
0184         .address = AD7746_REG_CAP_DATA_HIGH << 8 |
0185             AD7746_CAPSETUP_CIN2,
0186     },
0187     [CIN2_DIFF] = {
0188         .type = IIO_CAPACITANCE,
0189         .differential = 1,
0190         .indexed = 1,
0191         .channel = 1,
0192         .channel2 = 3,
0193         .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
0194         BIT(IIO_CHAN_INFO_CALIBSCALE) | BIT(IIO_CHAN_INFO_OFFSET),
0195         .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_CALIBBIAS) |
0196         BIT(IIO_CHAN_INFO_SCALE) | BIT(IIO_CHAN_INFO_SAMP_FREQ),
0197         .address = AD7746_REG_CAP_DATA_HIGH << 8 |
0198             AD7746_CAPSETUP_CAPDIFF | AD7746_CAPSETUP_CIN2,
0199     }
0200 };
0201 
0202 /* Values are Update Rate (Hz), Conversion Time (ms) + 1*/
0203 static const unsigned char ad7746_vt_filter_rate_table[][2] = {
0204     {50, 20 + 1}, {31, 32 + 1}, {16, 62 + 1}, {8, 122 + 1},
0205 };
0206 
0207 static const unsigned char ad7746_cap_filter_rate_table[][2] = {
0208     {91, 11 + 1}, {84, 12 + 1}, {50, 20 + 1}, {26, 38 + 1},
0209     {16, 62 + 1}, {13, 77 + 1}, {11, 92 + 1}, {9, 110 + 1},
0210 };
0211 
0212 static int ad7746_set_capdac(struct ad7746_chip_info *chip, int channel)
0213 {
0214     int ret = i2c_smbus_write_byte_data(chip->client,
0215                         AD7746_REG_CAPDACA,
0216                         chip->capdac[channel][0]);
0217     if (ret < 0)
0218         return ret;
0219 
0220     return i2c_smbus_write_byte_data(chip->client,
0221                       AD7746_REG_CAPDACB,
0222                       chip->capdac[channel][1]);
0223 }
0224 
0225 static int ad7746_select_channel(struct iio_dev *indio_dev,
0226                  struct iio_chan_spec const *chan)
0227 {
0228     struct ad7746_chip_info *chip = iio_priv(indio_dev);
0229     u8 vt_setup, cap_setup;
0230     int ret, delay, idx;
0231 
0232     switch (chan->type) {
0233     case IIO_CAPACITANCE:
0234         cap_setup = (chan->address & 0xFF) | AD7746_CAPSETUP_CAPEN;
0235         vt_setup = chip->vt_setup & ~AD7746_VTSETUP_VTEN;
0236         idx = (chip->config & AD7746_CONF_CAPFS_MASK) >>
0237             AD7746_CONF_CAPFS_SHIFT;
0238         delay = ad7746_cap_filter_rate_table[idx][1];
0239 
0240         ret = ad7746_set_capdac(chip, chan->channel);
0241         if (ret < 0)
0242             return ret;
0243 
0244         if (chip->capdac_set != chan->channel)
0245             chip->capdac_set = chan->channel;
0246         break;
0247     case IIO_VOLTAGE:
0248     case IIO_TEMP:
0249         vt_setup = (chan->address & 0xFF) | AD7746_VTSETUP_VTEN;
0250         cap_setup = chip->cap_setup & ~AD7746_CAPSETUP_CAPEN;
0251         idx = (chip->config & AD7746_CONF_VTFS_MASK) >>
0252             AD7746_CONF_VTFS_SHIFT;
0253         delay = ad7746_cap_filter_rate_table[idx][1];
0254         break;
0255     default:
0256         return -EINVAL;
0257     }
0258 
0259     if (chip->cap_setup != cap_setup) {
0260         ret = i2c_smbus_write_byte_data(chip->client,
0261                         AD7746_REG_CAP_SETUP,
0262                         cap_setup);
0263         if (ret < 0)
0264             return ret;
0265 
0266         chip->cap_setup = cap_setup;
0267     }
0268 
0269     if (chip->vt_setup != vt_setup) {
0270         ret = i2c_smbus_write_byte_data(chip->client,
0271                         AD7746_REG_VT_SETUP,
0272                         vt_setup);
0273         if (ret < 0)
0274             return ret;
0275 
0276         chip->vt_setup = vt_setup;
0277     }
0278 
0279     return delay;
0280 }
0281 
0282 static inline ssize_t ad7746_start_calib(struct device *dev,
0283                      struct device_attribute *attr,
0284                      const char *buf,
0285                      size_t len,
0286                      u8 regval)
0287 {
0288     struct iio_dev *indio_dev = dev_to_iio_dev(dev);
0289     struct ad7746_chip_info *chip = iio_priv(indio_dev);
0290     int ret, timeout = 10;
0291     bool doit;
0292 
0293     ret = kstrtobool(buf, &doit);
0294     if (ret < 0)
0295         return ret;
0296 
0297     if (!doit)
0298         return 0;
0299 
0300     mutex_lock(&chip->lock);
0301     regval |= chip->config;
0302     ret = i2c_smbus_write_byte_data(chip->client, AD7746_REG_CFG, regval);
0303     if (ret < 0)
0304         goto unlock;
0305 
0306     do {
0307         msleep(20);
0308         ret = i2c_smbus_read_byte_data(chip->client, AD7746_REG_CFG);
0309         if (ret < 0)
0310             goto unlock;
0311 
0312     } while ((ret == regval) && timeout--);
0313 
0314     mutex_unlock(&chip->lock);
0315 
0316     return len;
0317 
0318 unlock:
0319     mutex_unlock(&chip->lock);
0320     return ret;
0321 }
0322 
0323 static ssize_t ad7746_start_offset_calib(struct device *dev,
0324                      struct device_attribute *attr,
0325                      const char *buf,
0326                      size_t len)
0327 {
0328     struct iio_dev *indio_dev = dev_to_iio_dev(dev);
0329     int ret = ad7746_select_channel(indio_dev,
0330                   &ad7746_channels[to_iio_dev_attr(attr)->address]);
0331     if (ret < 0)
0332         return ret;
0333 
0334     return ad7746_start_calib(dev, attr, buf, len,
0335                   AD7746_CONF_MODE_OFFS_CAL);
0336 }
0337 
0338 static ssize_t ad7746_start_gain_calib(struct device *dev,
0339                        struct device_attribute *attr,
0340                        const char *buf,
0341                        size_t len)
0342 {
0343     struct iio_dev *indio_dev = dev_to_iio_dev(dev);
0344     int ret = ad7746_select_channel(indio_dev,
0345                   &ad7746_channels[to_iio_dev_attr(attr)->address]);
0346     if (ret < 0)
0347         return ret;
0348 
0349     return ad7746_start_calib(dev, attr, buf, len,
0350                   AD7746_CONF_MODE_GAIN_CAL);
0351 }
0352 
0353 static IIO_DEVICE_ATTR(in_capacitance0_calibbias_calibration,
0354                0200, NULL, ad7746_start_offset_calib, CIN1);
0355 static IIO_DEVICE_ATTR(in_capacitance1_calibbias_calibration,
0356                0200, NULL, ad7746_start_offset_calib, CIN2);
0357 static IIO_DEVICE_ATTR(in_capacitance0_calibscale_calibration,
0358                0200, NULL, ad7746_start_gain_calib, CIN1);
0359 static IIO_DEVICE_ATTR(in_capacitance1_calibscale_calibration,
0360                0200, NULL, ad7746_start_gain_calib, CIN2);
0361 static IIO_DEVICE_ATTR(in_voltage0_calibscale_calibration,
0362                0200, NULL, ad7746_start_gain_calib, VIN);
0363 
0364 static int ad7746_store_cap_filter_rate_setup(struct ad7746_chip_info *chip,
0365                           int val)
0366 {
0367     int i;
0368 
0369     for (i = 0; i < ARRAY_SIZE(ad7746_cap_filter_rate_table); i++)
0370         if (val >= ad7746_cap_filter_rate_table[i][0])
0371             break;
0372 
0373     if (i >= ARRAY_SIZE(ad7746_cap_filter_rate_table))
0374         i = ARRAY_SIZE(ad7746_cap_filter_rate_table) - 1;
0375 
0376     chip->config &= ~AD7746_CONF_CAPFS_MASK;
0377     chip->config |= i << AD7746_CONF_CAPFS_SHIFT;
0378 
0379     return 0;
0380 }
0381 
0382 static int ad7746_store_vt_filter_rate_setup(struct ad7746_chip_info *chip,
0383                          int val)
0384 {
0385     int i;
0386 
0387     for (i = 0; i < ARRAY_SIZE(ad7746_vt_filter_rate_table); i++)
0388         if (val >= ad7746_vt_filter_rate_table[i][0])
0389             break;
0390 
0391     if (i >= ARRAY_SIZE(ad7746_vt_filter_rate_table))
0392         i = ARRAY_SIZE(ad7746_vt_filter_rate_table) - 1;
0393 
0394     chip->config &= ~AD7746_CONF_VTFS_MASK;
0395     chip->config |= i << AD7746_CONF_VTFS_SHIFT;
0396 
0397     return 0;
0398 }
0399 
0400 static IIO_CONST_ATTR(in_voltage_sampling_frequency_available, "50 31 16 8");
0401 static IIO_CONST_ATTR(in_capacitance_sampling_frequency_available,
0402                "91 84 50 26 16 13 11 9");
0403 
0404 static struct attribute *ad7746_attributes[] = {
0405     &iio_dev_attr_in_capacitance0_calibbias_calibration.dev_attr.attr,
0406     &iio_dev_attr_in_capacitance0_calibscale_calibration.dev_attr.attr,
0407     &iio_dev_attr_in_capacitance1_calibscale_calibration.dev_attr.attr,
0408     &iio_dev_attr_in_capacitance1_calibbias_calibration.dev_attr.attr,
0409     &iio_dev_attr_in_voltage0_calibscale_calibration.dev_attr.attr,
0410     &iio_const_attr_in_voltage_sampling_frequency_available.dev_attr.attr,
0411     &iio_const_attr_in_capacitance_sampling_frequency_available.dev_attr.attr,
0412     NULL,
0413 };
0414 
0415 static const struct attribute_group ad7746_attribute_group = {
0416     .attrs = ad7746_attributes,
0417 };
0418 
0419 static int ad7746_write_raw(struct iio_dev *indio_dev,
0420                 struct iio_chan_spec const *chan,
0421                 int val,
0422                 int val2,
0423                 long mask)
0424 {
0425     struct ad7746_chip_info *chip = iio_priv(indio_dev);
0426     int ret, reg;
0427 
0428     mutex_lock(&chip->lock);
0429 
0430     switch (mask) {
0431     case IIO_CHAN_INFO_CALIBSCALE:
0432         if (val != 1) {
0433             ret = -EINVAL;
0434             goto out;
0435         }
0436 
0437         val = (val2 * 1024) / 15625;
0438 
0439         switch (chan->type) {
0440         case IIO_CAPACITANCE:
0441             reg = AD7746_REG_CAP_GAINH;
0442             break;
0443         case IIO_VOLTAGE:
0444             reg = AD7746_REG_VOLT_GAINH;
0445             break;
0446         default:
0447             ret = -EINVAL;
0448             goto out;
0449         }
0450 
0451         ret = i2c_smbus_write_word_swapped(chip->client, reg, val);
0452         if (ret < 0)
0453             goto out;
0454 
0455         ret = 0;
0456         break;
0457     case IIO_CHAN_INFO_CALIBBIAS:
0458         if (val < 0 || val > 0xFFFF) {
0459             ret = -EINVAL;
0460             goto out;
0461         }
0462         ret = i2c_smbus_write_word_swapped(chip->client,
0463                            AD7746_REG_CAP_OFFH, val);
0464         if (ret < 0)
0465             goto out;
0466 
0467         ret = 0;
0468         break;
0469     case IIO_CHAN_INFO_OFFSET:
0470         if (val < 0 || val > 43008000) { /* 21pF */
0471             ret = -EINVAL;
0472             goto out;
0473         }
0474 
0475         /*
0476          * CAPDAC Scale = 21pF_typ / 127
0477          * CIN Scale = 8.192pF / 2^24
0478          * Offset Scale = CAPDAC Scale / CIN Scale = 338646
0479          */
0480 
0481         val /= 338646;
0482 
0483         chip->capdac[chan->channel][chan->differential] = val > 0 ?
0484             AD7746_CAPDAC_DACP(val) | AD7746_CAPDAC_DACEN : 0;
0485 
0486         ret = ad7746_set_capdac(chip, chan->channel);
0487         if (ret < 0)
0488             goto out;
0489 
0490         chip->capdac_set = chan->channel;
0491 
0492         ret = 0;
0493         break;
0494     case IIO_CHAN_INFO_SAMP_FREQ:
0495         if (val2) {
0496             ret = -EINVAL;
0497             goto out;
0498         }
0499 
0500         switch (chan->type) {
0501         case IIO_CAPACITANCE:
0502             ret = ad7746_store_cap_filter_rate_setup(chip, val);
0503             break;
0504         case IIO_VOLTAGE:
0505             ret = ad7746_store_vt_filter_rate_setup(chip, val);
0506             break;
0507         default:
0508             ret = -EINVAL;
0509         }
0510         break;
0511     default:
0512         ret = -EINVAL;
0513     }
0514 
0515 out:
0516     mutex_unlock(&chip->lock);
0517     return ret;
0518 }
0519 
0520 static int ad7746_read_raw(struct iio_dev *indio_dev,
0521                struct iio_chan_spec const *chan,
0522                int *val, int *val2,
0523                long mask)
0524 {
0525     struct ad7746_chip_info *chip = iio_priv(indio_dev);
0526     int ret, delay, idx;
0527     u8 regval, reg;
0528 
0529     mutex_lock(&chip->lock);
0530 
0531     switch (mask) {
0532     case IIO_CHAN_INFO_RAW:
0533     case IIO_CHAN_INFO_PROCESSED:
0534         ret = ad7746_select_channel(indio_dev, chan);
0535         if (ret < 0)
0536             goto out;
0537         delay = ret;
0538 
0539         regval = chip->config | AD7746_CONF_MODE_SINGLE_CONV;
0540         ret = i2c_smbus_write_byte_data(chip->client, AD7746_REG_CFG,
0541                         regval);
0542         if (ret < 0)
0543             goto out;
0544 
0545         msleep(delay);
0546         /* Now read the actual register */
0547 
0548         ret = i2c_smbus_read_i2c_block_data(chip->client,
0549                             chan->address >> 8, 3,
0550                             &chip->data.d8[1]);
0551 
0552         if (ret < 0)
0553             goto out;
0554 
0555         *val = (be32_to_cpu(chip->data.d32) & 0xFFFFFF) - 0x800000;
0556 
0557         switch (chan->type) {
0558         case IIO_TEMP:
0559             /*
0560              * temperature in milli degrees Celsius
0561              * T = ((*val / 2048) - 4096) * 1000
0562              */
0563             *val = (*val * 125) / 256;
0564             break;
0565         case IIO_VOLTAGE:
0566             if (chan->channel == 1) /* supply_raw*/
0567                 *val = *val * 6;
0568             break;
0569         default:
0570             break;
0571         }
0572 
0573         ret = IIO_VAL_INT;
0574         break;
0575     case IIO_CHAN_INFO_CALIBSCALE:
0576         switch (chan->type) {
0577         case IIO_CAPACITANCE:
0578             reg = AD7746_REG_CAP_GAINH;
0579             break;
0580         case IIO_VOLTAGE:
0581             reg = AD7746_REG_VOLT_GAINH;
0582             break;
0583         default:
0584             ret = -EINVAL;
0585             goto out;
0586         }
0587 
0588         ret = i2c_smbus_read_word_swapped(chip->client, reg);
0589         if (ret < 0)
0590             goto out;
0591         /* 1 + gain_val / 2^16 */
0592         *val = 1;
0593         *val2 = (15625 * ret) / 1024;
0594 
0595         ret = IIO_VAL_INT_PLUS_MICRO;
0596         break;
0597     case IIO_CHAN_INFO_CALIBBIAS:
0598         ret = i2c_smbus_read_word_swapped(chip->client,
0599                           AD7746_REG_CAP_OFFH);
0600         if (ret < 0)
0601             goto out;
0602         *val = ret;
0603 
0604         ret = IIO_VAL_INT;
0605         break;
0606     case IIO_CHAN_INFO_OFFSET:
0607         *val = AD7746_CAPDAC_DACP(chip->capdac[chan->channel]
0608                       [chan->differential]) * 338646;
0609 
0610         ret = IIO_VAL_INT;
0611         break;
0612     case IIO_CHAN_INFO_SCALE:
0613         switch (chan->type) {
0614         case IIO_CAPACITANCE:
0615             /* 8.192pf / 2^24 */
0616             *val =  0;
0617             *val2 = 488;
0618             ret = IIO_VAL_INT_PLUS_NANO;
0619             break;
0620         case IIO_VOLTAGE:
0621             /* 1170mV / 2^23 */
0622             *val = 1170;
0623             *val2 = 23;
0624             ret = IIO_VAL_FRACTIONAL_LOG2;
0625             break;
0626         default:
0627             ret = -EINVAL;
0628             break;
0629         }
0630 
0631         break;
0632     case IIO_CHAN_INFO_SAMP_FREQ:
0633         switch (chan->type) {
0634         case IIO_CAPACITANCE:
0635             idx = (chip->config & AD7746_CONF_CAPFS_MASK) >>
0636                 AD7746_CONF_CAPFS_SHIFT;
0637             *val = ad7746_cap_filter_rate_table[idx][0];
0638             ret = IIO_VAL_INT;
0639             break;
0640         case IIO_VOLTAGE:
0641             idx = (chip->config & AD7746_CONF_VTFS_MASK) >>
0642                 AD7746_CONF_VTFS_SHIFT;
0643             *val = ad7746_vt_filter_rate_table[idx][0];
0644             ret = IIO_VAL_INT;
0645             break;
0646         default:
0647             ret = -EINVAL;
0648         }
0649         break;
0650     default:
0651         ret = -EINVAL;
0652     }
0653 out:
0654     mutex_unlock(&chip->lock);
0655     return ret;
0656 }
0657 
0658 static const struct iio_info ad7746_info = {
0659     .attrs = &ad7746_attribute_group,
0660     .read_raw = ad7746_read_raw,
0661     .write_raw = ad7746_write_raw,
0662 };
0663 
0664 static int ad7746_probe(struct i2c_client *client,
0665             const struct i2c_device_id *id)
0666 {
0667     struct device *dev = &client->dev;
0668     struct ad7746_chip_info *chip;
0669     struct iio_dev *indio_dev;
0670     unsigned char regval = 0;
0671     unsigned int vdd_permille;
0672     int ret;
0673 
0674     indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*chip));
0675     if (!indio_dev)
0676         return -ENOMEM;
0677     chip = iio_priv(indio_dev);
0678     mutex_init(&chip->lock);
0679     /* this is only used for device removal purposes */
0680     i2c_set_clientdata(client, indio_dev);
0681 
0682     chip->client = client;
0683     chip->capdac_set = -1;
0684 
0685     indio_dev->name = id->name;
0686     indio_dev->info = &ad7746_info;
0687     indio_dev->channels = ad7746_channels;
0688     if (id->driver_data == 7746)
0689         indio_dev->num_channels = ARRAY_SIZE(ad7746_channels);
0690     else
0691         indio_dev->num_channels =  ARRAY_SIZE(ad7746_channels) - 2;
0692     indio_dev->modes = INDIO_DIRECT_MODE;
0693 
0694     if (device_property_read_bool(dev, "adi,exca-output-en")) {
0695         if (device_property_read_bool(dev, "adi,exca-output-invert"))
0696             regval |= AD7746_EXCSETUP_NEXCA;
0697         else
0698             regval |= AD7746_EXCSETUP_EXCA;
0699     }
0700 
0701     if (device_property_read_bool(dev, "adi,excb-output-en")) {
0702         if (device_property_read_bool(dev, "adi,excb-output-invert"))
0703             regval |= AD7746_EXCSETUP_NEXCB;
0704         else
0705             regval |= AD7746_EXCSETUP_EXCB;
0706     }
0707 
0708     ret = device_property_read_u32(dev, "adi,excitation-vdd-permille",
0709                        &vdd_permille);
0710     if (!ret) {
0711         switch (vdd_permille) {
0712         case 125:
0713             regval |= AD7746_EXCSETUP_EXCLVL(0);
0714             break;
0715         case 250:
0716             regval |= AD7746_EXCSETUP_EXCLVL(1);
0717             break;
0718         case 375:
0719             regval |= AD7746_EXCSETUP_EXCLVL(2);
0720             break;
0721         case 500:
0722             regval |= AD7746_EXCSETUP_EXCLVL(3);
0723             break;
0724         default:
0725             break;
0726         }
0727     }
0728 
0729     ret = i2c_smbus_write_byte_data(chip->client,
0730                     AD7746_REG_EXC_SETUP, regval);
0731     if (ret < 0)
0732         return ret;
0733 
0734     return devm_iio_device_register(indio_dev->dev.parent, indio_dev);
0735 }
0736 
0737 static const struct i2c_device_id ad7746_id[] = {
0738     { "ad7745", 7745 },
0739     { "ad7746", 7746 },
0740     { "ad7747", 7747 },
0741     {}
0742 };
0743 
0744 MODULE_DEVICE_TABLE(i2c, ad7746_id);
0745 
0746 static const struct of_device_id ad7746_of_match[] = {
0747     { .compatible = "adi,ad7745" },
0748     { .compatible = "adi,ad7746" },
0749     { .compatible = "adi,ad7747" },
0750     { },
0751 };
0752 
0753 MODULE_DEVICE_TABLE(of, ad7746_of_match);
0754 
0755 static struct i2c_driver ad7746_driver = {
0756     .driver = {
0757         .name = KBUILD_MODNAME,
0758         .of_match_table = ad7746_of_match,
0759     },
0760     .probe = ad7746_probe,
0761     .id_table = ad7746_id,
0762 };
0763 module_i2c_driver(ad7746_driver);
0764 
0765 MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>");
0766 MODULE_DESCRIPTION("Analog Devices AD7746/5/7 capacitive sensor driver");
0767 MODULE_LICENSE("GPL v2");
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