staging/clocking-wizard/dt-binding.txt

0001 Binding for Xilinx Clocking Wizard IP Core
0002
0003 This binding uses the common clock binding[1]. Details about the devices can be
0004 found in the product guide[2].
0005
0006 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
0007 [2] Clocking Wizard Product Guide
0008 https://www.xilinx.com/support/documentation/ip_documentation/clk_wiz/v5_1/pg065-clk-wiz.pdf
0009
0010 Required properties:
0011  - compatible: Must be 'xlnx,clocking-wizard'
0012  - reg: Base and size of the cores register space
0013  - clocks: Handle to input clock
0014  - clock-names: Tuple containing 'clk_in1' and 's_axi_aclk'
0015  - clock-output-names: Names for the output clocks
0016
0017 Optional properties:
0018  - speed-grade: Speed grade of the device (valid values are 1..3)
0019
0020 Example:
0021         clock-generator@40040000 {
0022                 reg = <0x40040000 0x1000>;
0023                 compatible = "xlnx,clocking-wizard";
0024                 speed-grade = <1>;
0025                 clock-names = "clk_in1", "s_axi_aclk";
0026                 clocks = <&clkc 15>, <&clkc 15>;
0027                 clock-output-names = "clk_out0", "clk_out1", "clk_out2",
0028                                      "clk_out3", "clk_out4", "clk_out5",
0029                                      "clk_out6", "clk_out7";
0030         };