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0001 /*
0002  * Sonics Silicon Backplane
0003  * Subsystem core
0004  *
0005  * Copyright 2005, Broadcom Corporation
0006  * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
0007  *
0008  * Licensed under the GNU/GPL. See COPYING for details.
0009  */
0010 
0011 #include "ssb_private.h"
0012 
0013 #include <linux/delay.h>
0014 #include <linux/io.h>
0015 #include <linux/module.h>
0016 #include <linux/platform_device.h>
0017 #include <linux/ssb/ssb.h>
0018 #include <linux/ssb/ssb_regs.h>
0019 #include <linux/ssb/ssb_driver_gige.h>
0020 #include <linux/dma-mapping.h>
0021 #include <linux/pci.h>
0022 #include <linux/mmc/sdio_func.h>
0023 #include <linux/slab.h>
0024 
0025 #include <pcmcia/cistpl.h>
0026 #include <pcmcia/ds.h>
0027 
0028 
0029 MODULE_DESCRIPTION("Sonics Silicon Backplane driver");
0030 MODULE_LICENSE("GPL");
0031 
0032 
0033 /* Temporary list of yet-to-be-attached buses */
0034 static LIST_HEAD(attach_queue);
0035 /* List if running buses */
0036 static LIST_HEAD(buses);
0037 /* Software ID counter */
0038 static unsigned int next_busnumber;
0039 /* buses_mutes locks the two buslists and the next_busnumber.
0040  * Don't lock this directly, but use ssb_buses_[un]lock() below.
0041  */
0042 static DEFINE_MUTEX(buses_mutex);
0043 
0044 /* There are differences in the codeflow, if the bus is
0045  * initialized from early boot, as various needed services
0046  * are not available early. This is a mechanism to delay
0047  * these initializations to after early boot has finished.
0048  * It's also used to avoid mutex locking, as that's not
0049  * available and needed early.
0050  */
0051 static bool ssb_is_early_boot = 1;
0052 
0053 static void ssb_buses_lock(void);
0054 static void ssb_buses_unlock(void);
0055 
0056 
0057 #ifdef CONFIG_SSB_PCIHOST
0058 struct ssb_bus *ssb_pci_dev_to_bus(struct pci_dev *pdev)
0059 {
0060     struct ssb_bus *bus;
0061 
0062     ssb_buses_lock();
0063     list_for_each_entry(bus, &buses, list) {
0064         if (bus->bustype == SSB_BUSTYPE_PCI &&
0065             bus->host_pci == pdev)
0066             goto found;
0067     }
0068     bus = NULL;
0069 found:
0070     ssb_buses_unlock();
0071 
0072     return bus;
0073 }
0074 #endif /* CONFIG_SSB_PCIHOST */
0075 
0076 #ifdef CONFIG_SSB_PCMCIAHOST
0077 struct ssb_bus *ssb_pcmcia_dev_to_bus(struct pcmcia_device *pdev)
0078 {
0079     struct ssb_bus *bus;
0080 
0081     ssb_buses_lock();
0082     list_for_each_entry(bus, &buses, list) {
0083         if (bus->bustype == SSB_BUSTYPE_PCMCIA &&
0084             bus->host_pcmcia == pdev)
0085             goto found;
0086     }
0087     bus = NULL;
0088 found:
0089     ssb_buses_unlock();
0090 
0091     return bus;
0092 }
0093 #endif /* CONFIG_SSB_PCMCIAHOST */
0094 
0095 int ssb_for_each_bus_call(unsigned long data,
0096               int (*func)(struct ssb_bus *bus, unsigned long data))
0097 {
0098     struct ssb_bus *bus;
0099     int res;
0100 
0101     ssb_buses_lock();
0102     list_for_each_entry(bus, &buses, list) {
0103         res = func(bus, data);
0104         if (res >= 0) {
0105             ssb_buses_unlock();
0106             return res;
0107         }
0108     }
0109     ssb_buses_unlock();
0110 
0111     return -ENODEV;
0112 }
0113 
0114 static struct ssb_device *ssb_device_get(struct ssb_device *dev)
0115 {
0116     if (dev)
0117         get_device(dev->dev);
0118     return dev;
0119 }
0120 
0121 static void ssb_device_put(struct ssb_device *dev)
0122 {
0123     if (dev)
0124         put_device(dev->dev);
0125 }
0126 
0127 static int ssb_device_resume(struct device *dev)
0128 {
0129     struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
0130     struct ssb_driver *ssb_drv;
0131     int err = 0;
0132 
0133     if (dev->driver) {
0134         ssb_drv = drv_to_ssb_drv(dev->driver);
0135         if (ssb_drv && ssb_drv->resume)
0136             err = ssb_drv->resume(ssb_dev);
0137         if (err)
0138             goto out;
0139     }
0140 out:
0141     return err;
0142 }
0143 
0144 static int ssb_device_suspend(struct device *dev, pm_message_t state)
0145 {
0146     struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
0147     struct ssb_driver *ssb_drv;
0148     int err = 0;
0149 
0150     if (dev->driver) {
0151         ssb_drv = drv_to_ssb_drv(dev->driver);
0152         if (ssb_drv && ssb_drv->suspend)
0153             err = ssb_drv->suspend(ssb_dev, state);
0154         if (err)
0155             goto out;
0156     }
0157 out:
0158     return err;
0159 }
0160 
0161 int ssb_bus_resume(struct ssb_bus *bus)
0162 {
0163     int err;
0164 
0165     /* Reset HW state information in memory, so that HW is
0166      * completely reinitialized.
0167      */
0168     bus->mapped_device = NULL;
0169 #ifdef CONFIG_SSB_DRIVER_PCICORE
0170     bus->pcicore.setup_done = 0;
0171 #endif
0172 
0173     err = ssb_bus_powerup(bus, 0);
0174     if (err)
0175         return err;
0176     err = ssb_pcmcia_hardware_setup(bus);
0177     if (err) {
0178         ssb_bus_may_powerdown(bus);
0179         return err;
0180     }
0181     ssb_chipco_resume(&bus->chipco);
0182     ssb_bus_may_powerdown(bus);
0183 
0184     return 0;
0185 }
0186 EXPORT_SYMBOL(ssb_bus_resume);
0187 
0188 int ssb_bus_suspend(struct ssb_bus *bus)
0189 {
0190     ssb_chipco_suspend(&bus->chipco);
0191     ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 0);
0192 
0193     return 0;
0194 }
0195 EXPORT_SYMBOL(ssb_bus_suspend);
0196 
0197 #ifdef CONFIG_SSB_SPROM
0198 /** ssb_devices_freeze - Freeze all devices on the bus.
0199  *
0200  * After freezing no device driver will be handling a device
0201  * on this bus anymore. ssb_devices_thaw() must be called after
0202  * a successful freeze to reactivate the devices.
0203  *
0204  * @bus: The bus.
0205  * @ctx: Context structure. Pass this to ssb_devices_thaw().
0206  */
0207 int ssb_devices_freeze(struct ssb_bus *bus, struct ssb_freeze_context *ctx)
0208 {
0209     struct ssb_device *sdev;
0210     struct ssb_driver *sdrv;
0211     unsigned int i;
0212 
0213     memset(ctx, 0, sizeof(*ctx));
0214     ctx->bus = bus;
0215     WARN_ON(bus->nr_devices > ARRAY_SIZE(ctx->device_frozen));
0216 
0217     for (i = 0; i < bus->nr_devices; i++) {
0218         sdev = ssb_device_get(&bus->devices[i]);
0219 
0220         if (!sdev->dev || !sdev->dev->driver ||
0221             !device_is_registered(sdev->dev)) {
0222             ssb_device_put(sdev);
0223             continue;
0224         }
0225         sdrv = drv_to_ssb_drv(sdev->dev->driver);
0226         if (WARN_ON(!sdrv->remove))
0227             continue;
0228         sdrv->remove(sdev);
0229         ctx->device_frozen[i] = 1;
0230     }
0231 
0232     return 0;
0233 }
0234 
0235 /** ssb_devices_thaw - Unfreeze all devices on the bus.
0236  *
0237  * This will re-attach the device drivers and re-init the devices.
0238  *
0239  * @ctx: The context structure from ssb_devices_freeze()
0240  */
0241 int ssb_devices_thaw(struct ssb_freeze_context *ctx)
0242 {
0243     struct ssb_bus *bus = ctx->bus;
0244     struct ssb_device *sdev;
0245     struct ssb_driver *sdrv;
0246     unsigned int i;
0247     int err, result = 0;
0248 
0249     for (i = 0; i < bus->nr_devices; i++) {
0250         if (!ctx->device_frozen[i])
0251             continue;
0252         sdev = &bus->devices[i];
0253 
0254         if (WARN_ON(!sdev->dev || !sdev->dev->driver))
0255             continue;
0256         sdrv = drv_to_ssb_drv(sdev->dev->driver);
0257         if (WARN_ON(!sdrv || !sdrv->probe))
0258             continue;
0259 
0260         err = sdrv->probe(sdev, &sdev->id);
0261         if (err) {
0262             dev_err(sdev->dev,
0263                 "Failed to thaw device %s\n",
0264                 dev_name(sdev->dev));
0265             result = err;
0266         }
0267         ssb_device_put(sdev);
0268     }
0269 
0270     return result;
0271 }
0272 #endif /* CONFIG_SSB_SPROM */
0273 
0274 static void ssb_device_shutdown(struct device *dev)
0275 {
0276     struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
0277     struct ssb_driver *ssb_drv;
0278 
0279     if (!dev->driver)
0280         return;
0281     ssb_drv = drv_to_ssb_drv(dev->driver);
0282     if (ssb_drv && ssb_drv->shutdown)
0283         ssb_drv->shutdown(ssb_dev);
0284 }
0285 
0286 static void ssb_device_remove(struct device *dev)
0287 {
0288     struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
0289     struct ssb_driver *ssb_drv = drv_to_ssb_drv(dev->driver);
0290 
0291     if (ssb_drv && ssb_drv->remove)
0292         ssb_drv->remove(ssb_dev);
0293     ssb_device_put(ssb_dev);
0294 }
0295 
0296 static int ssb_device_probe(struct device *dev)
0297 {
0298     struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
0299     struct ssb_driver *ssb_drv = drv_to_ssb_drv(dev->driver);
0300     int err = 0;
0301 
0302     ssb_device_get(ssb_dev);
0303     if (ssb_drv && ssb_drv->probe)
0304         err = ssb_drv->probe(ssb_dev, &ssb_dev->id);
0305     if (err)
0306         ssb_device_put(ssb_dev);
0307 
0308     return err;
0309 }
0310 
0311 static int ssb_match_devid(const struct ssb_device_id *tabid,
0312                const struct ssb_device_id *devid)
0313 {
0314     if ((tabid->vendor != devid->vendor) &&
0315         tabid->vendor != SSB_ANY_VENDOR)
0316         return 0;
0317     if ((tabid->coreid != devid->coreid) &&
0318         tabid->coreid != SSB_ANY_ID)
0319         return 0;
0320     if ((tabid->revision != devid->revision) &&
0321         tabid->revision != SSB_ANY_REV)
0322         return 0;
0323     return 1;
0324 }
0325 
0326 static int ssb_bus_match(struct device *dev, struct device_driver *drv)
0327 {
0328     struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
0329     struct ssb_driver *ssb_drv = drv_to_ssb_drv(drv);
0330     const struct ssb_device_id *id;
0331 
0332     for (id = ssb_drv->id_table;
0333          id->vendor || id->coreid || id->revision;
0334          id++) {
0335         if (ssb_match_devid(id, &ssb_dev->id))
0336             return 1; /* found */
0337     }
0338 
0339     return 0;
0340 }
0341 
0342 static int ssb_device_uevent(struct device *dev, struct kobj_uevent_env *env)
0343 {
0344     struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
0345 
0346     if (!dev)
0347         return -ENODEV;
0348 
0349     return add_uevent_var(env,
0350                  "MODALIAS=ssb:v%04Xid%04Xrev%02X",
0351                  ssb_dev->id.vendor, ssb_dev->id.coreid,
0352                  ssb_dev->id.revision);
0353 }
0354 
0355 #define ssb_config_attr(attrib, field, format_string) \
0356 static ssize_t \
0357 attrib##_show(struct device *dev, struct device_attribute *attr, char *buf) \
0358 { \
0359     return sprintf(buf, format_string, dev_to_ssb_dev(dev)->field); \
0360 } \
0361 static DEVICE_ATTR_RO(attrib);
0362 
0363 ssb_config_attr(core_num, core_index, "%u\n")
0364 ssb_config_attr(coreid, id.coreid, "0x%04x\n")
0365 ssb_config_attr(vendor, id.vendor, "0x%04x\n")
0366 ssb_config_attr(revision, id.revision, "%u\n")
0367 ssb_config_attr(irq, irq, "%u\n")
0368 static ssize_t
0369 name_show(struct device *dev, struct device_attribute *attr, char *buf)
0370 {
0371     return sprintf(buf, "%s\n",
0372                ssb_core_name(dev_to_ssb_dev(dev)->id.coreid));
0373 }
0374 static DEVICE_ATTR_RO(name);
0375 
0376 static struct attribute *ssb_device_attrs[] = {
0377     &dev_attr_name.attr,
0378     &dev_attr_core_num.attr,
0379     &dev_attr_coreid.attr,
0380     &dev_attr_vendor.attr,
0381     &dev_attr_revision.attr,
0382     &dev_attr_irq.attr,
0383     NULL,
0384 };
0385 ATTRIBUTE_GROUPS(ssb_device);
0386 
0387 static struct bus_type ssb_bustype = {
0388     .name       = "ssb",
0389     .match      = ssb_bus_match,
0390     .probe      = ssb_device_probe,
0391     .remove     = ssb_device_remove,
0392     .shutdown   = ssb_device_shutdown,
0393     .suspend    = ssb_device_suspend,
0394     .resume     = ssb_device_resume,
0395     .uevent     = ssb_device_uevent,
0396     .dev_groups = ssb_device_groups,
0397 };
0398 
0399 static void ssb_buses_lock(void)
0400 {
0401     /* See the comment at the ssb_is_early_boot definition */
0402     if (!ssb_is_early_boot)
0403         mutex_lock(&buses_mutex);
0404 }
0405 
0406 static void ssb_buses_unlock(void)
0407 {
0408     /* See the comment at the ssb_is_early_boot definition */
0409     if (!ssb_is_early_boot)
0410         mutex_unlock(&buses_mutex);
0411 }
0412 
0413 static void ssb_devices_unregister(struct ssb_bus *bus)
0414 {
0415     struct ssb_device *sdev;
0416     int i;
0417 
0418     for (i = bus->nr_devices - 1; i >= 0; i--) {
0419         sdev = &(bus->devices[i]);
0420         if (sdev->dev)
0421             device_unregister(sdev->dev);
0422     }
0423 
0424 #ifdef CONFIG_SSB_EMBEDDED
0425     if (bus->bustype == SSB_BUSTYPE_SSB)
0426         platform_device_unregister(bus->watchdog);
0427 #endif
0428 }
0429 
0430 void ssb_bus_unregister(struct ssb_bus *bus)
0431 {
0432     int err;
0433 
0434     err = ssb_gpio_unregister(bus);
0435     if (err)
0436         pr_debug("Can not unregister GPIO driver: %i\n", err);
0437 
0438     ssb_buses_lock();
0439     ssb_devices_unregister(bus);
0440     list_del(&bus->list);
0441     ssb_buses_unlock();
0442 
0443     ssb_pcmcia_exit(bus);
0444     ssb_pci_exit(bus);
0445     ssb_iounmap(bus);
0446 }
0447 EXPORT_SYMBOL(ssb_bus_unregister);
0448 
0449 static void ssb_release_dev(struct device *dev)
0450 {
0451     struct __ssb_dev_wrapper *devwrap;
0452 
0453     devwrap = container_of(dev, struct __ssb_dev_wrapper, dev);
0454     kfree(devwrap);
0455 }
0456 
0457 static int ssb_devices_register(struct ssb_bus *bus)
0458 {
0459     struct ssb_device *sdev;
0460     struct device *dev;
0461     struct __ssb_dev_wrapper *devwrap;
0462     int i, err = 0;
0463     int dev_idx = 0;
0464 
0465     for (i = 0; i < bus->nr_devices; i++) {
0466         sdev = &(bus->devices[i]);
0467 
0468         /* We don't register SSB-system devices to the kernel,
0469          * as the drivers for them are built into SSB.
0470          */
0471         switch (sdev->id.coreid) {
0472         case SSB_DEV_CHIPCOMMON:
0473         case SSB_DEV_PCI:
0474         case SSB_DEV_PCIE:
0475         case SSB_DEV_PCMCIA:
0476         case SSB_DEV_MIPS:
0477         case SSB_DEV_MIPS_3302:
0478         case SSB_DEV_EXTIF:
0479             continue;
0480         }
0481 
0482         devwrap = kzalloc(sizeof(*devwrap), GFP_KERNEL);
0483         if (!devwrap) {
0484             err = -ENOMEM;
0485             goto error;
0486         }
0487         dev = &devwrap->dev;
0488         devwrap->sdev = sdev;
0489 
0490         dev->release = ssb_release_dev;
0491         dev->bus = &ssb_bustype;
0492         dev_set_name(dev, "ssb%u:%d", bus->busnumber, dev_idx);
0493 
0494         switch (bus->bustype) {
0495         case SSB_BUSTYPE_PCI:
0496 #ifdef CONFIG_SSB_PCIHOST
0497             sdev->irq = bus->host_pci->irq;
0498             dev->parent = &bus->host_pci->dev;
0499             sdev->dma_dev = dev->parent;
0500 #endif
0501             break;
0502         case SSB_BUSTYPE_PCMCIA:
0503 #ifdef CONFIG_SSB_PCMCIAHOST
0504             sdev->irq = bus->host_pcmcia->irq;
0505             dev->parent = &bus->host_pcmcia->dev;
0506 #endif
0507             break;
0508         case SSB_BUSTYPE_SDIO:
0509 #ifdef CONFIG_SSB_SDIOHOST
0510             dev->parent = &bus->host_sdio->dev;
0511 #endif
0512             break;
0513         case SSB_BUSTYPE_SSB:
0514             dev->dma_mask = &dev->coherent_dma_mask;
0515             sdev->dma_dev = dev;
0516             break;
0517         }
0518 
0519         sdev->dev = dev;
0520         err = device_register(dev);
0521         if (err) {
0522             pr_err("Could not register %s\n", dev_name(dev));
0523             /* Set dev to NULL to not unregister
0524              * dev on error unwinding.
0525              */
0526             sdev->dev = NULL;
0527             put_device(dev);
0528             goto error;
0529         }
0530         dev_idx++;
0531     }
0532 
0533 #ifdef CONFIG_SSB_DRIVER_MIPS
0534     if (bus->mipscore.pflash.present) {
0535         err = platform_device_register(&ssb_pflash_dev);
0536         if (err)
0537             pr_err("Error registering parallel flash\n");
0538     }
0539 #endif
0540 
0541 #ifdef CONFIG_SSB_SFLASH
0542     if (bus->mipscore.sflash.present) {
0543         err = platform_device_register(&ssb_sflash_dev);
0544         if (err)
0545             pr_err("Error registering serial flash\n");
0546     }
0547 #endif
0548 
0549     return 0;
0550 error:
0551     /* Unwind the already registered devices. */
0552     ssb_devices_unregister(bus);
0553     return err;
0554 }
0555 
0556 /* Needs ssb_buses_lock() */
0557 static int ssb_attach_queued_buses(void)
0558 {
0559     struct ssb_bus *bus, *n;
0560     int err = 0;
0561     int drop_them_all = 0;
0562 
0563     list_for_each_entry_safe(bus, n, &attach_queue, list) {
0564         if (drop_them_all) {
0565             list_del(&bus->list);
0566             continue;
0567         }
0568         /* Can't init the PCIcore in ssb_bus_register(), as that
0569          * is too early in boot for embedded systems
0570          * (no udelay() available). So do it here in attach stage.
0571          */
0572         err = ssb_bus_powerup(bus, 0);
0573         if (err)
0574             goto error;
0575         ssb_pcicore_init(&bus->pcicore);
0576         if (bus->bustype == SSB_BUSTYPE_SSB)
0577             ssb_watchdog_register(bus);
0578 
0579         err = ssb_gpio_init(bus);
0580         if (err == -ENOTSUPP)
0581             pr_debug("GPIO driver not activated\n");
0582         else if (err)
0583             pr_debug("Error registering GPIO driver: %i\n", err);
0584 
0585         ssb_bus_may_powerdown(bus);
0586 
0587         err = ssb_devices_register(bus);
0588 error:
0589         if (err) {
0590             drop_them_all = 1;
0591             list_del(&bus->list);
0592             continue;
0593         }
0594         list_move_tail(&bus->list, &buses);
0595     }
0596 
0597     return err;
0598 }
0599 
0600 static int ssb_fetch_invariants(struct ssb_bus *bus,
0601                 ssb_invariants_func_t get_invariants)
0602 {
0603     struct ssb_init_invariants iv;
0604     int err;
0605 
0606     memset(&iv, 0, sizeof(iv));
0607     err = get_invariants(bus, &iv);
0608     if (err)
0609         goto out;
0610     memcpy(&bus->boardinfo, &iv.boardinfo, sizeof(iv.boardinfo));
0611     memcpy(&bus->sprom, &iv.sprom, sizeof(iv.sprom));
0612     bus->has_cardbus_slot = iv.has_cardbus_slot;
0613 out:
0614     return err;
0615 }
0616 
0617 static int __maybe_unused
0618 ssb_bus_register(struct ssb_bus *bus,
0619          ssb_invariants_func_t get_invariants,
0620          unsigned long baseaddr)
0621 {
0622     int err;
0623 
0624     spin_lock_init(&bus->bar_lock);
0625     INIT_LIST_HEAD(&bus->list);
0626 #ifdef CONFIG_SSB_EMBEDDED
0627     spin_lock_init(&bus->gpio_lock);
0628 #endif
0629 
0630     /* Powerup the bus */
0631     err = ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 1);
0632     if (err)
0633         goto out;
0634 
0635     /* Init SDIO-host device (if any), before the scan */
0636     err = ssb_sdio_init(bus);
0637     if (err)
0638         goto err_disable_xtal;
0639 
0640     ssb_buses_lock();
0641     bus->busnumber = next_busnumber;
0642     /* Scan for devices (cores) */
0643     err = ssb_bus_scan(bus, baseaddr);
0644     if (err)
0645         goto err_sdio_exit;
0646 
0647     /* Init PCI-host device (if any) */
0648     err = ssb_pci_init(bus);
0649     if (err)
0650         goto err_unmap;
0651     /* Init PCMCIA-host device (if any) */
0652     err = ssb_pcmcia_init(bus);
0653     if (err)
0654         goto err_pci_exit;
0655 
0656     /* Initialize basic system devices (if available) */
0657     err = ssb_bus_powerup(bus, 0);
0658     if (err)
0659         goto err_pcmcia_exit;
0660     ssb_chipcommon_init(&bus->chipco);
0661     ssb_extif_init(&bus->extif);
0662     ssb_mipscore_init(&bus->mipscore);
0663     err = ssb_fetch_invariants(bus, get_invariants);
0664     if (err) {
0665         ssb_bus_may_powerdown(bus);
0666         goto err_pcmcia_exit;
0667     }
0668     ssb_bus_may_powerdown(bus);
0669 
0670     /* Queue it for attach.
0671      * See the comment at the ssb_is_early_boot definition.
0672      */
0673     list_add_tail(&bus->list, &attach_queue);
0674     if (!ssb_is_early_boot) {
0675         /* This is not early boot, so we must attach the bus now */
0676         err = ssb_attach_queued_buses();
0677         if (err)
0678             goto err_dequeue;
0679     }
0680     next_busnumber++;
0681     ssb_buses_unlock();
0682 
0683 out:
0684     return err;
0685 
0686 err_dequeue:
0687     list_del(&bus->list);
0688 err_pcmcia_exit:
0689     ssb_pcmcia_exit(bus);
0690 err_pci_exit:
0691     ssb_pci_exit(bus);
0692 err_unmap:
0693     ssb_iounmap(bus);
0694 err_sdio_exit:
0695     ssb_sdio_exit(bus);
0696 err_disable_xtal:
0697     ssb_buses_unlock();
0698     ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 0);
0699     return err;
0700 }
0701 
0702 #ifdef CONFIG_SSB_PCIHOST
0703 int ssb_bus_pcibus_register(struct ssb_bus *bus, struct pci_dev *host_pci)
0704 {
0705     int err;
0706 
0707     bus->bustype = SSB_BUSTYPE_PCI;
0708     bus->host_pci = host_pci;
0709     bus->ops = &ssb_pci_ops;
0710 
0711     err = ssb_bus_register(bus, ssb_pci_get_invariants, 0);
0712     if (!err) {
0713         dev_info(&host_pci->dev,
0714              "Sonics Silicon Backplane found on PCI device %s\n",
0715              dev_name(&host_pci->dev));
0716     } else {
0717         dev_err(&host_pci->dev,
0718             "Failed to register PCI version of SSB with error %d\n",
0719             err);
0720     }
0721 
0722     return err;
0723 }
0724 #endif /* CONFIG_SSB_PCIHOST */
0725 
0726 #ifdef CONFIG_SSB_PCMCIAHOST
0727 int ssb_bus_pcmciabus_register(struct ssb_bus *bus,
0728                    struct pcmcia_device *pcmcia_dev,
0729                    unsigned long baseaddr)
0730 {
0731     int err;
0732 
0733     bus->bustype = SSB_BUSTYPE_PCMCIA;
0734     bus->host_pcmcia = pcmcia_dev;
0735     bus->ops = &ssb_pcmcia_ops;
0736 
0737     err = ssb_bus_register(bus, ssb_pcmcia_get_invariants, baseaddr);
0738     if (!err) {
0739         dev_info(&pcmcia_dev->dev,
0740              "Sonics Silicon Backplane found on PCMCIA device %s\n",
0741              pcmcia_dev->devname);
0742     }
0743 
0744     return err;
0745 }
0746 #endif /* CONFIG_SSB_PCMCIAHOST */
0747 
0748 #ifdef CONFIG_SSB_SDIOHOST
0749 int ssb_bus_sdiobus_register(struct ssb_bus *bus, struct sdio_func *func,
0750                  unsigned int quirks)
0751 {
0752     int err;
0753 
0754     bus->bustype = SSB_BUSTYPE_SDIO;
0755     bus->host_sdio = func;
0756     bus->ops = &ssb_sdio_ops;
0757     bus->quirks = quirks;
0758 
0759     err = ssb_bus_register(bus, ssb_sdio_get_invariants, ~0);
0760     if (!err) {
0761         dev_info(&func->dev,
0762              "Sonics Silicon Backplane found on SDIO device %s\n",
0763              sdio_func_id(func));
0764     }
0765 
0766     return err;
0767 }
0768 EXPORT_SYMBOL(ssb_bus_sdiobus_register);
0769 #endif /* CONFIG_SSB_PCMCIAHOST */
0770 
0771 #ifdef CONFIG_SSB_HOST_SOC
0772 int ssb_bus_host_soc_register(struct ssb_bus *bus, unsigned long baseaddr)
0773 {
0774     int err;
0775 
0776     bus->bustype = SSB_BUSTYPE_SSB;
0777     bus->ops = &ssb_host_soc_ops;
0778 
0779     err = ssb_bus_register(bus, ssb_host_soc_get_invariants, baseaddr);
0780     if (!err) {
0781         pr_info("Sonics Silicon Backplane found at address 0x%08lX\n",
0782             baseaddr);
0783     }
0784 
0785     return err;
0786 }
0787 #endif
0788 
0789 int __ssb_driver_register(struct ssb_driver *drv, struct module *owner)
0790 {
0791     drv->drv.name = drv->name;
0792     drv->drv.bus = &ssb_bustype;
0793     drv->drv.owner = owner;
0794 
0795     return driver_register(&drv->drv);
0796 }
0797 EXPORT_SYMBOL(__ssb_driver_register);
0798 
0799 void ssb_driver_unregister(struct ssb_driver *drv)
0800 {
0801     driver_unregister(&drv->drv);
0802 }
0803 EXPORT_SYMBOL(ssb_driver_unregister);
0804 
0805 void ssb_set_devtypedata(struct ssb_device *dev, void *data)
0806 {
0807     struct ssb_bus *bus = dev->bus;
0808     struct ssb_device *ent;
0809     int i;
0810 
0811     for (i = 0; i < bus->nr_devices; i++) {
0812         ent = &(bus->devices[i]);
0813         if (ent->id.vendor != dev->id.vendor)
0814             continue;
0815         if (ent->id.coreid != dev->id.coreid)
0816             continue;
0817 
0818         ent->devtypedata = data;
0819     }
0820 }
0821 EXPORT_SYMBOL(ssb_set_devtypedata);
0822 
0823 static u32 clkfactor_f6_resolve(u32 v)
0824 {
0825     /* map the magic values */
0826     switch (v) {
0827     case SSB_CHIPCO_CLK_F6_2:
0828         return 2;
0829     case SSB_CHIPCO_CLK_F6_3:
0830         return 3;
0831     case SSB_CHIPCO_CLK_F6_4:
0832         return 4;
0833     case SSB_CHIPCO_CLK_F6_5:
0834         return 5;
0835     case SSB_CHIPCO_CLK_F6_6:
0836         return 6;
0837     case SSB_CHIPCO_CLK_F6_7:
0838         return 7;
0839     }
0840     return 0;
0841 }
0842 
0843 /* Calculate the speed the backplane would run at a given set of clockcontrol values */
0844 u32 ssb_calc_clock_rate(u32 plltype, u32 n, u32 m)
0845 {
0846     u32 n1, n2, clock, m1, m2, m3, mc;
0847 
0848     n1 = (n & SSB_CHIPCO_CLK_N1);
0849     n2 = ((n & SSB_CHIPCO_CLK_N2) >> SSB_CHIPCO_CLK_N2_SHIFT);
0850 
0851     switch (plltype) {
0852     case SSB_PLLTYPE_6: /* 100/200 or 120/240 only */
0853         if (m & SSB_CHIPCO_CLK_T6_MMASK)
0854             return SSB_CHIPCO_CLK_T6_M1;
0855         return SSB_CHIPCO_CLK_T6_M0;
0856     case SSB_PLLTYPE_1: /* 48Mhz base, 3 dividers */
0857     case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */
0858     case SSB_PLLTYPE_4: /* 48Mhz, 4 dividers */
0859     case SSB_PLLTYPE_7: /* 25Mhz, 4 dividers */
0860         n1 = clkfactor_f6_resolve(n1);
0861         n2 += SSB_CHIPCO_CLK_F5_BIAS;
0862         break;
0863     case SSB_PLLTYPE_2: /* 48Mhz, 4 dividers */
0864         n1 += SSB_CHIPCO_CLK_T2_BIAS;
0865         n2 += SSB_CHIPCO_CLK_T2_BIAS;
0866         WARN_ON(!((n1 >= 2) && (n1 <= 7)));
0867         WARN_ON(!((n2 >= 5) && (n2 <= 23)));
0868         break;
0869     case SSB_PLLTYPE_5: /* 25Mhz, 4 dividers */
0870         return 100000000;
0871     default:
0872         WARN_ON(1);
0873     }
0874 
0875     switch (plltype) {
0876     case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */
0877     case SSB_PLLTYPE_7: /* 25Mhz, 4 dividers */
0878         clock = SSB_CHIPCO_CLK_BASE2 * n1 * n2;
0879         break;
0880     default:
0881         clock = SSB_CHIPCO_CLK_BASE1 * n1 * n2;
0882     }
0883     if (!clock)
0884         return 0;
0885 
0886     m1 = (m & SSB_CHIPCO_CLK_M1);
0887     m2 = ((m & SSB_CHIPCO_CLK_M2) >> SSB_CHIPCO_CLK_M2_SHIFT);
0888     m3 = ((m & SSB_CHIPCO_CLK_M3) >> SSB_CHIPCO_CLK_M3_SHIFT);
0889     mc = ((m & SSB_CHIPCO_CLK_MC) >> SSB_CHIPCO_CLK_MC_SHIFT);
0890 
0891     switch (plltype) {
0892     case SSB_PLLTYPE_1: /* 48Mhz base, 3 dividers */
0893     case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */
0894     case SSB_PLLTYPE_4: /* 48Mhz, 4 dividers */
0895     case SSB_PLLTYPE_7: /* 25Mhz, 4 dividers */
0896         m1 = clkfactor_f6_resolve(m1);
0897         if ((plltype == SSB_PLLTYPE_1) ||
0898             (plltype == SSB_PLLTYPE_3))
0899             m2 += SSB_CHIPCO_CLK_F5_BIAS;
0900         else
0901             m2 = clkfactor_f6_resolve(m2);
0902         m3 = clkfactor_f6_resolve(m3);
0903 
0904         switch (mc) {
0905         case SSB_CHIPCO_CLK_MC_BYPASS:
0906             return clock;
0907         case SSB_CHIPCO_CLK_MC_M1:
0908             return (clock / m1);
0909         case SSB_CHIPCO_CLK_MC_M1M2:
0910             return (clock / (m1 * m2));
0911         case SSB_CHIPCO_CLK_MC_M1M2M3:
0912             return (clock / (m1 * m2 * m3));
0913         case SSB_CHIPCO_CLK_MC_M1M3:
0914             return (clock / (m1 * m3));
0915         }
0916         return 0;
0917     case SSB_PLLTYPE_2:
0918         m1 += SSB_CHIPCO_CLK_T2_BIAS;
0919         m2 += SSB_CHIPCO_CLK_T2M2_BIAS;
0920         m3 += SSB_CHIPCO_CLK_T2_BIAS;
0921         WARN_ON(!((m1 >= 2) && (m1 <= 7)));
0922         WARN_ON(!((m2 >= 3) && (m2 <= 10)));
0923         WARN_ON(!((m3 >= 2) && (m3 <= 7)));
0924 
0925         if (!(mc & SSB_CHIPCO_CLK_T2MC_M1BYP))
0926             clock /= m1;
0927         if (!(mc & SSB_CHIPCO_CLK_T2MC_M2BYP))
0928             clock /= m2;
0929         if (!(mc & SSB_CHIPCO_CLK_T2MC_M3BYP))
0930             clock /= m3;
0931         return clock;
0932     default:
0933         WARN_ON(1);
0934     }
0935     return 0;
0936 }
0937 
0938 /* Get the current speed the backplane is running at */
0939 u32 ssb_clockspeed(struct ssb_bus *bus)
0940 {
0941     u32 rate;
0942     u32 plltype;
0943     u32 clkctl_n, clkctl_m;
0944 
0945     if (bus->chipco.capabilities & SSB_CHIPCO_CAP_PMU)
0946         return ssb_pmu_get_controlclock(&bus->chipco);
0947 
0948     if (ssb_extif_available(&bus->extif))
0949         ssb_extif_get_clockcontrol(&bus->extif, &plltype,
0950                        &clkctl_n, &clkctl_m);
0951     else if (bus->chipco.dev)
0952         ssb_chipco_get_clockcontrol(&bus->chipco, &plltype,
0953                         &clkctl_n, &clkctl_m);
0954     else
0955         return 0;
0956 
0957     if (bus->chip_id == 0x5365) {
0958         rate = 100000000;
0959     } else {
0960         rate = ssb_calc_clock_rate(plltype, clkctl_n, clkctl_m);
0961         if (plltype == SSB_PLLTYPE_3) /* 25Mhz, 2 dividers */
0962             rate /= 2;
0963     }
0964 
0965     return rate;
0966 }
0967 EXPORT_SYMBOL(ssb_clockspeed);
0968 
0969 static u32 ssb_tmslow_reject_bitmask(struct ssb_device *dev)
0970 {
0971     u32 rev = ssb_read32(dev, SSB_IDLOW) & SSB_IDLOW_SSBREV;
0972 
0973     /* The REJECT bit seems to be different for Backplane rev 2.3 */
0974     switch (rev) {
0975     case SSB_IDLOW_SSBREV_22:
0976     case SSB_IDLOW_SSBREV_24:
0977     case SSB_IDLOW_SSBREV_26:
0978         return SSB_TMSLOW_REJECT;
0979     case SSB_IDLOW_SSBREV_23:
0980         return SSB_TMSLOW_REJECT_23;
0981     case SSB_IDLOW_SSBREV_25:     /* TODO - find the proper REJECT bit */
0982     case SSB_IDLOW_SSBREV_27:     /* same here */
0983         return SSB_TMSLOW_REJECT;   /* this is a guess */
0984     case SSB_IDLOW_SSBREV:
0985         break;
0986     default:
0987         WARN(1, KERN_INFO "ssb: Backplane Revision 0x%.8X\n", rev);
0988     }
0989     return (SSB_TMSLOW_REJECT | SSB_TMSLOW_REJECT_23);
0990 }
0991 
0992 int ssb_device_is_enabled(struct ssb_device *dev)
0993 {
0994     u32 val;
0995     u32 reject;
0996 
0997     reject = ssb_tmslow_reject_bitmask(dev);
0998     val = ssb_read32(dev, SSB_TMSLOW);
0999     val &= SSB_TMSLOW_CLOCK | SSB_TMSLOW_RESET | reject;
1000 
1001     return (val == SSB_TMSLOW_CLOCK);
1002 }
1003 EXPORT_SYMBOL(ssb_device_is_enabled);
1004 
1005 static void ssb_flush_tmslow(struct ssb_device *dev)
1006 {
1007     /* Make _really_ sure the device has finished the TMSLOW
1008      * register write transaction, as we risk running into
1009      * a machine check exception otherwise.
1010      * Do this by reading the register back to commit the
1011      * PCI write and delay an additional usec for the device
1012      * to react to the change.
1013      */
1014     ssb_read32(dev, SSB_TMSLOW);
1015     udelay(1);
1016 }
1017 
1018 void ssb_device_enable(struct ssb_device *dev, u32 core_specific_flags)
1019 {
1020     u32 val;
1021 
1022     ssb_device_disable(dev, core_specific_flags);
1023     ssb_write32(dev, SSB_TMSLOW,
1024             SSB_TMSLOW_RESET | SSB_TMSLOW_CLOCK |
1025             SSB_TMSLOW_FGC | core_specific_flags);
1026     ssb_flush_tmslow(dev);
1027 
1028     /* Clear SERR if set. This is a hw bug workaround. */
1029     if (ssb_read32(dev, SSB_TMSHIGH) & SSB_TMSHIGH_SERR)
1030         ssb_write32(dev, SSB_TMSHIGH, 0);
1031 
1032     val = ssb_read32(dev, SSB_IMSTATE);
1033     if (val & (SSB_IMSTATE_IBE | SSB_IMSTATE_TO)) {
1034         val &= ~(SSB_IMSTATE_IBE | SSB_IMSTATE_TO);
1035         ssb_write32(dev, SSB_IMSTATE, val);
1036     }
1037 
1038     ssb_write32(dev, SSB_TMSLOW,
1039             SSB_TMSLOW_CLOCK | SSB_TMSLOW_FGC |
1040             core_specific_flags);
1041     ssb_flush_tmslow(dev);
1042 
1043     ssb_write32(dev, SSB_TMSLOW, SSB_TMSLOW_CLOCK |
1044             core_specific_flags);
1045     ssb_flush_tmslow(dev);
1046 }
1047 EXPORT_SYMBOL(ssb_device_enable);
1048 
1049 /* Wait for bitmask in a register to get set or cleared.
1050  * timeout is in units of ten-microseconds
1051  */
1052 static int ssb_wait_bits(struct ssb_device *dev, u16 reg, u32 bitmask,
1053              int timeout, int set)
1054 {
1055     int i;
1056     u32 val;
1057 
1058     for (i = 0; i < timeout; i++) {
1059         val = ssb_read32(dev, reg);
1060         if (set) {
1061             if ((val & bitmask) == bitmask)
1062                 return 0;
1063         } else {
1064             if (!(val & bitmask))
1065                 return 0;
1066         }
1067         udelay(10);
1068     }
1069     dev_err(dev->dev,
1070         "Timeout waiting for bitmask %08X on register %04X to %s\n",
1071         bitmask, reg, set ? "set" : "clear");
1072 
1073     return -ETIMEDOUT;
1074 }
1075 
1076 void ssb_device_disable(struct ssb_device *dev, u32 core_specific_flags)
1077 {
1078     u32 reject, val;
1079 
1080     if (ssb_read32(dev, SSB_TMSLOW) & SSB_TMSLOW_RESET)
1081         return;
1082 
1083     reject = ssb_tmslow_reject_bitmask(dev);
1084 
1085     if (ssb_read32(dev, SSB_TMSLOW) & SSB_TMSLOW_CLOCK) {
1086         ssb_write32(dev, SSB_TMSLOW, reject | SSB_TMSLOW_CLOCK);
1087         ssb_wait_bits(dev, SSB_TMSLOW, reject, 1000, 1);
1088         ssb_wait_bits(dev, SSB_TMSHIGH, SSB_TMSHIGH_BUSY, 1000, 0);
1089 
1090         if (ssb_read32(dev, SSB_IDLOW) & SSB_IDLOW_INITIATOR) {
1091             val = ssb_read32(dev, SSB_IMSTATE);
1092             val |= SSB_IMSTATE_REJECT;
1093             ssb_write32(dev, SSB_IMSTATE, val);
1094             ssb_wait_bits(dev, SSB_IMSTATE, SSB_IMSTATE_BUSY, 1000,
1095                       0);
1096         }
1097 
1098         ssb_write32(dev, SSB_TMSLOW,
1099             SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK |
1100             reject | SSB_TMSLOW_RESET |
1101             core_specific_flags);
1102         ssb_flush_tmslow(dev);
1103 
1104         if (ssb_read32(dev, SSB_IDLOW) & SSB_IDLOW_INITIATOR) {
1105             val = ssb_read32(dev, SSB_IMSTATE);
1106             val &= ~SSB_IMSTATE_REJECT;
1107             ssb_write32(dev, SSB_IMSTATE, val);
1108         }
1109     }
1110 
1111     ssb_write32(dev, SSB_TMSLOW,
1112             reject | SSB_TMSLOW_RESET |
1113             core_specific_flags);
1114     ssb_flush_tmslow(dev);
1115 }
1116 EXPORT_SYMBOL(ssb_device_disable);
1117 
1118 /* Some chipsets need routing known for PCIe and 64-bit DMA */
1119 static bool ssb_dma_translation_special_bit(struct ssb_device *dev)
1120 {
1121     u16 chip_id = dev->bus->chip_id;
1122 
1123     if (dev->id.coreid == SSB_DEV_80211) {
1124         return (chip_id == 0x4322 || chip_id == 43221 ||
1125             chip_id == 43231 || chip_id == 43222);
1126     }
1127 
1128     return false;
1129 }
1130 
1131 u32 ssb_dma_translation(struct ssb_device *dev)
1132 {
1133     switch (dev->bus->bustype) {
1134     case SSB_BUSTYPE_SSB:
1135         return 0;
1136     case SSB_BUSTYPE_PCI:
1137         if (pci_is_pcie(dev->bus->host_pci) &&
1138             ssb_read32(dev, SSB_TMSHIGH) & SSB_TMSHIGH_DMA64) {
1139             return SSB_PCIE_DMA_H32;
1140         } else {
1141             if (ssb_dma_translation_special_bit(dev))
1142                 return SSB_PCIE_DMA_H32;
1143             else
1144                 return SSB_PCI_DMA;
1145         }
1146     default:
1147         __ssb_dma_not_implemented(dev);
1148     }
1149     return 0;
1150 }
1151 EXPORT_SYMBOL(ssb_dma_translation);
1152 
1153 int ssb_bus_may_powerdown(struct ssb_bus *bus)
1154 {
1155     struct ssb_chipcommon *cc;
1156     int err = 0;
1157 
1158     /* On buses where more than one core may be working
1159      * at a time, we must not powerdown stuff if there are
1160      * still cores that may want to run.
1161      */
1162     if (bus->bustype == SSB_BUSTYPE_SSB)
1163         goto out;
1164 
1165     cc = &bus->chipco;
1166 
1167     if (!cc->dev)
1168         goto out;
1169     if (cc->dev->id.revision < 5)
1170         goto out;
1171 
1172     ssb_chipco_set_clockmode(cc, SSB_CLKMODE_SLOW);
1173     err = ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 0);
1174     if (err)
1175         goto error;
1176 out:
1177     bus->powered_up = 0;
1178     return err;
1179 error:
1180     pr_err("Bus powerdown failed\n");
1181     goto out;
1182 }
1183 EXPORT_SYMBOL(ssb_bus_may_powerdown);
1184 
1185 int ssb_bus_powerup(struct ssb_bus *bus, bool dynamic_pctl)
1186 {
1187     int err;
1188     enum ssb_clkmode mode;
1189 
1190     err = ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 1);
1191     if (err)
1192         goto error;
1193 
1194     bus->powered_up = 1;
1195 
1196     mode = dynamic_pctl ? SSB_CLKMODE_DYNAMIC : SSB_CLKMODE_FAST;
1197     ssb_chipco_set_clockmode(&bus->chipco, mode);
1198 
1199     return 0;
1200 error:
1201     pr_err("Bus powerup failed\n");
1202     return err;
1203 }
1204 EXPORT_SYMBOL(ssb_bus_powerup);
1205 
1206 static void ssb_broadcast_value(struct ssb_device *dev,
1207                 u32 address, u32 data)
1208 {
1209 #ifdef CONFIG_SSB_DRIVER_PCICORE
1210     /* This is used for both, PCI and ChipCommon core, so be careful. */
1211     BUILD_BUG_ON(SSB_PCICORE_BCAST_ADDR != SSB_CHIPCO_BCAST_ADDR);
1212     BUILD_BUG_ON(SSB_PCICORE_BCAST_DATA != SSB_CHIPCO_BCAST_DATA);
1213 #endif
1214 
1215     ssb_write32(dev, SSB_CHIPCO_BCAST_ADDR, address);
1216     ssb_read32(dev, SSB_CHIPCO_BCAST_ADDR); /* flush */
1217     ssb_write32(dev, SSB_CHIPCO_BCAST_DATA, data);
1218     ssb_read32(dev, SSB_CHIPCO_BCAST_DATA); /* flush */
1219 }
1220 
1221 void ssb_commit_settings(struct ssb_bus *bus)
1222 {
1223     struct ssb_device *dev;
1224 
1225 #ifdef CONFIG_SSB_DRIVER_PCICORE
1226     dev = bus->chipco.dev ? bus->chipco.dev : bus->pcicore.dev;
1227 #else
1228     dev = bus->chipco.dev;
1229 #endif
1230     if (WARN_ON(!dev))
1231         return;
1232     /* This forces an update of the cached registers. */
1233     ssb_broadcast_value(dev, 0xFD8, 0);
1234 }
1235 EXPORT_SYMBOL(ssb_commit_settings);
1236 
1237 u32 ssb_admatch_base(u32 adm)
1238 {
1239     u32 base = 0;
1240 
1241     switch (adm & SSB_ADM_TYPE) {
1242     case SSB_ADM_TYPE0:
1243         base = (adm & SSB_ADM_BASE0);
1244         break;
1245     case SSB_ADM_TYPE1:
1246         WARN_ON(adm & SSB_ADM_NEG); /* unsupported */
1247         base = (adm & SSB_ADM_BASE1);
1248         break;
1249     case SSB_ADM_TYPE2:
1250         WARN_ON(adm & SSB_ADM_NEG); /* unsupported */
1251         base = (adm & SSB_ADM_BASE2);
1252         break;
1253     default:
1254         WARN_ON(1);
1255     }
1256 
1257     return base;
1258 }
1259 EXPORT_SYMBOL(ssb_admatch_base);
1260 
1261 u32 ssb_admatch_size(u32 adm)
1262 {
1263     u32 size = 0;
1264 
1265     switch (adm & SSB_ADM_TYPE) {
1266     case SSB_ADM_TYPE0:
1267         size = ((adm & SSB_ADM_SZ0) >> SSB_ADM_SZ0_SHIFT);
1268         break;
1269     case SSB_ADM_TYPE1:
1270         WARN_ON(adm & SSB_ADM_NEG); /* unsupported */
1271         size = ((adm & SSB_ADM_SZ1) >> SSB_ADM_SZ1_SHIFT);
1272         break;
1273     case SSB_ADM_TYPE2:
1274         WARN_ON(adm & SSB_ADM_NEG); /* unsupported */
1275         size = ((adm & SSB_ADM_SZ2) >> SSB_ADM_SZ2_SHIFT);
1276         break;
1277     default:
1278         WARN_ON(1);
1279     }
1280     size = (1 << (size + 1));
1281 
1282     return size;
1283 }
1284 EXPORT_SYMBOL(ssb_admatch_size);
1285 
1286 static int __init ssb_modinit(void)
1287 {
1288     int err;
1289 
1290     /* See the comment at the ssb_is_early_boot definition */
1291     ssb_is_early_boot = 0;
1292     err = bus_register(&ssb_bustype);
1293     if (err)
1294         return err;
1295 
1296     /* Maybe we already registered some buses at early boot.
1297      * Check for this and attach them
1298      */
1299     ssb_buses_lock();
1300     err = ssb_attach_queued_buses();
1301     ssb_buses_unlock();
1302     if (err) {
1303         bus_unregister(&ssb_bustype);
1304         goto out;
1305     }
1306 
1307     err = b43_pci_ssb_bridge_init();
1308     if (err) {
1309         pr_err("Broadcom 43xx PCI-SSB-bridge initialization failed\n");
1310         /* don't fail SSB init because of this */
1311     }
1312     err = ssb_host_pcmcia_init();
1313     if (err) {
1314         pr_err("PCMCIA host initialization failed\n");
1315         /* don't fail SSB init because of this */
1316     }
1317     err = ssb_gige_init();
1318     if (err) {
1319         pr_err("SSB Broadcom Gigabit Ethernet driver initialization failed\n");
1320         /* don't fail SSB init because of this */
1321         err = 0;
1322     }
1323 out:
1324     return err;
1325 }
1326 /* ssb must be initialized after PCI but before the ssb drivers.
1327  * That means we must use some initcall between subsys_initcall
1328  * and device_initcall.
1329  */
1330 fs_initcall(ssb_modinit);
1331 
1332 static void __exit ssb_modexit(void)
1333 {
1334     ssb_gige_exit();
1335     ssb_host_pcmcia_exit();
1336     b43_pci_ssb_bridge_exit();
1337     bus_unregister(&ssb_bustype);
1338 }
1339 module_exit(ssb_modexit)
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