drivers/ssb/driver_mipscore.c

0001 /*
0002  * Sonics Silicon Backplane
0003  * Broadcom MIPS core driver
0004  *
0005  * Copyright 2005, Broadcom Corporation
0006  * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
0007  *
0008  * Licensed under the GNU/GPL. See COPYING for details.
0009  */
0010
0011 #include "ssb_private.h"
0012
0013 #include <linux/ssb/ssb.h>
0014
0015 #include <linux/mtd/physmap.h>
0016 #include <linux/serial.h>
0017 #include <linux/serial_core.h>
0018 #include <linux/serial_reg.h>
0019 #include <linux/time.h>
0020 #ifdef CONFIG_BCM47XX
0021 #include <linux/bcm47xx_nvram.h>
0022 #endif
0023
0024 static const char * const part_probes[] = { "bcm47xxpart", NULL };
0025
0026 static struct physmap_flash_data ssb_pflash_data = {
0027     .part_probe_types   = part_probes,
0028 };
0029
0030 static struct resource ssb_pflash_resource = {
0031     .name   = "ssb_pflash",
0032     .flags  = IORESOURCE_MEM,
0033 };
0034
0035 struct platform_device ssb_pflash_dev = {
0036     .name       = "physmap-flash",
0037     .dev        = {
0038         .platform_data  = &ssb_pflash_data,
0039     },
0040     .resource   = &ssb_pflash_resource,
0041     .num_resources  = 1,
0042 };
0043
0044 static inline u32 mips_read32(struct ssb_mipscore *mcore,
0045                   u16 offset)
0046 {
0047     return ssb_read32(mcore->dev, offset);
0048 }
0049
0050 static inline void mips_write32(struct ssb_mipscore *mcore,
0051                 u16 offset,
0052                 u32 value)
0053 {
0054     ssb_write32(mcore->dev, offset, value);
0055 }
0056
0057 static const u32 ipsflag_irq_mask[] = {
0058     0,
0059     SSB_IPSFLAG_IRQ1,
0060     SSB_IPSFLAG_IRQ2,
0061     SSB_IPSFLAG_IRQ3,
0062     SSB_IPSFLAG_IRQ4,
0063 };
0064
0065 static const u32 ipsflag_irq_shift[] = {
0066     0,
0067     SSB_IPSFLAG_IRQ1_SHIFT,
0068     SSB_IPSFLAG_IRQ2_SHIFT,
0069     SSB_IPSFLAG_IRQ3_SHIFT,
0070     SSB_IPSFLAG_IRQ4_SHIFT,
0071 };
0072
0073 static inline u32 ssb_irqflag(struct ssb_device *dev)
0074 {
0075     u32 tpsflag = ssb_read32(dev, SSB_TPSFLAG);
0076     if (tpsflag)
0077         return ssb_read32(dev, SSB_TPSFLAG) & SSB_TPSFLAG_BPFLAG;
0078     else
0079         /* not irq supported */
0080         return 0x3f;
0081 }
0082
0083 static struct ssb_device *find_device(struct ssb_device *rdev, int irqflag)
0084 {
0085     struct ssb_bus *bus = rdev->bus;
0086     int i;
0087     for (i = 0; i < bus->nr_devices; i++) {
0088         struct ssb_device *dev;
0089         dev = &(bus->devices[i]);
0090         if (ssb_irqflag(dev) == irqflag)
0091             return dev;
0092     }
0093     return NULL;
0094 }
0095
0096 /* Get the MIPS IRQ assignment for a specified device.
0097  * If unassigned, 0 is returned.
0098  * If disabled, 5 is returned.
0099  * If not supported, 6 is returned.
0100  */
0101 unsigned int ssb_mips_irq(struct ssb_device *dev)
0102 {
0103     struct ssb_bus *bus = dev->bus;
0104     struct ssb_device *mdev = bus->mipscore.dev;
0105     u32 irqflag;
0106     u32 ipsflag;
0107     u32 tmp;
0108     unsigned int irq;
0109
0110     irqflag = ssb_irqflag(dev);
0111     if (irqflag == 0x3f)
0112         return 6;
0113     ipsflag = ssb_read32(bus->mipscore.dev, SSB_IPSFLAG);
0114     for (irq = 1; irq <= 4; irq++) {
0115         tmp = ((ipsflag & ipsflag_irq_mask[irq]) >> ipsflag_irq_shift[irq]);
0116         if (tmp == irqflag)
0117             break;
0118     }
0119     if (irq == 5) {
0120         if ((1 << irqflag) & ssb_read32(mdev, SSB_INTVEC))
0121             irq = 0;
0122     }
0123
0124     return irq;
0125 }
0126
0127 static void clear_irq(struct ssb_bus *bus, unsigned int irq)
0128 {
0129     struct ssb_device *dev = bus->mipscore.dev;
0130
0131     /* Clear the IRQ in the MIPScore backplane registers */
0132     if (irq == 0) {
0133         ssb_write32(dev, SSB_INTVEC, 0);
0134     } else {
0135         ssb_write32(dev, SSB_IPSFLAG,
0136                 ssb_read32(dev, SSB_IPSFLAG) |
0137                 ipsflag_irq_mask[irq]);
0138     }
0139 }
0140
0141 static void set_irq(struct ssb_device *dev, unsigned int irq)
0142 {
0143     unsigned int oldirq = ssb_mips_irq(dev);
0144     struct ssb_bus *bus = dev->bus;
0145     struct ssb_device *mdev = bus->mipscore.dev;
0146     u32 irqflag = ssb_irqflag(dev);
0147
0148     BUG_ON(oldirq == 6);
0149
0150     dev->irq = irq + 2;
0151
0152     /* clear the old irq */
0153     if (oldirq == 0)
0154         ssb_write32(mdev, SSB_INTVEC, (~(1 << irqflag) & ssb_read32(mdev, SSB_INTVEC)));
0155     else if (oldirq != 5)
0156         clear_irq(bus, oldirq);
0157
0158     /* assign the new one */
0159     if (irq == 0) {
0160         ssb_write32(mdev, SSB_INTVEC, ((1 << irqflag) | ssb_read32(mdev, SSB_INTVEC)));
0161     } else {
0162         u32 ipsflag = ssb_read32(mdev, SSB_IPSFLAG);
0163         if ((ipsflag & ipsflag_irq_mask[irq]) != ipsflag_irq_mask[irq]) {
0164             u32 oldipsflag = (ipsflag & ipsflag_irq_mask[irq]) >> ipsflag_irq_shift[irq];
0165             struct ssb_device *olddev = find_device(dev, oldipsflag);
0166             if (olddev)
0167                 set_irq(olddev, 0);
0168         }
0169         irqflag <<= ipsflag_irq_shift[irq];
0170         irqflag |= (ipsflag & ~ipsflag_irq_mask[irq]);
0171         ssb_write32(mdev, SSB_IPSFLAG, irqflag);
0172     }
0173     dev_dbg(dev->dev, "set_irq: core 0x%04x, irq %d => %d\n",
0174         dev->id.coreid, oldirq+2, irq+2);
0175 }
0176
0177 static void print_irq(struct ssb_device *dev, unsigned int irq)
0178 {
0179     static const char *irq_name[] = {"2(S)", "3", "4", "5", "6", "D", "I"};
0180     dev_dbg(dev->dev,
0181         "core 0x%04x, irq : %s%s %s%s %s%s %s%s %s%s %s%s %s%s\n",
0182         dev->id.coreid,
0183         irq_name[0], irq == 0 ? "*" : " ",
0184         irq_name[1], irq == 1 ? "*" : " ",
0185         irq_name[2], irq == 2 ? "*" : " ",
0186         irq_name[3], irq == 3 ? "*" : " ",
0187         irq_name[4], irq == 4 ? "*" : " ",
0188         irq_name[5], irq == 5 ? "*" : " ",
0189         irq_name[6], irq == 6 ? "*" : " ");
0190 }
0191
0192 static void dump_irq(struct ssb_bus *bus)
0193 {
0194     int i;
0195     for (i = 0; i < bus->nr_devices; i++) {
0196         struct ssb_device *dev;
0197         dev = &(bus->devices[i]);
0198         print_irq(dev, ssb_mips_irq(dev));
0199     }
0200 }
0201
0202 static void ssb_mips_serial_init(struct ssb_mipscore *mcore)
0203 {
0204     struct ssb_bus *bus = mcore->dev->bus;
0205
0206     if (ssb_extif_available(&bus->extif))
0207         mcore->nr_serial_ports = ssb_extif_serial_init(&bus->extif, mcore->serial_ports);
0208     else if (ssb_chipco_available(&bus->chipco))
0209         mcore->nr_serial_ports = ssb_chipco_serial_init(&bus->chipco, mcore->serial_ports);
0210     else
0211         mcore->nr_serial_ports = 0;
0212 }
0213
0214 static void ssb_mips_flash_detect(struct ssb_mipscore *mcore)
0215 {
0216     struct ssb_bus *bus = mcore->dev->bus;
0217     struct ssb_sflash *sflash = &mcore->sflash;
0218     struct ssb_pflash *pflash = &mcore->pflash;
0219
0220     /* When there is no chipcommon on the bus there is 4MB flash */
0221     if (!ssb_chipco_available(&bus->chipco)) {
0222         pflash->present = true;
0223         pflash->buswidth = 2;
0224         pflash->window = SSB_FLASH1;
0225         pflash->window_size = SSB_FLASH1_SZ;
0226         goto ssb_pflash;
0227     }
0228
0229     /* There is ChipCommon, so use it to read info about flash */
0230     switch (bus->chipco.capabilities & SSB_CHIPCO_CAP_FLASHT) {
0231     case SSB_CHIPCO_FLASHT_STSER:
0232     case SSB_CHIPCO_FLASHT_ATSER:
0233         dev_dbg(mcore->dev->dev, "Found serial flash\n");
0234         ssb_sflash_init(&bus->chipco);
0235         break;
0236     case SSB_CHIPCO_FLASHT_PARA:
0237         dev_dbg(mcore->dev->dev, "Found parallel flash\n");
0238         pflash->present = true;
0239         pflash->window = SSB_FLASH2;
0240         pflash->window_size = SSB_FLASH2_SZ;
0241         if ((ssb_read32(bus->chipco.dev, SSB_CHIPCO_FLASH_CFG)
0242                        & SSB_CHIPCO_CFG_DS16) == 0)
0243             pflash->buswidth = 1;
0244         else
0245             pflash->buswidth = 2;
0246         break;
0247     }
0248
0249 ssb_pflash:
0250     if (sflash->present) {
0251 #ifdef CONFIG_BCM47XX
0252         bcm47xx_nvram_init_from_mem(sflash->window, sflash->size);
0253 #endif
0254     } else if (pflash->present) {
0255 #ifdef CONFIG_BCM47XX
0256         bcm47xx_nvram_init_from_mem(pflash->window, pflash->window_size);
0257 #endif
0258
0259         ssb_pflash_data.width = pflash->buswidth;
0260         ssb_pflash_resource.start = pflash->window;
0261         ssb_pflash_resource.end = pflash->window + pflash->window_size;
0262     }
0263 }
0264
0265 u32 ssb_cpu_clock(struct ssb_mipscore *mcore)
0266 {
0267     struct ssb_bus *bus = mcore->dev->bus;
0268     u32 pll_type, n, m, rate = 0;
0269
0270     if (bus->chipco.capabilities & SSB_CHIPCO_CAP_PMU)
0271         return ssb_pmu_get_cpu_clock(&bus->chipco);
0272
0273     if (ssb_extif_available(&bus->extif)) {
0274         ssb_extif_get_clockcontrol(&bus->extif, &pll_type, &n, &m);
0275     } else if (ssb_chipco_available(&bus->chipco)) {
0276         ssb_chipco_get_clockcpu(&bus->chipco, &pll_type, &n, &m);
0277     } else
0278         return 0;
0279
0280     if ((pll_type == SSB_PLLTYPE_5) || (bus->chip_id == 0x5365)) {
0281         rate = 200000000;
0282     } else {
0283         rate = ssb_calc_clock_rate(pll_type, n, m);
0284     }
0285
0286     if (pll_type == SSB_PLLTYPE_6) {
0287         rate *= 2;
0288     }
0289
0290     return rate;
0291 }
0292
0293 void ssb_mipscore_init(struct ssb_mipscore *mcore)
0294 {
0295     struct ssb_bus *bus;
0296     struct ssb_device *dev;
0297     unsigned long hz, ns;
0298     unsigned int irq, i;
0299
0300     if (!mcore->dev)
0301         return; /* We don't have a MIPS core */
0302
0303     dev_dbg(mcore->dev->dev, "Initializing MIPS core...\n");
0304
0305     bus = mcore->dev->bus;
0306     hz = ssb_clockspeed(bus);
0307     if (!hz)
0308         hz = 100000000;
0309     ns = 1000000000 / hz;
0310
0311     if (ssb_extif_available(&bus->extif))
0312         ssb_extif_timing_init(&bus->extif, ns);
0313     else if (ssb_chipco_available(&bus->chipco))
0314         ssb_chipco_timing_init(&bus->chipco, ns);
0315
0316     /* Assign IRQs to all cores on the bus, start with irq line 2, because serial usually takes 1 */
0317     for (irq = 2, i = 0; i < bus->nr_devices; i++) {
0318         int mips_irq;
0319         dev = &(bus->devices[i]);
0320         mips_irq = ssb_mips_irq(dev);
0321         if (mips_irq > 4)
0322             dev->irq = 0;
0323         else
0324             dev->irq = mips_irq + 2;
0325         if (dev->irq > 5)
0326             continue;
0327         switch (dev->id.coreid) {
0328         case SSB_DEV_USB11_HOST:
0329             /* shouldn't need a separate irq line for non-4710, most of them have a proper
0330              * external usb controller on the pci */
0331             if ((bus->chip_id == 0x4710) && (irq <= 4)) {
0332                 set_irq(dev, irq++);
0333             }
0334             break;
0335         case SSB_DEV_PCI:
0336         case SSB_DEV_ETHERNET:
0337         case SSB_DEV_ETHERNET_GBIT:
0338         case SSB_DEV_80211:
0339         case SSB_DEV_USB20_HOST:
0340             /* These devices get their own IRQ line if available, the rest goes on IRQ0 */
0341             if (irq <= 4) {
0342                 set_irq(dev, irq++);
0343                 break;
0344             }
0345             fallthrough;
0346         case SSB_DEV_EXTIF:
0347             set_irq(dev, 0);
0348             break;
0349         }
0350     }
0351     dev_dbg(mcore->dev->dev, "after irq reconfiguration\n");
0352     dump_irq(bus);
0353
0354     ssb_mips_serial_init(mcore);
0355     ssb_mips_flash_detect(mcore);
0356 }