drivers/ssb/driver_gige.c

0001 /*
0002  * Sonics Silicon Backplane
0003  * Broadcom Gigabit Ethernet core driver
0004  *
0005  * Copyright 2008, Broadcom Corporation
0006  * Copyright 2008, Michael Buesch <m@bues.ch>
0007  *
0008  * Licensed under the GNU/GPL. See COPYING for details.
0009  */
0010
0011 #include <linux/ssb/ssb.h>
0012 #include <linux/ssb/ssb_driver_gige.h>
0013 #include <linux/export.h>
0014 #include <linux/pci.h>
0015 #include <linux/pci_regs.h>
0016 #include <linux/slab.h>
0017
0018
0019 /*
0020 MODULE_DESCRIPTION("SSB Broadcom Gigabit Ethernet driver");
0021 MODULE_AUTHOR("Michael Buesch");
0022 MODULE_LICENSE("GPL");
0023 */
0024
0025 static const struct ssb_device_id ssb_gige_tbl[] = {
0026     SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_ETHERNET_GBIT, SSB_ANY_REV),
0027     {},
0028 };
0029 /* MODULE_DEVICE_TABLE(ssb, ssb_gige_tbl); */
0030
0031
0032 static inline u8 gige_read8(struct ssb_gige *dev, u16 offset)
0033 {
0034     return ssb_read8(dev->dev, offset);
0035 }
0036
0037 static inline u16 gige_read16(struct ssb_gige *dev, u16 offset)
0038 {
0039     return ssb_read16(dev->dev, offset);
0040 }
0041
0042 static inline u32 gige_read32(struct ssb_gige *dev, u16 offset)
0043 {
0044     return ssb_read32(dev->dev, offset);
0045 }
0046
0047 static inline void gige_write8(struct ssb_gige *dev,
0048                    u16 offset, u8 value)
0049 {
0050     ssb_write8(dev->dev, offset, value);
0051 }
0052
0053 static inline void gige_write16(struct ssb_gige *dev,
0054                 u16 offset, u16 value)
0055 {
0056     ssb_write16(dev->dev, offset, value);
0057 }
0058
0059 static inline void gige_write32(struct ssb_gige *dev,
0060                 u16 offset, u32 value)
0061 {
0062     ssb_write32(dev->dev, offset, value);
0063 }
0064
0065 static inline
0066 u8 gige_pcicfg_read8(struct ssb_gige *dev, unsigned int offset)
0067 {
0068     BUG_ON(offset >= 256);
0069     return gige_read8(dev, SSB_GIGE_PCICFG + offset);
0070 }
0071
0072 static inline
0073 u16 gige_pcicfg_read16(struct ssb_gige *dev, unsigned int offset)
0074 {
0075     BUG_ON(offset >= 256);
0076     return gige_read16(dev, SSB_GIGE_PCICFG + offset);
0077 }
0078
0079 static inline
0080 u32 gige_pcicfg_read32(struct ssb_gige *dev, unsigned int offset)
0081 {
0082     BUG_ON(offset >= 256);
0083     return gige_read32(dev, SSB_GIGE_PCICFG + offset);
0084 }
0085
0086 static inline
0087 void gige_pcicfg_write8(struct ssb_gige *dev,
0088             unsigned int offset, u8 value)
0089 {
0090     BUG_ON(offset >= 256);
0091     gige_write8(dev, SSB_GIGE_PCICFG + offset, value);
0092 }
0093
0094 static inline
0095 void gige_pcicfg_write16(struct ssb_gige *dev,
0096              unsigned int offset, u16 value)
0097 {
0098     BUG_ON(offset >= 256);
0099     gige_write16(dev, SSB_GIGE_PCICFG + offset, value);
0100 }
0101
0102 static inline
0103 void gige_pcicfg_write32(struct ssb_gige *dev,
0104              unsigned int offset, u32 value)
0105 {
0106     BUG_ON(offset >= 256);
0107     gige_write32(dev, SSB_GIGE_PCICFG + offset, value);
0108 }
0109
0110 static int ssb_gige_pci_read_config(struct pci_bus *bus, unsigned int devfn,
0111                     int reg, int size, u32 *val)
0112 {
0113     struct ssb_gige *dev = container_of(bus->ops, struct ssb_gige, pci_ops);
0114     unsigned long flags;
0115
0116     if ((PCI_SLOT(devfn) > 0) || (PCI_FUNC(devfn) > 0))
0117         return PCIBIOS_DEVICE_NOT_FOUND;
0118     if (reg >= 256)
0119         return PCIBIOS_DEVICE_NOT_FOUND;
0120
0121     spin_lock_irqsave(&dev->lock, flags);
0122     switch (size) {
0123     case 1:
0124         *val = gige_pcicfg_read8(dev, reg);
0125         break;
0126     case 2:
0127         *val = gige_pcicfg_read16(dev, reg);
0128         break;
0129     case 4:
0130         *val = gige_pcicfg_read32(dev, reg);
0131         break;
0132     default:
0133         WARN_ON(1);
0134     }
0135     spin_unlock_irqrestore(&dev->lock, flags);
0136
0137     return PCIBIOS_SUCCESSFUL;
0138 }
0139
0140 static int ssb_gige_pci_write_config(struct pci_bus *bus, unsigned int devfn,
0141                      int reg, int size, u32 val)
0142 {
0143     struct ssb_gige *dev = container_of(bus->ops, struct ssb_gige, pci_ops);
0144     unsigned long flags;
0145
0146     if ((PCI_SLOT(devfn) > 0) || (PCI_FUNC(devfn) > 0))
0147         return PCIBIOS_DEVICE_NOT_FOUND;
0148     if (reg >= 256)
0149         return PCIBIOS_DEVICE_NOT_FOUND;
0150
0151     spin_lock_irqsave(&dev->lock, flags);
0152     switch (size) {
0153     case 1:
0154         gige_pcicfg_write8(dev, reg, val);
0155         break;
0156     case 2:
0157         gige_pcicfg_write16(dev, reg, val);
0158         break;
0159     case 4:
0160         gige_pcicfg_write32(dev, reg, val);
0161         break;
0162     default:
0163         WARN_ON(1);
0164     }
0165     spin_unlock_irqrestore(&dev->lock, flags);
0166
0167     return PCIBIOS_SUCCESSFUL;
0168 }
0169
0170 static int ssb_gige_probe(struct ssb_device *sdev,
0171               const struct ssb_device_id *id)
0172 {
0173     struct ssb_gige *dev;
0174     u32 base, tmslow, tmshigh;
0175
0176     dev = kzalloc(sizeof(*dev), GFP_KERNEL);
0177     if (!dev)
0178         return -ENOMEM;
0179     dev->dev = sdev;
0180
0181     spin_lock_init(&dev->lock);
0182     dev->pci_controller.pci_ops = &dev->pci_ops;
0183     dev->pci_controller.io_resource = &dev->io_resource;
0184     dev->pci_controller.mem_resource = &dev->mem_resource;
0185     dev->pci_controller.io_map_base = 0x800;
0186     dev->pci_ops.read = ssb_gige_pci_read_config;
0187     dev->pci_ops.write = ssb_gige_pci_write_config;
0188
0189     dev->io_resource.name = SSB_GIGE_IO_RES_NAME;
0190     dev->io_resource.start = 0x800;
0191     dev->io_resource.end = 0x8FF;
0192     dev->io_resource.flags = IORESOURCE_IO | IORESOURCE_PCI_FIXED;
0193
0194     if (!ssb_device_is_enabled(sdev))
0195         ssb_device_enable(sdev, 0);
0196
0197     /* Setup BAR0. This is a 64k MMIO region. */
0198     base = ssb_admatch_base(ssb_read32(sdev, SSB_ADMATCH1));
0199     gige_pcicfg_write32(dev, PCI_BASE_ADDRESS_0, base);
0200     gige_pcicfg_write32(dev, PCI_BASE_ADDRESS_1, 0);
0201
0202     dev->mem_resource.name = SSB_GIGE_MEM_RES_NAME;
0203     dev->mem_resource.start = base;
0204     dev->mem_resource.end = base + 0x10000 - 1;
0205     dev->mem_resource.flags = IORESOURCE_MEM | IORESOURCE_PCI_FIXED;
0206
0207     /* Enable the memory region. */
0208     gige_pcicfg_write16(dev, PCI_COMMAND,
0209                 gige_pcicfg_read16(dev, PCI_COMMAND)
0210                 | PCI_COMMAND_MEMORY);
0211
0212     /* Write flushing is controlled by the Flush Status Control register.
0213      * We want to flush every register write with a timeout and we want
0214      * to disable the IRQ mask while flushing to avoid concurrency.
0215      * Note that automatic write flushing does _not_ work from
0216      * an IRQ handler. The driver must flush manually by reading a register.
0217      */
0218     gige_write32(dev, SSB_GIGE_SHIM_FLUSHSTAT, 0x00000068);
0219
0220     /* Check if we have an RGMII or GMII PHY-bus.
0221      * On RGMII do not bypass the DLLs */
0222     tmslow = ssb_read32(sdev, SSB_TMSLOW);
0223     tmshigh = ssb_read32(sdev, SSB_TMSHIGH);
0224     if (tmshigh & SSB_GIGE_TMSHIGH_RGMII) {
0225         tmslow &= ~SSB_GIGE_TMSLOW_TXBYPASS;
0226         tmslow &= ~SSB_GIGE_TMSLOW_RXBYPASS;
0227         dev->has_rgmii = 1;
0228     } else {
0229         tmslow |= SSB_GIGE_TMSLOW_TXBYPASS;
0230         tmslow |= SSB_GIGE_TMSLOW_RXBYPASS;
0231         dev->has_rgmii = 0;
0232     }
0233     tmslow |= SSB_GIGE_TMSLOW_DLLEN;
0234     ssb_write32(sdev, SSB_TMSLOW, tmslow);
0235
0236     ssb_set_drvdata(sdev, dev);
0237     register_pci_controller(&dev->pci_controller);
0238
0239     return 0;
0240 }
0241
0242 bool pdev_is_ssb_gige_core(struct pci_dev *pdev)
0243 {
0244     if (!pdev->resource[0].name)
0245         return false;
0246     return (strcmp(pdev->resource[0].name, SSB_GIGE_MEM_RES_NAME) == 0);
0247 }
0248 EXPORT_SYMBOL(pdev_is_ssb_gige_core);
0249
0250 int ssb_gige_pcibios_plat_dev_init(struct ssb_device *sdev,
0251                    struct pci_dev *pdev)
0252 {
0253     struct ssb_gige *dev = ssb_get_drvdata(sdev);
0254     struct resource *res;
0255
0256     if (pdev->bus->ops != &dev->pci_ops) {
0257         /* The PCI device is not on this SSB GigE bridge device. */
0258         return -ENODEV;
0259     }
0260
0261     /* Fixup the PCI resources. */
0262     res = &(pdev->resource[0]);
0263     res->flags = IORESOURCE_MEM | IORESOURCE_PCI_FIXED;
0264     res->name = dev->mem_resource.name;
0265     res->start = dev->mem_resource.start;
0266     res->end = dev->mem_resource.end;
0267
0268     /* Fixup interrupt lines. */
0269     pdev->irq = ssb_mips_irq(sdev) + 2;
0270     pci_write_config_byte(pdev, PCI_INTERRUPT_LINE, pdev->irq);
0271
0272     return 0;
0273 }
0274
0275 int ssb_gige_map_irq(struct ssb_device *sdev,
0276              const struct pci_dev *pdev)
0277 {
0278     struct ssb_gige *dev = ssb_get_drvdata(sdev);
0279
0280     if (pdev->bus->ops != &dev->pci_ops) {
0281         /* The PCI device is not on this SSB GigE bridge device. */
0282         return -ENODEV;
0283     }
0284
0285     return ssb_mips_irq(sdev) + 2;
0286 }
0287
0288 static struct ssb_driver ssb_gige_driver = {
0289     .name       = "BCM-GigE",
0290     .id_table   = ssb_gige_tbl,
0291     .probe      = ssb_gige_probe,
0292 };
0293
0294 int ssb_gige_init(void)
0295 {
0296     return ssb_driver_register(&ssb_gige_driver);
0297 }