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OSCL-LXR
 
 

     

0001 /*
0002  * Sonics Silicon Backplane
0003  * Broadcom ChipCommon core driver
0004  *
0005  * Copyright 2005, Broadcom Corporation
0006  * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
0007  * Copyright 2012, Hauke Mehrtens <hauke@hauke-m.de>
0008  *
0009  * Licensed under the GNU/GPL. See COPYING for details.
0010  */
0011 
0012 #include "ssb_private.h"
0013 
0014 #include <linux/ssb/ssb.h>
0015 #include <linux/ssb/ssb_regs.h>
0016 #include <linux/export.h>
0017 #include <linux/pci.h>
0018 #include <linux/bcm47xx_wdt.h>
0019 
0020 
0021 /* Clock sources */
0022 enum ssb_clksrc {
0023     /* PCI clock */
0024     SSB_CHIPCO_CLKSRC_PCI,
0025     /* Crystal slow clock oscillator */
0026     SSB_CHIPCO_CLKSRC_XTALOS,
0027     /* Low power oscillator */
0028     SSB_CHIPCO_CLKSRC_LOPWROS,
0029 };
0030 
0031 
0032 static inline u32 chipco_write32_masked(struct ssb_chipcommon *cc, u16 offset,
0033                     u32 mask, u32 value)
0034 {
0035     value &= mask;
0036     value |= chipco_read32(cc, offset) & ~mask;
0037     chipco_write32(cc, offset, value);
0038 
0039     return value;
0040 }
0041 
0042 void ssb_chipco_set_clockmode(struct ssb_chipcommon *cc,
0043                   enum ssb_clkmode mode)
0044 {
0045     struct ssb_device *ccdev = cc->dev;
0046     struct ssb_bus *bus;
0047     u32 tmp;
0048 
0049     if (!ccdev)
0050         return;
0051     bus = ccdev->bus;
0052 
0053     /* We support SLOW only on 6..9 */
0054     if (ccdev->id.revision >= 10 && mode == SSB_CLKMODE_SLOW)
0055         mode = SSB_CLKMODE_DYNAMIC;
0056 
0057     if (cc->capabilities & SSB_CHIPCO_CAP_PMU)
0058         return; /* PMU controls clockmode, separated function needed */
0059     WARN_ON(ccdev->id.revision >= 20);
0060 
0061     /* chipcommon cores prior to rev6 don't support dynamic clock control */
0062     if (ccdev->id.revision < 6)
0063         return;
0064 
0065     /* ChipCommon cores rev10+ need testing */
0066     if (ccdev->id.revision >= 10)
0067         return;
0068 
0069     if (!(cc->capabilities & SSB_CHIPCO_CAP_PCTL))
0070         return;
0071 
0072     switch (mode) {
0073     case SSB_CLKMODE_SLOW: /* For revs 6..9 only */
0074         tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
0075         tmp |= SSB_CHIPCO_SLOWCLKCTL_FSLOW;
0076         chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
0077         break;
0078     case SSB_CLKMODE_FAST:
0079         if (ccdev->id.revision < 10) {
0080             ssb_pci_xtal(bus, SSB_GPIO_XTAL, 1); /* Force crystal on */
0081             tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
0082             tmp &= ~SSB_CHIPCO_SLOWCLKCTL_FSLOW;
0083             tmp |= SSB_CHIPCO_SLOWCLKCTL_IPLL;
0084             chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
0085         } else {
0086             chipco_write32(cc, SSB_CHIPCO_SYSCLKCTL,
0087                 (chipco_read32(cc, SSB_CHIPCO_SYSCLKCTL) |
0088                  SSB_CHIPCO_SYSCLKCTL_FORCEHT));
0089             /* udelay(150); TODO: not available in early init */
0090         }
0091         break;
0092     case SSB_CLKMODE_DYNAMIC:
0093         if (ccdev->id.revision < 10) {
0094             tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
0095             tmp &= ~SSB_CHIPCO_SLOWCLKCTL_FSLOW;
0096             tmp &= ~SSB_CHIPCO_SLOWCLKCTL_IPLL;
0097             tmp &= ~SSB_CHIPCO_SLOWCLKCTL_ENXTAL;
0098             if ((tmp & SSB_CHIPCO_SLOWCLKCTL_SRC) !=
0099                 SSB_CHIPCO_SLOWCLKCTL_SRC_XTAL)
0100                 tmp |= SSB_CHIPCO_SLOWCLKCTL_ENXTAL;
0101             chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
0102 
0103             /* For dynamic control, we have to release our xtal_pu
0104              * "force on" */
0105             if (tmp & SSB_CHIPCO_SLOWCLKCTL_ENXTAL)
0106                 ssb_pci_xtal(bus, SSB_GPIO_XTAL, 0);
0107         } else {
0108             chipco_write32(cc, SSB_CHIPCO_SYSCLKCTL,
0109                 (chipco_read32(cc, SSB_CHIPCO_SYSCLKCTL) &
0110                  ~SSB_CHIPCO_SYSCLKCTL_FORCEHT));
0111         }
0112         break;
0113     default:
0114         WARN_ON(1);
0115     }
0116 }
0117 
0118 /* Get the Slow Clock Source */
0119 static enum ssb_clksrc chipco_pctl_get_slowclksrc(struct ssb_chipcommon *cc)
0120 {
0121     struct ssb_bus *bus = cc->dev->bus;
0122     u32 tmp;
0123 
0124     if (cc->dev->id.revision < 6) {
0125         if (bus->bustype == SSB_BUSTYPE_SSB ||
0126             bus->bustype == SSB_BUSTYPE_PCMCIA)
0127             return SSB_CHIPCO_CLKSRC_XTALOS;
0128         if (bus->bustype == SSB_BUSTYPE_PCI) {
0129             pci_read_config_dword(bus->host_pci, SSB_GPIO_OUT, &tmp);
0130             if (tmp & 0x10)
0131                 return SSB_CHIPCO_CLKSRC_PCI;
0132             return SSB_CHIPCO_CLKSRC_XTALOS;
0133         }
0134     }
0135     if (cc->dev->id.revision < 10) {
0136         tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
0137         tmp &= 0x7;
0138         if (tmp == 0)
0139             return SSB_CHIPCO_CLKSRC_LOPWROS;
0140         if (tmp == 1)
0141             return SSB_CHIPCO_CLKSRC_XTALOS;
0142         if (tmp == 2)
0143             return SSB_CHIPCO_CLKSRC_PCI;
0144     }
0145 
0146     return SSB_CHIPCO_CLKSRC_XTALOS;
0147 }
0148 
0149 /* Get maximum or minimum (depending on get_max flag) slowclock frequency. */
0150 static int chipco_pctl_clockfreqlimit(struct ssb_chipcommon *cc, int get_max)
0151 {
0152     int limit;
0153     enum ssb_clksrc clocksrc;
0154     int divisor = 1;
0155     u32 tmp;
0156 
0157     clocksrc = chipco_pctl_get_slowclksrc(cc);
0158     if (cc->dev->id.revision < 6) {
0159         switch (clocksrc) {
0160         case SSB_CHIPCO_CLKSRC_PCI:
0161             divisor = 64;
0162             break;
0163         case SSB_CHIPCO_CLKSRC_XTALOS:
0164             divisor = 32;
0165             break;
0166         default:
0167             WARN_ON(1);
0168         }
0169     } else if (cc->dev->id.revision < 10) {
0170         switch (clocksrc) {
0171         case SSB_CHIPCO_CLKSRC_LOPWROS:
0172             break;
0173         case SSB_CHIPCO_CLKSRC_XTALOS:
0174         case SSB_CHIPCO_CLKSRC_PCI:
0175             tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
0176             divisor = (tmp >> 16) + 1;
0177             divisor *= 4;
0178             break;
0179         }
0180     } else {
0181         tmp = chipco_read32(cc, SSB_CHIPCO_SYSCLKCTL);
0182         divisor = (tmp >> 16) + 1;
0183         divisor *= 4;
0184     }
0185 
0186     switch (clocksrc) {
0187     case SSB_CHIPCO_CLKSRC_LOPWROS:
0188         if (get_max)
0189             limit = 43000;
0190         else
0191             limit = 25000;
0192         break;
0193     case SSB_CHIPCO_CLKSRC_XTALOS:
0194         if (get_max)
0195             limit = 20200000;
0196         else
0197             limit = 19800000;
0198         break;
0199     case SSB_CHIPCO_CLKSRC_PCI:
0200         if (get_max)
0201             limit = 34000000;
0202         else
0203             limit = 25000000;
0204         break;
0205     }
0206     limit /= divisor;
0207 
0208     return limit;
0209 }
0210 
0211 static void chipco_powercontrol_init(struct ssb_chipcommon *cc)
0212 {
0213     struct ssb_bus *bus = cc->dev->bus;
0214 
0215     if (bus->chip_id == 0x4321) {
0216         if (bus->chip_rev == 0)
0217             chipco_write32(cc, SSB_CHIPCO_CHIPCTL, 0x3A4);
0218         else if (bus->chip_rev == 1)
0219             chipco_write32(cc, SSB_CHIPCO_CHIPCTL, 0xA4);
0220     }
0221 
0222     if (!(cc->capabilities & SSB_CHIPCO_CAP_PCTL))
0223         return;
0224 
0225     if (cc->dev->id.revision >= 10) {
0226         /* Set Idle Power clock rate to 1Mhz */
0227         chipco_write32(cc, SSB_CHIPCO_SYSCLKCTL,
0228                    (chipco_read32(cc, SSB_CHIPCO_SYSCLKCTL) &
0229                 0x0000FFFF) | 0x00040000);
0230     } else {
0231         int maxfreq;
0232 
0233         maxfreq = chipco_pctl_clockfreqlimit(cc, 1);
0234         chipco_write32(cc, SSB_CHIPCO_PLLONDELAY,
0235                    (maxfreq * 150 + 999999) / 1000000);
0236         chipco_write32(cc, SSB_CHIPCO_FREFSELDELAY,
0237                    (maxfreq * 15 + 999999) / 1000000);
0238     }
0239 }
0240 
0241 /* https://bcm-v4.sipsolutions.net/802.11/PmuFastPwrupDelay */
0242 static u16 pmu_fast_powerup_delay(struct ssb_chipcommon *cc)
0243 {
0244     struct ssb_bus *bus = cc->dev->bus;
0245 
0246     switch (bus->chip_id) {
0247     case 0x4312:
0248     case 0x4322:
0249     case 0x4328:
0250         return 7000;
0251     case 0x4325:
0252         /* TODO: */
0253     default:
0254         return 15000;
0255     }
0256 }
0257 
0258 /* https://bcm-v4.sipsolutions.net/802.11/ClkctlFastPwrupDelay */
0259 static void calc_fast_powerup_delay(struct ssb_chipcommon *cc)
0260 {
0261     struct ssb_bus *bus = cc->dev->bus;
0262     int minfreq;
0263     unsigned int tmp;
0264     u32 pll_on_delay;
0265 
0266     if (bus->bustype != SSB_BUSTYPE_PCI)
0267         return;
0268 
0269     if (cc->capabilities & SSB_CHIPCO_CAP_PMU) {
0270         cc->fast_pwrup_delay = pmu_fast_powerup_delay(cc);
0271         return;
0272     }
0273 
0274     if (!(cc->capabilities & SSB_CHIPCO_CAP_PCTL))
0275         return;
0276 
0277     minfreq = chipco_pctl_clockfreqlimit(cc, 0);
0278     pll_on_delay = chipco_read32(cc, SSB_CHIPCO_PLLONDELAY);
0279     tmp = (((pll_on_delay + 2) * 1000000) + (minfreq - 1)) / minfreq;
0280     WARN_ON(tmp & ~0xFFFF);
0281 
0282     cc->fast_pwrup_delay = tmp;
0283 }
0284 
0285 static u32 ssb_chipco_alp_clock(struct ssb_chipcommon *cc)
0286 {
0287     if (cc->capabilities & SSB_CHIPCO_CAP_PMU)
0288         return ssb_pmu_get_alp_clock(cc);
0289 
0290     return 20000000;
0291 }
0292 
0293 static u32 ssb_chipco_watchdog_get_max_timer(struct ssb_chipcommon *cc)
0294 {
0295     u32 nb;
0296 
0297     if (cc->capabilities & SSB_CHIPCO_CAP_PMU) {
0298         if (cc->dev->id.revision < 26)
0299             nb = 16;
0300         else
0301             nb = (cc->dev->id.revision >= 37) ? 32 : 24;
0302     } else {
0303         nb = 28;
0304     }
0305     if (nb == 32)
0306         return 0xffffffff;
0307     else
0308         return (1 << nb) - 1;
0309 }
0310 
0311 u32 ssb_chipco_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt, u32 ticks)
0312 {
0313     struct ssb_chipcommon *cc = bcm47xx_wdt_get_drvdata(wdt);
0314 
0315     if (cc->dev->bus->bustype != SSB_BUSTYPE_SSB)
0316         return 0;
0317 
0318     return ssb_chipco_watchdog_timer_set(cc, ticks);
0319 }
0320 
0321 u32 ssb_chipco_watchdog_timer_set_ms(struct bcm47xx_wdt *wdt, u32 ms)
0322 {
0323     struct ssb_chipcommon *cc = bcm47xx_wdt_get_drvdata(wdt);
0324     u32 ticks;
0325 
0326     if (cc->dev->bus->bustype != SSB_BUSTYPE_SSB)
0327         return 0;
0328 
0329     ticks = ssb_chipco_watchdog_timer_set(cc, cc->ticks_per_ms * ms);
0330     return ticks / cc->ticks_per_ms;
0331 }
0332 
0333 static int ssb_chipco_watchdog_ticks_per_ms(struct ssb_chipcommon *cc)
0334 {
0335     struct ssb_bus *bus = cc->dev->bus;
0336 
0337     if (cc->capabilities & SSB_CHIPCO_CAP_PMU) {
0338             /* based on 32KHz ILP clock */
0339             return 32;
0340     } else {
0341         if (cc->dev->id.revision < 18)
0342             return ssb_clockspeed(bus) / 1000;
0343         else
0344             return ssb_chipco_alp_clock(cc) / 1000;
0345     }
0346 }
0347 
0348 void ssb_chipcommon_init(struct ssb_chipcommon *cc)
0349 {
0350     if (!cc->dev)
0351         return; /* We don't have a ChipCommon */
0352 
0353     spin_lock_init(&cc->gpio_lock);
0354 
0355     if (cc->dev->id.revision >= 11)
0356         cc->status = chipco_read32(cc, SSB_CHIPCO_CHIPSTAT);
0357     dev_dbg(cc->dev->dev, "chipcommon status is 0x%x\n", cc->status);
0358 
0359     if (cc->dev->id.revision >= 20) {
0360         chipco_write32(cc, SSB_CHIPCO_GPIOPULLUP, 0);
0361         chipco_write32(cc, SSB_CHIPCO_GPIOPULLDOWN, 0);
0362     }
0363 
0364     ssb_pmu_init(cc);
0365     chipco_powercontrol_init(cc);
0366     ssb_chipco_set_clockmode(cc, SSB_CLKMODE_FAST);
0367     calc_fast_powerup_delay(cc);
0368 
0369     if (cc->dev->bus->bustype == SSB_BUSTYPE_SSB) {
0370         cc->ticks_per_ms = ssb_chipco_watchdog_ticks_per_ms(cc);
0371         cc->max_timer_ms = ssb_chipco_watchdog_get_max_timer(cc) / cc->ticks_per_ms;
0372     }
0373 }
0374 
0375 void ssb_chipco_suspend(struct ssb_chipcommon *cc)
0376 {
0377     if (!cc->dev)
0378         return;
0379     ssb_chipco_set_clockmode(cc, SSB_CLKMODE_SLOW);
0380 }
0381 
0382 void ssb_chipco_resume(struct ssb_chipcommon *cc)
0383 {
0384     if (!cc->dev)
0385         return;
0386     chipco_powercontrol_init(cc);
0387     ssb_chipco_set_clockmode(cc, SSB_CLKMODE_FAST);
0388 }
0389 
0390 /* Get the processor clock */
0391 void ssb_chipco_get_clockcpu(struct ssb_chipcommon *cc,
0392                              u32 *plltype, u32 *n, u32 *m)
0393 {
0394     *n = chipco_read32(cc, SSB_CHIPCO_CLOCK_N);
0395     *plltype = (cc->capabilities & SSB_CHIPCO_CAP_PLLT);
0396     switch (*plltype) {
0397     case SSB_PLLTYPE_2:
0398     case SSB_PLLTYPE_4:
0399     case SSB_PLLTYPE_6:
0400     case SSB_PLLTYPE_7:
0401         *m = chipco_read32(cc, SSB_CHIPCO_CLOCK_MIPS);
0402         break;
0403     case SSB_PLLTYPE_3:
0404         /* 5350 uses m2 to control mips */
0405         *m = chipco_read32(cc, SSB_CHIPCO_CLOCK_M2);
0406         break;
0407     default:
0408         *m = chipco_read32(cc, SSB_CHIPCO_CLOCK_SB);
0409         break;
0410     }
0411 }
0412 
0413 /* Get the bus clock */
0414 void ssb_chipco_get_clockcontrol(struct ssb_chipcommon *cc,
0415                  u32 *plltype, u32 *n, u32 *m)
0416 {
0417     *n = chipco_read32(cc, SSB_CHIPCO_CLOCK_N);
0418     *plltype = (cc->capabilities & SSB_CHIPCO_CAP_PLLT);
0419     switch (*plltype) {
0420     case SSB_PLLTYPE_6: /* 100/200 or 120/240 only */
0421         *m = chipco_read32(cc, SSB_CHIPCO_CLOCK_MIPS);
0422         break;
0423     case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */
0424         if (cc->dev->bus->chip_id != 0x5365) {
0425             *m = chipco_read32(cc, SSB_CHIPCO_CLOCK_M2);
0426             break;
0427         }
0428         fallthrough;
0429     default:
0430         *m = chipco_read32(cc, SSB_CHIPCO_CLOCK_SB);
0431     }
0432 }
0433 
0434 void ssb_chipco_timing_init(struct ssb_chipcommon *cc,
0435                 unsigned long ns)
0436 {
0437     struct ssb_device *dev = cc->dev;
0438     struct ssb_bus *bus = dev->bus;
0439     u32 tmp;
0440 
0441     /* set register for external IO to control LED. */
0442     chipco_write32(cc, SSB_CHIPCO_PROG_CFG, 0x11);
0443     tmp = DIV_ROUND_UP(10, ns) << SSB_PROG_WCNT_3_SHIFT;        /* Waitcount-3 = 10ns */
0444     tmp |= DIV_ROUND_UP(40, ns) << SSB_PROG_WCNT_1_SHIFT;   /* Waitcount-1 = 40ns */
0445     tmp |= DIV_ROUND_UP(240, ns);               /* Waitcount-0 = 240ns */
0446     chipco_write32(cc, SSB_CHIPCO_PROG_WAITCNT, tmp);   /* 0x01020a0c for a 100Mhz clock */
0447 
0448     /* Set timing for the flash */
0449     tmp = DIV_ROUND_UP(10, ns) << SSB_FLASH_WCNT_3_SHIFT;   /* Waitcount-3 = 10nS */
0450     tmp |= DIV_ROUND_UP(10, ns) << SSB_FLASH_WCNT_1_SHIFT;  /* Waitcount-1 = 10nS */
0451     tmp |= DIV_ROUND_UP(120, ns);               /* Waitcount-0 = 120nS */
0452     if ((bus->chip_id == 0x5365) ||
0453         (dev->id.revision < 9))
0454         chipco_write32(cc, SSB_CHIPCO_FLASH_WAITCNT, tmp);
0455     if ((bus->chip_id == 0x5365) ||
0456         (dev->id.revision < 9) ||
0457         ((bus->chip_id == 0x5350) && (bus->chip_rev == 0)))
0458         chipco_write32(cc, SSB_CHIPCO_PCMCIA_MEMWAIT, tmp);
0459 
0460     if (bus->chip_id == 0x5350) {
0461         /* Enable EXTIF */
0462         tmp = DIV_ROUND_UP(10, ns) << SSB_PROG_WCNT_3_SHIFT;      /* Waitcount-3 = 10ns */
0463         tmp |= DIV_ROUND_UP(20, ns) << SSB_PROG_WCNT_2_SHIFT;  /* Waitcount-2 = 20ns */
0464         tmp |= DIV_ROUND_UP(100, ns) << SSB_PROG_WCNT_1_SHIFT; /* Waitcount-1 = 100ns */
0465         tmp |= DIV_ROUND_UP(120, ns);             /* Waitcount-0 = 120ns */
0466         chipco_write32(cc, SSB_CHIPCO_PROG_WAITCNT, tmp); /* 0x01020a0c for a 100Mhz clock */
0467     }
0468 }
0469 
0470 /* Set chip watchdog reset timer to fire in 'ticks' backplane cycles */
0471 u32 ssb_chipco_watchdog_timer_set(struct ssb_chipcommon *cc, u32 ticks)
0472 {
0473     u32 maxt;
0474     enum ssb_clkmode clkmode;
0475 
0476     maxt = ssb_chipco_watchdog_get_max_timer(cc);
0477     if (cc->capabilities & SSB_CHIPCO_CAP_PMU) {
0478         if (ticks == 1)
0479             ticks = 2;
0480         else if (ticks > maxt)
0481             ticks = maxt;
0482         chipco_write32(cc, SSB_CHIPCO_PMU_WATCHDOG, ticks);
0483     } else {
0484         clkmode = ticks ? SSB_CLKMODE_FAST : SSB_CLKMODE_DYNAMIC;
0485         ssb_chipco_set_clockmode(cc, clkmode);
0486         if (ticks > maxt)
0487             ticks = maxt;
0488         /* instant NMI */
0489         chipco_write32(cc, SSB_CHIPCO_WATCHDOG, ticks);
0490     }
0491     return ticks;
0492 }
0493 
0494 void ssb_chipco_irq_mask(struct ssb_chipcommon *cc, u32 mask, u32 value)
0495 {
0496     chipco_write32_masked(cc, SSB_CHIPCO_IRQMASK, mask, value);
0497 }
0498 
0499 u32 ssb_chipco_irq_status(struct ssb_chipcommon *cc, u32 mask)
0500 {
0501     return chipco_read32(cc, SSB_CHIPCO_IRQSTAT) & mask;
0502 }
0503 
0504 u32 ssb_chipco_gpio_in(struct ssb_chipcommon *cc, u32 mask)
0505 {
0506     return chipco_read32(cc, SSB_CHIPCO_GPIOIN) & mask;
0507 }
0508 
0509 u32 ssb_chipco_gpio_out(struct ssb_chipcommon *cc, u32 mask, u32 value)
0510 {
0511     unsigned long flags;
0512     u32 res = 0;
0513 
0514     spin_lock_irqsave(&cc->gpio_lock, flags);
0515     res = chipco_write32_masked(cc, SSB_CHIPCO_GPIOOUT, mask, value);
0516     spin_unlock_irqrestore(&cc->gpio_lock, flags);
0517 
0518     return res;
0519 }
0520 
0521 u32 ssb_chipco_gpio_outen(struct ssb_chipcommon *cc, u32 mask, u32 value)
0522 {
0523     unsigned long flags;
0524     u32 res = 0;
0525 
0526     spin_lock_irqsave(&cc->gpio_lock, flags);
0527     res = chipco_write32_masked(cc, SSB_CHIPCO_GPIOOUTEN, mask, value);
0528     spin_unlock_irqrestore(&cc->gpio_lock, flags);
0529 
0530     return res;
0531 }
0532 
0533 u32 ssb_chipco_gpio_control(struct ssb_chipcommon *cc, u32 mask, u32 value)
0534 {
0535     unsigned long flags;
0536     u32 res = 0;
0537 
0538     spin_lock_irqsave(&cc->gpio_lock, flags);
0539     res = chipco_write32_masked(cc, SSB_CHIPCO_GPIOCTL, mask, value);
0540     spin_unlock_irqrestore(&cc->gpio_lock, flags);
0541 
0542     return res;
0543 }
0544 EXPORT_SYMBOL(ssb_chipco_gpio_control);
0545 
0546 u32 ssb_chipco_gpio_intmask(struct ssb_chipcommon *cc, u32 mask, u32 value)
0547 {
0548     unsigned long flags;
0549     u32 res = 0;
0550 
0551     spin_lock_irqsave(&cc->gpio_lock, flags);
0552     res = chipco_write32_masked(cc, SSB_CHIPCO_GPIOIRQ, mask, value);
0553     spin_unlock_irqrestore(&cc->gpio_lock, flags);
0554 
0555     return res;
0556 }
0557 
0558 u32 ssb_chipco_gpio_polarity(struct ssb_chipcommon *cc, u32 mask, u32 value)
0559 {
0560     unsigned long flags;
0561     u32 res = 0;
0562 
0563     spin_lock_irqsave(&cc->gpio_lock, flags);
0564     res = chipco_write32_masked(cc, SSB_CHIPCO_GPIOPOL, mask, value);
0565     spin_unlock_irqrestore(&cc->gpio_lock, flags);
0566 
0567     return res;
0568 }
0569 
0570 u32 ssb_chipco_gpio_pullup(struct ssb_chipcommon *cc, u32 mask, u32 value)
0571 {
0572     unsigned long flags;
0573     u32 res = 0;
0574 
0575     if (cc->dev->id.revision < 20)
0576         return 0xffffffff;
0577 
0578     spin_lock_irqsave(&cc->gpio_lock, flags);
0579     res = chipco_write32_masked(cc, SSB_CHIPCO_GPIOPULLUP, mask, value);
0580     spin_unlock_irqrestore(&cc->gpio_lock, flags);
0581 
0582     return res;
0583 }
0584 
0585 u32 ssb_chipco_gpio_pulldown(struct ssb_chipcommon *cc, u32 mask, u32 value)
0586 {
0587     unsigned long flags;
0588     u32 res = 0;
0589 
0590     if (cc->dev->id.revision < 20)
0591         return 0xffffffff;
0592 
0593     spin_lock_irqsave(&cc->gpio_lock, flags);
0594     res = chipco_write32_masked(cc, SSB_CHIPCO_GPIOPULLDOWN, mask, value);
0595     spin_unlock_irqrestore(&cc->gpio_lock, flags);
0596 
0597     return res;
0598 }
0599 
0600 #ifdef CONFIG_SSB_SERIAL
0601 int ssb_chipco_serial_init(struct ssb_chipcommon *cc,
0602                struct ssb_serial_port *ports)
0603 {
0604     struct ssb_bus *bus = cc->dev->bus;
0605     int nr_ports = 0;
0606     u32 plltype;
0607     unsigned int irq;
0608     u32 baud_base, div;
0609     u32 i, n;
0610     unsigned int ccrev = cc->dev->id.revision;
0611 
0612     plltype = (cc->capabilities & SSB_CHIPCO_CAP_PLLT);
0613     irq = ssb_mips_irq(cc->dev);
0614 
0615     if (plltype == SSB_PLLTYPE_1) {
0616         /* PLL clock */
0617         baud_base = ssb_calc_clock_rate(plltype,
0618                         chipco_read32(cc, SSB_CHIPCO_CLOCK_N),
0619                         chipco_read32(cc, SSB_CHIPCO_CLOCK_M2));
0620         div = 1;
0621     } else {
0622         if (ccrev == 20) {
0623             /* BCM5354 uses constant 25MHz clock */
0624             baud_base = 25000000;
0625             div = 48;
0626             /* Set the override bit so we don't divide it */
0627             chipco_write32(cc, SSB_CHIPCO_CORECTL,
0628                        chipco_read32(cc, SSB_CHIPCO_CORECTL)
0629                        | SSB_CHIPCO_CORECTL_UARTCLK0);
0630         } else if ((ccrev >= 11) && (ccrev != 15)) {
0631             baud_base = ssb_chipco_alp_clock(cc);
0632             div = 1;
0633             if (ccrev >= 21) {
0634                 /* Turn off UART clock before switching clocksource. */
0635                 chipco_write32(cc, SSB_CHIPCO_CORECTL,
0636                            chipco_read32(cc, SSB_CHIPCO_CORECTL)
0637                            & ~SSB_CHIPCO_CORECTL_UARTCLKEN);
0638             }
0639             /* Set the override bit so we don't divide it */
0640             chipco_write32(cc, SSB_CHIPCO_CORECTL,
0641                        chipco_read32(cc, SSB_CHIPCO_CORECTL)
0642                        | SSB_CHIPCO_CORECTL_UARTCLK0);
0643             if (ccrev >= 21) {
0644                 /* Re-enable the UART clock. */
0645                 chipco_write32(cc, SSB_CHIPCO_CORECTL,
0646                            chipco_read32(cc, SSB_CHIPCO_CORECTL)
0647                            | SSB_CHIPCO_CORECTL_UARTCLKEN);
0648             }
0649         } else if (ccrev >= 3) {
0650             /* Internal backplane clock */
0651             baud_base = ssb_clockspeed(bus);
0652             div = chipco_read32(cc, SSB_CHIPCO_CLKDIV)
0653                   & SSB_CHIPCO_CLKDIV_UART;
0654         } else {
0655             /* Fixed internal backplane clock */
0656             baud_base = 88000000;
0657             div = 48;
0658         }
0659 
0660         /* Clock source depends on strapping if UartClkOverride is unset */
0661         if ((ccrev > 0) &&
0662             !(chipco_read32(cc, SSB_CHIPCO_CORECTL) & SSB_CHIPCO_CORECTL_UARTCLK0)) {
0663             if ((cc->capabilities & SSB_CHIPCO_CAP_UARTCLK) ==
0664                 SSB_CHIPCO_CAP_UARTCLK_INT) {
0665                 /* Internal divided backplane clock */
0666                 baud_base /= div;
0667             } else {
0668                 /* Assume external clock of 1.8432 MHz */
0669                 baud_base = 1843200;
0670             }
0671         }
0672     }
0673 
0674     /* Determine the registers of the UARTs */
0675     n = (cc->capabilities & SSB_CHIPCO_CAP_NRUART);
0676     for (i = 0; i < n; i++) {
0677         void __iomem *cc_mmio;
0678         void __iomem *uart_regs;
0679 
0680         cc_mmio = cc->dev->bus->mmio + (cc->dev->core_index * SSB_CORE_SIZE);
0681         uart_regs = cc_mmio + SSB_CHIPCO_UART0_DATA;
0682         /* Offset changed at after rev 0 */
0683         if (ccrev == 0)
0684             uart_regs += (i * 8);
0685         else
0686             uart_regs += (i * 256);
0687 
0688         nr_ports++;
0689         ports[i].regs = uart_regs;
0690         ports[i].irq = irq;
0691         ports[i].baud_base = baud_base;
0692         ports[i].reg_shift = 0;
0693     }
0694 
0695     return nr_ports;
0696 }
0697 #endif /* CONFIG_SSB_SERIAL */
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