Back to home page

OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (c) 2012-2015, 2017, 2021, The Linux Foundation. All rights reserved.
0004  */
0005 #include <linux/bitmap.h>
0006 #include <linux/delay.h>
0007 #include <linux/err.h>
0008 #include <linux/interrupt.h>
0009 #include <linux/io.h>
0010 #include <linux/irqchip/chained_irq.h>
0011 #include <linux/irqdomain.h>
0012 #include <linux/irq.h>
0013 #include <linux/kernel.h>
0014 #include <linux/module.h>
0015 #include <linux/of.h>
0016 #include <linux/platform_device.h>
0017 #include <linux/slab.h>
0018 #include <linux/spmi.h>
0019 
0020 /* PMIC Arbiter configuration registers */
0021 #define PMIC_ARB_VERSION        0x0000
0022 #define PMIC_ARB_VERSION_V2_MIN     0x20010000
0023 #define PMIC_ARB_VERSION_V3_MIN     0x30000000
0024 #define PMIC_ARB_VERSION_V5_MIN     0x50000000
0025 #define PMIC_ARB_INT_EN         0x0004
0026 
0027 /* PMIC Arbiter channel registers offsets */
0028 #define PMIC_ARB_CMD            0x00
0029 #define PMIC_ARB_CONFIG         0x04
0030 #define PMIC_ARB_STATUS         0x08
0031 #define PMIC_ARB_WDATA0         0x10
0032 #define PMIC_ARB_WDATA1         0x14
0033 #define PMIC_ARB_RDATA0         0x18
0034 #define PMIC_ARB_RDATA1         0x1C
0035 
0036 /* Mapping Table */
0037 #define SPMI_MAPPING_TABLE_REG(N)   (0x0B00 + (4 * (N)))
0038 #define SPMI_MAPPING_BIT_INDEX(X)   (((X) >> 18) & 0xF)
0039 #define SPMI_MAPPING_BIT_IS_0_FLAG(X)   (((X) >> 17) & 0x1)
0040 #define SPMI_MAPPING_BIT_IS_0_RESULT(X) (((X) >> 9) & 0xFF)
0041 #define SPMI_MAPPING_BIT_IS_1_FLAG(X)   (((X) >> 8) & 0x1)
0042 #define SPMI_MAPPING_BIT_IS_1_RESULT(X) (((X) >> 0) & 0xFF)
0043 
0044 #define SPMI_MAPPING_TABLE_TREE_DEPTH   16  /* Maximum of 16-bits */
0045 #define PMIC_ARB_MAX_PPID       BIT(12) /* PPID is 12bit */
0046 #define PMIC_ARB_APID_VALID     BIT(15)
0047 #define PMIC_ARB_CHAN_IS_IRQ_OWNER(reg) ((reg) & BIT(24))
0048 #define INVALID_EE              0xFF
0049 
0050 /* Ownership Table */
0051 #define SPMI_OWNERSHIP_TABLE_REG(N) (0x0700 + (4 * (N)))
0052 #define SPMI_OWNERSHIP_PERIPH2OWNER(X)  ((X) & 0x7)
0053 
0054 /* Channel Status fields */
0055 enum pmic_arb_chnl_status {
0056     PMIC_ARB_STATUS_DONE    = BIT(0),
0057     PMIC_ARB_STATUS_FAILURE = BIT(1),
0058     PMIC_ARB_STATUS_DENIED  = BIT(2),
0059     PMIC_ARB_STATUS_DROPPED = BIT(3),
0060 };
0061 
0062 /* Command register fields */
0063 #define PMIC_ARB_CMD_MAX_BYTE_COUNT 8
0064 
0065 /* Command Opcodes */
0066 enum pmic_arb_cmd_op_code {
0067     PMIC_ARB_OP_EXT_WRITEL = 0,
0068     PMIC_ARB_OP_EXT_READL = 1,
0069     PMIC_ARB_OP_EXT_WRITE = 2,
0070     PMIC_ARB_OP_RESET = 3,
0071     PMIC_ARB_OP_SLEEP = 4,
0072     PMIC_ARB_OP_SHUTDOWN = 5,
0073     PMIC_ARB_OP_WAKEUP = 6,
0074     PMIC_ARB_OP_AUTHENTICATE = 7,
0075     PMIC_ARB_OP_MSTR_READ = 8,
0076     PMIC_ARB_OP_MSTR_WRITE = 9,
0077     PMIC_ARB_OP_EXT_READ = 13,
0078     PMIC_ARB_OP_WRITE = 14,
0079     PMIC_ARB_OP_READ = 15,
0080     PMIC_ARB_OP_ZERO_WRITE = 16,
0081 };
0082 
0083 /*
0084  * PMIC arbiter version 5 uses different register offsets for read/write vs
0085  * observer channels.
0086  */
0087 enum pmic_arb_channel {
0088     PMIC_ARB_CHANNEL_RW,
0089     PMIC_ARB_CHANNEL_OBS,
0090 };
0091 
0092 /* Maximum number of support PMIC peripherals */
0093 #define PMIC_ARB_MAX_PERIPHS        512
0094 #define PMIC_ARB_TIMEOUT_US     100
0095 #define PMIC_ARB_MAX_TRANS_BYTES    (8)
0096 
0097 #define PMIC_ARB_APID_MASK      0xFF
0098 #define PMIC_ARB_PPID_MASK      0xFFF
0099 
0100 /* interrupt enable bit */
0101 #define SPMI_PIC_ACC_ENABLE_BIT     BIT(0)
0102 
0103 #define spec_to_hwirq(slave_id, periph_id, irq_id, apid) \
0104     ((((slave_id) & 0xF)   << 28) | \
0105     (((periph_id) & 0xFF)  << 20) | \
0106     (((irq_id)    & 0x7)   << 16) | \
0107     (((apid)      & 0x1FF) << 0))
0108 
0109 #define hwirq_to_sid(hwirq)  (((hwirq) >> 28) & 0xF)
0110 #define hwirq_to_per(hwirq)  (((hwirq) >> 20) & 0xFF)
0111 #define hwirq_to_irq(hwirq)  (((hwirq) >> 16) & 0x7)
0112 #define hwirq_to_apid(hwirq) (((hwirq) >> 0)  & 0x1FF)
0113 
0114 struct pmic_arb_ver_ops;
0115 
0116 struct apid_data {
0117     u16     ppid;
0118     u8      write_ee;
0119     u8      irq_ee;
0120 };
0121 
0122 /**
0123  * spmi_pmic_arb - SPMI PMIC Arbiter object
0124  *
0125  * @rd_base:        on v1 "core", on v2 "observer" register base off DT.
0126  * @wr_base:        on v1 "core", on v2 "chnls"    register base off DT.
0127  * @intr:       address of the SPMI interrupt control registers.
0128  * @cnfg:       address of the PMIC Arbiter configuration registers.
0129  * @lock:       lock to synchronize accesses.
0130  * @channel:        execution environment channel to use for accesses.
0131  * @irq:        PMIC ARB interrupt.
0132  * @ee:         the current Execution Environment
0133  * @min_apid:       minimum APID (used for bounding IRQ search)
0134  * @max_apid:       maximum APID
0135  * @mapping_table:  in-memory copy of PPID -> APID mapping table.
0136  * @domain:     irq domain object for PMIC IRQ domain
0137  * @spmic:      SPMI controller object
0138  * @ver_ops:        version dependent operations.
0139  * @ppid_to_apid    in-memory copy of PPID -> APID mapping table.
0140  */
0141 struct spmi_pmic_arb {
0142     void __iomem        *rd_base;
0143     void __iomem        *wr_base;
0144     void __iomem        *intr;
0145     void __iomem        *cnfg;
0146     void __iomem        *core;
0147     resource_size_t     core_size;
0148     raw_spinlock_t      lock;
0149     u8          channel;
0150     int         irq;
0151     u8          ee;
0152     u16         min_apid;
0153     u16         max_apid;
0154     u32         *mapping_table;
0155     DECLARE_BITMAP(mapping_table_valid, PMIC_ARB_MAX_PERIPHS);
0156     struct irq_domain   *domain;
0157     struct spmi_controller  *spmic;
0158     const struct pmic_arb_ver_ops *ver_ops;
0159     u16         *ppid_to_apid;
0160     u16         last_apid;
0161     struct apid_data    apid_data[PMIC_ARB_MAX_PERIPHS];
0162 };
0163 
0164 /**
0165  * pmic_arb_ver: version dependent functionality.
0166  *
0167  * @ver_str:        version string.
0168  * @ppid_to_apid:   finds the apid for a given ppid.
0169  * @non_data_cmd:   on v1 issues an spmi non-data command.
0170  *          on v2 no HW support, returns -EOPNOTSUPP.
0171  * @offset:     on v1 offset of per-ee channel.
0172  *          on v2 offset of per-ee and per-ppid channel.
0173  * @fmt_cmd:        formats a GENI/SPMI command.
0174  * @owner_acc_status:   on v1 address of PMIC_ARB_SPMI_PIC_OWNERm_ACC_STATUSn
0175  *          on v2 address of SPMI_PIC_OWNERm_ACC_STATUSn.
0176  * @acc_enable:     on v1 address of PMIC_ARB_SPMI_PIC_ACC_ENABLEn
0177  *          on v2 address of SPMI_PIC_ACC_ENABLEn.
0178  * @irq_status:     on v1 address of PMIC_ARB_SPMI_PIC_IRQ_STATUSn
0179  *          on v2 address of SPMI_PIC_IRQ_STATUSn.
0180  * @irq_clear:      on v1 address of PMIC_ARB_SPMI_PIC_IRQ_CLEARn
0181  *          on v2 address of SPMI_PIC_IRQ_CLEARn.
0182  * @apid_map_offset:    offset of PMIC_ARB_REG_CHNLn
0183  */
0184 struct pmic_arb_ver_ops {
0185     const char *ver_str;
0186     int (*ppid_to_apid)(struct spmi_pmic_arb *pmic_arb, u16 ppid);
0187     /* spmi commands (read_cmd, write_cmd, cmd) functionality */
0188     int (*offset)(struct spmi_pmic_arb *pmic_arb, u8 sid, u16 addr,
0189             enum pmic_arb_channel ch_type);
0190     u32 (*fmt_cmd)(u8 opc, u8 sid, u16 addr, u8 bc);
0191     int (*non_data_cmd)(struct spmi_controller *ctrl, u8 opc, u8 sid);
0192     /* Interrupts controller functionality (offset of PIC registers) */
0193     void __iomem *(*owner_acc_status)(struct spmi_pmic_arb *pmic_arb, u8 m,
0194                       u16 n);
0195     void __iomem *(*acc_enable)(struct spmi_pmic_arb *pmic_arb, u16 n);
0196     void __iomem *(*irq_status)(struct spmi_pmic_arb *pmic_arb, u16 n);
0197     void __iomem *(*irq_clear)(struct spmi_pmic_arb *pmic_arb, u16 n);
0198     u32 (*apid_map_offset)(u16 n);
0199 };
0200 
0201 static inline void pmic_arb_base_write(struct spmi_pmic_arb *pmic_arb,
0202                        u32 offset, u32 val)
0203 {
0204     writel_relaxed(val, pmic_arb->wr_base + offset);
0205 }
0206 
0207 static inline void pmic_arb_set_rd_cmd(struct spmi_pmic_arb *pmic_arb,
0208                        u32 offset, u32 val)
0209 {
0210     writel_relaxed(val, pmic_arb->rd_base + offset);
0211 }
0212 
0213 /**
0214  * pmic_arb_read_data: reads pmic-arb's register and copy 1..4 bytes to buf
0215  * @bc:     byte count -1. range: 0..3
0216  * @reg:    register's address
0217  * @buf:    output parameter, length must be bc + 1
0218  */
0219 static void
0220 pmic_arb_read_data(struct spmi_pmic_arb *pmic_arb, u8 *buf, u32 reg, u8 bc)
0221 {
0222     u32 data = __raw_readl(pmic_arb->rd_base + reg);
0223 
0224     memcpy(buf, &data, (bc & 3) + 1);
0225 }
0226 
0227 /**
0228  * pmic_arb_write_data: write 1..4 bytes from buf to pmic-arb's register
0229  * @bc:     byte-count -1. range: 0..3.
0230  * @reg:    register's address.
0231  * @buf:    buffer to write. length must be bc + 1.
0232  */
0233 static void pmic_arb_write_data(struct spmi_pmic_arb *pmic_arb, const u8 *buf,
0234                 u32 reg, u8 bc)
0235 {
0236     u32 data = 0;
0237 
0238     memcpy(&data, buf, (bc & 3) + 1);
0239     __raw_writel(data, pmic_arb->wr_base + reg);
0240 }
0241 
0242 static int pmic_arb_wait_for_done(struct spmi_controller *ctrl,
0243                   void __iomem *base, u8 sid, u16 addr,
0244                   enum pmic_arb_channel ch_type)
0245 {
0246     struct spmi_pmic_arb *pmic_arb = spmi_controller_get_drvdata(ctrl);
0247     u32 status = 0;
0248     u32 timeout = PMIC_ARB_TIMEOUT_US;
0249     u32 offset;
0250     int rc;
0251 
0252     rc = pmic_arb->ver_ops->offset(pmic_arb, sid, addr, ch_type);
0253     if (rc < 0)
0254         return rc;
0255 
0256     offset = rc;
0257     offset += PMIC_ARB_STATUS;
0258 
0259     while (timeout--) {
0260         status = readl_relaxed(base + offset);
0261 
0262         if (status & PMIC_ARB_STATUS_DONE) {
0263             if (status & PMIC_ARB_STATUS_DENIED) {
0264                 dev_err(&ctrl->dev, "%s: %#x %#x: transaction denied (%#x)\n",
0265                     __func__, sid, addr, status);
0266                 return -EPERM;
0267             }
0268 
0269             if (status & PMIC_ARB_STATUS_FAILURE) {
0270                 dev_err(&ctrl->dev, "%s: %#x %#x: transaction failed (%#x)\n",
0271                     __func__, sid, addr, status);
0272                 WARN_ON(1);
0273                 return -EIO;
0274             }
0275 
0276             if (status & PMIC_ARB_STATUS_DROPPED) {
0277                 dev_err(&ctrl->dev, "%s: %#x %#x: transaction dropped (%#x)\n",
0278                     __func__, sid, addr, status);
0279                 return -EIO;
0280             }
0281 
0282             return 0;
0283         }
0284         udelay(1);
0285     }
0286 
0287     dev_err(&ctrl->dev, "%s: %#x %#x: timeout, status %#x\n",
0288         __func__, sid, addr, status);
0289     return -ETIMEDOUT;
0290 }
0291 
0292 static int
0293 pmic_arb_non_data_cmd_v1(struct spmi_controller *ctrl, u8 opc, u8 sid)
0294 {
0295     struct spmi_pmic_arb *pmic_arb = spmi_controller_get_drvdata(ctrl);
0296     unsigned long flags;
0297     u32 cmd;
0298     int rc;
0299     u32 offset;
0300 
0301     rc = pmic_arb->ver_ops->offset(pmic_arb, sid, 0, PMIC_ARB_CHANNEL_RW);
0302     if (rc < 0)
0303         return rc;
0304 
0305     offset = rc;
0306     cmd = ((opc | 0x40) << 27) | ((sid & 0xf) << 20);
0307 
0308     raw_spin_lock_irqsave(&pmic_arb->lock, flags);
0309     pmic_arb_base_write(pmic_arb, offset + PMIC_ARB_CMD, cmd);
0310     rc = pmic_arb_wait_for_done(ctrl, pmic_arb->wr_base, sid, 0,
0311                     PMIC_ARB_CHANNEL_RW);
0312     raw_spin_unlock_irqrestore(&pmic_arb->lock, flags);
0313 
0314     return rc;
0315 }
0316 
0317 static int
0318 pmic_arb_non_data_cmd_v2(struct spmi_controller *ctrl, u8 opc, u8 sid)
0319 {
0320     return -EOPNOTSUPP;
0321 }
0322 
0323 /* Non-data command */
0324 static int pmic_arb_cmd(struct spmi_controller *ctrl, u8 opc, u8 sid)
0325 {
0326     struct spmi_pmic_arb *pmic_arb = spmi_controller_get_drvdata(ctrl);
0327 
0328     dev_dbg(&ctrl->dev, "cmd op:0x%x sid:%d\n", opc, sid);
0329 
0330     /* Check for valid non-data command */
0331     if (opc < SPMI_CMD_RESET || opc > SPMI_CMD_WAKEUP)
0332         return -EINVAL;
0333 
0334     return pmic_arb->ver_ops->non_data_cmd(ctrl, opc, sid);
0335 }
0336 
0337 static int pmic_arb_fmt_read_cmd(struct spmi_pmic_arb *pmic_arb, u8 opc, u8 sid,
0338                  u16 addr, size_t len, u32 *cmd, u32 *offset)
0339 {
0340     u8 bc = len - 1;
0341     int rc;
0342 
0343     rc = pmic_arb->ver_ops->offset(pmic_arb, sid, addr,
0344                        PMIC_ARB_CHANNEL_OBS);
0345     if (rc < 0)
0346         return rc;
0347 
0348     *offset = rc;
0349     if (bc >= PMIC_ARB_MAX_TRANS_BYTES) {
0350         dev_err(&pmic_arb->spmic->dev, "pmic-arb supports 1..%d bytes per trans, but:%zu requested",
0351             PMIC_ARB_MAX_TRANS_BYTES, len);
0352         return  -EINVAL;
0353     }
0354 
0355     /* Check the opcode */
0356     if (opc >= 0x60 && opc <= 0x7F)
0357         opc = PMIC_ARB_OP_READ;
0358     else if (opc >= 0x20 && opc <= 0x2F)
0359         opc = PMIC_ARB_OP_EXT_READ;
0360     else if (opc >= 0x38 && opc <= 0x3F)
0361         opc = PMIC_ARB_OP_EXT_READL;
0362     else
0363         return -EINVAL;
0364 
0365     *cmd = pmic_arb->ver_ops->fmt_cmd(opc, sid, addr, bc);
0366 
0367     return 0;
0368 }
0369 
0370 static int pmic_arb_read_cmd_unlocked(struct spmi_controller *ctrl, u32 cmd,
0371                       u32 offset, u8 sid, u16 addr, u8 *buf,
0372                       size_t len)
0373 {
0374     struct spmi_pmic_arb *pmic_arb = spmi_controller_get_drvdata(ctrl);
0375     u8 bc = len - 1;
0376     int rc;
0377 
0378     pmic_arb_set_rd_cmd(pmic_arb, offset + PMIC_ARB_CMD, cmd);
0379     rc = pmic_arb_wait_for_done(ctrl, pmic_arb->rd_base, sid, addr,
0380                     PMIC_ARB_CHANNEL_OBS);
0381     if (rc)
0382         return rc;
0383 
0384     pmic_arb_read_data(pmic_arb, buf, offset + PMIC_ARB_RDATA0,
0385              min_t(u8, bc, 3));
0386 
0387     if (bc > 3)
0388         pmic_arb_read_data(pmic_arb, buf + 4, offset + PMIC_ARB_RDATA1,
0389                     bc - 4);
0390     return 0;
0391 }
0392 
0393 static int pmic_arb_read_cmd(struct spmi_controller *ctrl, u8 opc, u8 sid,
0394                  u16 addr, u8 *buf, size_t len)
0395 {
0396     struct spmi_pmic_arb *pmic_arb = spmi_controller_get_drvdata(ctrl);
0397     unsigned long flags;
0398     u32 cmd, offset;
0399     int rc;
0400 
0401     rc = pmic_arb_fmt_read_cmd(pmic_arb, opc, sid, addr, len, &cmd,
0402                    &offset);
0403     if (rc)
0404         return rc;
0405 
0406     raw_spin_lock_irqsave(&pmic_arb->lock, flags);
0407     rc = pmic_arb_read_cmd_unlocked(ctrl, cmd, offset, sid, addr, buf, len);
0408     raw_spin_unlock_irqrestore(&pmic_arb->lock, flags);
0409 
0410     return rc;
0411 }
0412 
0413 static int pmic_arb_fmt_write_cmd(struct spmi_pmic_arb *pmic_arb, u8 opc,
0414                   u8 sid, u16 addr, size_t len, u32 *cmd,
0415                   u32 *offset)
0416 {
0417     u8 bc = len - 1;
0418     int rc;
0419 
0420     rc = pmic_arb->ver_ops->offset(pmic_arb, sid, addr,
0421                     PMIC_ARB_CHANNEL_RW);
0422     if (rc < 0)
0423         return rc;
0424 
0425     *offset = rc;
0426     if (bc >= PMIC_ARB_MAX_TRANS_BYTES) {
0427         dev_err(&pmic_arb->spmic->dev, "pmic-arb supports 1..%d bytes per trans, but:%zu requested",
0428             PMIC_ARB_MAX_TRANS_BYTES, len);
0429         return  -EINVAL;
0430     }
0431 
0432     /* Check the opcode */
0433     if (opc >= 0x40 && opc <= 0x5F)
0434         opc = PMIC_ARB_OP_WRITE;
0435     else if (opc <= 0x0F)
0436         opc = PMIC_ARB_OP_EXT_WRITE;
0437     else if (opc >= 0x30 && opc <= 0x37)
0438         opc = PMIC_ARB_OP_EXT_WRITEL;
0439     else if (opc >= 0x80)
0440         opc = PMIC_ARB_OP_ZERO_WRITE;
0441     else
0442         return -EINVAL;
0443 
0444     *cmd = pmic_arb->ver_ops->fmt_cmd(opc, sid, addr, bc);
0445 
0446     return 0;
0447 }
0448 
0449 static int pmic_arb_write_cmd_unlocked(struct spmi_controller *ctrl, u32 cmd,
0450                       u32 offset, u8 sid, u16 addr,
0451                       const u8 *buf, size_t len)
0452 {
0453     struct spmi_pmic_arb *pmic_arb = spmi_controller_get_drvdata(ctrl);
0454     u8 bc = len - 1;
0455 
0456     /* Write data to FIFOs */
0457     pmic_arb_write_data(pmic_arb, buf, offset + PMIC_ARB_WDATA0,
0458                 min_t(u8, bc, 3));
0459     if (bc > 3)
0460         pmic_arb_write_data(pmic_arb, buf + 4, offset + PMIC_ARB_WDATA1,
0461                     bc - 4);
0462 
0463     /* Start the transaction */
0464     pmic_arb_base_write(pmic_arb, offset + PMIC_ARB_CMD, cmd);
0465     return pmic_arb_wait_for_done(ctrl, pmic_arb->wr_base, sid, addr,
0466                       PMIC_ARB_CHANNEL_RW);
0467 }
0468 
0469 static int pmic_arb_write_cmd(struct spmi_controller *ctrl, u8 opc, u8 sid,
0470                   u16 addr, const u8 *buf, size_t len)
0471 {
0472     struct spmi_pmic_arb *pmic_arb = spmi_controller_get_drvdata(ctrl);
0473     unsigned long flags;
0474     u32 cmd, offset;
0475     int rc;
0476 
0477     rc = pmic_arb_fmt_write_cmd(pmic_arb, opc, sid, addr, len, &cmd,
0478                     &offset);
0479     if (rc)
0480         return rc;
0481 
0482     raw_spin_lock_irqsave(&pmic_arb->lock, flags);
0483     rc = pmic_arb_write_cmd_unlocked(ctrl, cmd, offset, sid, addr, buf,
0484                      len);
0485     raw_spin_unlock_irqrestore(&pmic_arb->lock, flags);
0486 
0487     return rc;
0488 }
0489 
0490 static int pmic_arb_masked_write(struct spmi_controller *ctrl, u8 sid, u16 addr,
0491                  const u8 *buf, const u8 *mask, size_t len)
0492 {
0493     struct spmi_pmic_arb *pmic_arb = spmi_controller_get_drvdata(ctrl);
0494     u32 read_cmd, read_offset, write_cmd, write_offset;
0495     u8 temp[PMIC_ARB_MAX_TRANS_BYTES];
0496     unsigned long flags;
0497     int rc, i;
0498 
0499     rc = pmic_arb_fmt_read_cmd(pmic_arb, SPMI_CMD_EXT_READL, sid, addr, len,
0500                    &read_cmd, &read_offset);
0501     if (rc)
0502         return rc;
0503 
0504     rc = pmic_arb_fmt_write_cmd(pmic_arb, SPMI_CMD_EXT_WRITEL, sid, addr,
0505                     len, &write_cmd, &write_offset);
0506     if (rc)
0507         return rc;
0508 
0509     raw_spin_lock_irqsave(&pmic_arb->lock, flags);
0510     rc = pmic_arb_read_cmd_unlocked(ctrl, read_cmd, read_offset, sid, addr,
0511                     temp, len);
0512     if (rc)
0513         goto done;
0514 
0515     for (i = 0; i < len; i++)
0516         temp[i] = (temp[i] & ~mask[i]) | (buf[i] & mask[i]);
0517 
0518     rc = pmic_arb_write_cmd_unlocked(ctrl, write_cmd, write_offset, sid,
0519                      addr, temp, len);
0520 done:
0521     raw_spin_unlock_irqrestore(&pmic_arb->lock, flags);
0522 
0523     return rc;
0524 }
0525 
0526 enum qpnpint_regs {
0527     QPNPINT_REG_RT_STS      = 0x10,
0528     QPNPINT_REG_SET_TYPE        = 0x11,
0529     QPNPINT_REG_POLARITY_HIGH   = 0x12,
0530     QPNPINT_REG_POLARITY_LOW    = 0x13,
0531     QPNPINT_REG_LATCHED_CLR     = 0x14,
0532     QPNPINT_REG_EN_SET      = 0x15,
0533     QPNPINT_REG_EN_CLR      = 0x16,
0534     QPNPINT_REG_LATCHED_STS     = 0x18,
0535 };
0536 
0537 struct spmi_pmic_arb_qpnpint_type {
0538     u8 type; /* 1 -> edge */
0539     u8 polarity_high;
0540     u8 polarity_low;
0541 } __packed;
0542 
0543 /* Simplified accessor functions for irqchip callbacks */
0544 static void qpnpint_spmi_write(struct irq_data *d, u8 reg, void *buf,
0545                    size_t len)
0546 {
0547     struct spmi_pmic_arb *pmic_arb = irq_data_get_irq_chip_data(d);
0548     u8 sid = hwirq_to_sid(d->hwirq);
0549     u8 per = hwirq_to_per(d->hwirq);
0550 
0551     if (pmic_arb_write_cmd(pmic_arb->spmic, SPMI_CMD_EXT_WRITEL, sid,
0552                    (per << 8) + reg, buf, len))
0553         dev_err_ratelimited(&pmic_arb->spmic->dev, "failed irqchip transaction on %x\n",
0554                     d->irq);
0555 }
0556 
0557 static void qpnpint_spmi_read(struct irq_data *d, u8 reg, void *buf, size_t len)
0558 {
0559     struct spmi_pmic_arb *pmic_arb = irq_data_get_irq_chip_data(d);
0560     u8 sid = hwirq_to_sid(d->hwirq);
0561     u8 per = hwirq_to_per(d->hwirq);
0562 
0563     if (pmic_arb_read_cmd(pmic_arb->spmic, SPMI_CMD_EXT_READL, sid,
0564                   (per << 8) + reg, buf, len))
0565         dev_err_ratelimited(&pmic_arb->spmic->dev, "failed irqchip transaction on %x\n",
0566                     d->irq);
0567 }
0568 
0569 static int qpnpint_spmi_masked_write(struct irq_data *d, u8 reg,
0570                      const void *buf, const void *mask,
0571                      size_t len)
0572 {
0573     struct spmi_pmic_arb *pmic_arb = irq_data_get_irq_chip_data(d);
0574     u8 sid = hwirq_to_sid(d->hwirq);
0575     u8 per = hwirq_to_per(d->hwirq);
0576     int rc;
0577 
0578     rc = pmic_arb_masked_write(pmic_arb->spmic, sid, (per << 8) + reg, buf,
0579                    mask, len);
0580     if (rc)
0581         dev_err_ratelimited(&pmic_arb->spmic->dev, "failed irqchip transaction on %x rc=%d\n",
0582                     d->irq, rc);
0583     return rc;
0584 }
0585 
0586 static void cleanup_irq(struct spmi_pmic_arb *pmic_arb, u16 apid, int id)
0587 {
0588     u16 ppid = pmic_arb->apid_data[apid].ppid;
0589     u8 sid = ppid >> 8;
0590     u8 per = ppid & 0xFF;
0591     u8 irq_mask = BIT(id);
0592 
0593     writel_relaxed(irq_mask, pmic_arb->ver_ops->irq_clear(pmic_arb, apid));
0594 
0595     if (pmic_arb_write_cmd(pmic_arb->spmic, SPMI_CMD_EXT_WRITEL, sid,
0596             (per << 8) + QPNPINT_REG_LATCHED_CLR, &irq_mask, 1))
0597         dev_err_ratelimited(&pmic_arb->spmic->dev, "failed to ack irq_mask = 0x%x for ppid = %x\n",
0598                 irq_mask, ppid);
0599 
0600     if (pmic_arb_write_cmd(pmic_arb->spmic, SPMI_CMD_EXT_WRITEL, sid,
0601                    (per << 8) + QPNPINT_REG_EN_CLR, &irq_mask, 1))
0602         dev_err_ratelimited(&pmic_arb->spmic->dev, "failed to ack irq_mask = 0x%x for ppid = %x\n",
0603                 irq_mask, ppid);
0604 }
0605 
0606 static void periph_interrupt(struct spmi_pmic_arb *pmic_arb, u16 apid)
0607 {
0608     unsigned int irq;
0609     u32 status, id;
0610     u8 sid = (pmic_arb->apid_data[apid].ppid >> 8) & 0xF;
0611     u8 per = pmic_arb->apid_data[apid].ppid & 0xFF;
0612 
0613     status = readl_relaxed(pmic_arb->ver_ops->irq_status(pmic_arb, apid));
0614     while (status) {
0615         id = ffs(status) - 1;
0616         status &= ~BIT(id);
0617         irq = irq_find_mapping(pmic_arb->domain,
0618                     spec_to_hwirq(sid, per, id, apid));
0619         if (irq == 0) {
0620             cleanup_irq(pmic_arb, apid, id);
0621             continue;
0622         }
0623         generic_handle_irq(irq);
0624     }
0625 }
0626 
0627 static void pmic_arb_chained_irq(struct irq_desc *desc)
0628 {
0629     struct spmi_pmic_arb *pmic_arb = irq_desc_get_handler_data(desc);
0630     const struct pmic_arb_ver_ops *ver_ops = pmic_arb->ver_ops;
0631     struct irq_chip *chip = irq_desc_get_chip(desc);
0632     int first = pmic_arb->min_apid >> 5;
0633     int last = pmic_arb->max_apid >> 5;
0634     u8 ee = pmic_arb->ee;
0635     u32 status, enable;
0636     int i, id, apid;
0637 
0638     chained_irq_enter(chip, desc);
0639 
0640     for (i = first; i <= last; ++i) {
0641         status = readl_relaxed(
0642                 ver_ops->owner_acc_status(pmic_arb, ee, i));
0643         while (status) {
0644             id = ffs(status) - 1;
0645             status &= ~BIT(id);
0646             apid = id + i * 32;
0647             enable = readl_relaxed(
0648                     ver_ops->acc_enable(pmic_arb, apid));
0649             if (enable & SPMI_PIC_ACC_ENABLE_BIT)
0650                 periph_interrupt(pmic_arb, apid);
0651         }
0652     }
0653 
0654     chained_irq_exit(chip, desc);
0655 }
0656 
0657 static void qpnpint_irq_ack(struct irq_data *d)
0658 {
0659     struct spmi_pmic_arb *pmic_arb = irq_data_get_irq_chip_data(d);
0660     u8 irq = hwirq_to_irq(d->hwirq);
0661     u16 apid = hwirq_to_apid(d->hwirq);
0662     u8 data;
0663 
0664     writel_relaxed(BIT(irq), pmic_arb->ver_ops->irq_clear(pmic_arb, apid));
0665 
0666     data = BIT(irq);
0667     qpnpint_spmi_write(d, QPNPINT_REG_LATCHED_CLR, &data, 1);
0668 }
0669 
0670 static void qpnpint_irq_mask(struct irq_data *d)
0671 {
0672     u8 irq = hwirq_to_irq(d->hwirq);
0673     u8 data = BIT(irq);
0674 
0675     qpnpint_spmi_write(d, QPNPINT_REG_EN_CLR, &data, 1);
0676 }
0677 
0678 static void qpnpint_irq_unmask(struct irq_data *d)
0679 {
0680     struct spmi_pmic_arb *pmic_arb = irq_data_get_irq_chip_data(d);
0681     const struct pmic_arb_ver_ops *ver_ops = pmic_arb->ver_ops;
0682     u8 irq = hwirq_to_irq(d->hwirq);
0683     u16 apid = hwirq_to_apid(d->hwirq);
0684     u8 buf[2];
0685 
0686     writel_relaxed(SPMI_PIC_ACC_ENABLE_BIT,
0687             ver_ops->acc_enable(pmic_arb, apid));
0688 
0689     qpnpint_spmi_read(d, QPNPINT_REG_EN_SET, &buf[0], 1);
0690     if (!(buf[0] & BIT(irq))) {
0691         /*
0692          * Since the interrupt is currently disabled, write to both the
0693          * LATCHED_CLR and EN_SET registers so that a spurious interrupt
0694          * cannot be triggered when the interrupt is enabled
0695          */
0696         buf[0] = BIT(irq);
0697         buf[1] = BIT(irq);
0698         qpnpint_spmi_write(d, QPNPINT_REG_LATCHED_CLR, &buf, 2);
0699     }
0700 }
0701 
0702 static int qpnpint_irq_set_type(struct irq_data *d, unsigned int flow_type)
0703 {
0704     struct spmi_pmic_arb_qpnpint_type type = {0};
0705     struct spmi_pmic_arb_qpnpint_type mask;
0706     irq_flow_handler_t flow_handler;
0707     u8 irq_bit = BIT(hwirq_to_irq(d->hwirq));
0708     int rc;
0709 
0710     if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)) {
0711         type.type = irq_bit;
0712         if (flow_type & IRQF_TRIGGER_RISING)
0713             type.polarity_high = irq_bit;
0714         if (flow_type & IRQF_TRIGGER_FALLING)
0715             type.polarity_low = irq_bit;
0716 
0717         flow_handler = handle_edge_irq;
0718     } else {
0719         if ((flow_type & (IRQF_TRIGGER_HIGH)) &&
0720             (flow_type & (IRQF_TRIGGER_LOW)))
0721             return -EINVAL;
0722 
0723         if (flow_type & IRQF_TRIGGER_HIGH)
0724             type.polarity_high = irq_bit;
0725         else
0726             type.polarity_low = irq_bit;
0727 
0728         flow_handler = handle_level_irq;
0729     }
0730 
0731     mask.type = irq_bit;
0732     mask.polarity_high = irq_bit;
0733     mask.polarity_low = irq_bit;
0734 
0735     rc = qpnpint_spmi_masked_write(d, QPNPINT_REG_SET_TYPE, &type, &mask,
0736                        sizeof(type));
0737     irq_set_handler_locked(d, flow_handler);
0738 
0739     return rc;
0740 }
0741 
0742 static int qpnpint_irq_set_wake(struct irq_data *d, unsigned int on)
0743 {
0744     struct spmi_pmic_arb *pmic_arb = irq_data_get_irq_chip_data(d);
0745 
0746     return irq_set_irq_wake(pmic_arb->irq, on);
0747 }
0748 
0749 static int qpnpint_get_irqchip_state(struct irq_data *d,
0750                      enum irqchip_irq_state which,
0751                      bool *state)
0752 {
0753     u8 irq = hwirq_to_irq(d->hwirq);
0754     u8 status = 0;
0755 
0756     if (which != IRQCHIP_STATE_LINE_LEVEL)
0757         return -EINVAL;
0758 
0759     qpnpint_spmi_read(d, QPNPINT_REG_RT_STS, &status, 1);
0760     *state = !!(status & BIT(irq));
0761 
0762     return 0;
0763 }
0764 
0765 static int qpnpint_irq_domain_activate(struct irq_domain *domain,
0766                        struct irq_data *d, bool reserve)
0767 {
0768     struct spmi_pmic_arb *pmic_arb = irq_data_get_irq_chip_data(d);
0769     u16 periph = hwirq_to_per(d->hwirq);
0770     u16 apid = hwirq_to_apid(d->hwirq);
0771     u16 sid = hwirq_to_sid(d->hwirq);
0772     u16 irq = hwirq_to_irq(d->hwirq);
0773 
0774     if (pmic_arb->apid_data[apid].irq_ee != pmic_arb->ee) {
0775         dev_err(&pmic_arb->spmic->dev, "failed to xlate sid = %#x, periph = %#x, irq = %u: ee=%u but owner=%u\n",
0776             sid, periph, irq, pmic_arb->ee,
0777             pmic_arb->apid_data[apid].irq_ee);
0778         return -ENODEV;
0779     }
0780 
0781     return 0;
0782 }
0783 
0784 static struct irq_chip pmic_arb_irqchip = {
0785     .name       = "pmic_arb",
0786     .irq_ack    = qpnpint_irq_ack,
0787     .irq_mask   = qpnpint_irq_mask,
0788     .irq_unmask = qpnpint_irq_unmask,
0789     .irq_set_type   = qpnpint_irq_set_type,
0790     .irq_set_wake   = qpnpint_irq_set_wake,
0791     .irq_get_irqchip_state  = qpnpint_get_irqchip_state,
0792     .flags      = IRQCHIP_MASK_ON_SUSPEND,
0793 };
0794 
0795 static int qpnpint_irq_domain_translate(struct irq_domain *d,
0796                     struct irq_fwspec *fwspec,
0797                     unsigned long *out_hwirq,
0798                     unsigned int *out_type)
0799 {
0800     struct spmi_pmic_arb *pmic_arb = d->host_data;
0801     u32 *intspec = fwspec->param;
0802     u16 apid, ppid;
0803     int rc;
0804 
0805     dev_dbg(&pmic_arb->spmic->dev, "intspec[0] 0x%1x intspec[1] 0x%02x intspec[2] 0x%02x\n",
0806         intspec[0], intspec[1], intspec[2]);
0807 
0808     if (irq_domain_get_of_node(d) != pmic_arb->spmic->dev.of_node)
0809         return -EINVAL;
0810     if (fwspec->param_count != 4)
0811         return -EINVAL;
0812     if (intspec[0] > 0xF || intspec[1] > 0xFF || intspec[2] > 0x7)
0813         return -EINVAL;
0814 
0815     ppid = intspec[0] << 8 | intspec[1];
0816     rc = pmic_arb->ver_ops->ppid_to_apid(pmic_arb, ppid);
0817     if (rc < 0) {
0818         dev_err(&pmic_arb->spmic->dev, "failed to xlate sid = %#x, periph = %#x, irq = %u rc = %d\n",
0819         intspec[0], intspec[1], intspec[2], rc);
0820         return rc;
0821     }
0822 
0823     apid = rc;
0824     /* Keep track of {max,min}_apid for bounding search during interrupt */
0825     if (apid > pmic_arb->max_apid)
0826         pmic_arb->max_apid = apid;
0827     if (apid < pmic_arb->min_apid)
0828         pmic_arb->min_apid = apid;
0829 
0830     *out_hwirq = spec_to_hwirq(intspec[0], intspec[1], intspec[2], apid);
0831     *out_type  = intspec[3] & IRQ_TYPE_SENSE_MASK;
0832 
0833     dev_dbg(&pmic_arb->spmic->dev, "out_hwirq = %lu\n", *out_hwirq);
0834 
0835     return 0;
0836 }
0837 
0838 static struct lock_class_key qpnpint_irq_lock_class, qpnpint_irq_request_class;
0839 
0840 static void qpnpint_irq_domain_map(struct spmi_pmic_arb *pmic_arb,
0841                    struct irq_domain *domain, unsigned int virq,
0842                    irq_hw_number_t hwirq, unsigned int type)
0843 {
0844     irq_flow_handler_t handler;
0845 
0846     dev_dbg(&pmic_arb->spmic->dev, "virq = %u, hwirq = %lu, type = %u\n",
0847         virq, hwirq, type);
0848 
0849     if (type & IRQ_TYPE_EDGE_BOTH)
0850         handler = handle_edge_irq;
0851     else
0852         handler = handle_level_irq;
0853 
0854 
0855     irq_set_lockdep_class(virq, &qpnpint_irq_lock_class,
0856                   &qpnpint_irq_request_class);
0857     irq_domain_set_info(domain, virq, hwirq, &pmic_arb_irqchip, pmic_arb,
0858                 handler, NULL, NULL);
0859 }
0860 
0861 static int qpnpint_irq_domain_alloc(struct irq_domain *domain,
0862                     unsigned int virq, unsigned int nr_irqs,
0863                     void *data)
0864 {
0865     struct spmi_pmic_arb *pmic_arb = domain->host_data;
0866     struct irq_fwspec *fwspec = data;
0867     irq_hw_number_t hwirq;
0868     unsigned int type;
0869     int ret, i;
0870 
0871     ret = qpnpint_irq_domain_translate(domain, fwspec, &hwirq, &type);
0872     if (ret)
0873         return ret;
0874 
0875     for (i = 0; i < nr_irqs; i++)
0876         qpnpint_irq_domain_map(pmic_arb, domain, virq + i, hwirq + i,
0877                        type);
0878 
0879     return 0;
0880 }
0881 
0882 static int pmic_arb_ppid_to_apid_v1(struct spmi_pmic_arb *pmic_arb, u16 ppid)
0883 {
0884     u32 *mapping_table = pmic_arb->mapping_table;
0885     int index = 0, i;
0886     u16 apid_valid;
0887     u16 apid;
0888     u32 data;
0889 
0890     apid_valid = pmic_arb->ppid_to_apid[ppid];
0891     if (apid_valid & PMIC_ARB_APID_VALID) {
0892         apid = apid_valid & ~PMIC_ARB_APID_VALID;
0893         return apid;
0894     }
0895 
0896     for (i = 0; i < SPMI_MAPPING_TABLE_TREE_DEPTH; ++i) {
0897         if (!test_and_set_bit(index, pmic_arb->mapping_table_valid))
0898             mapping_table[index] = readl_relaxed(pmic_arb->cnfg +
0899                         SPMI_MAPPING_TABLE_REG(index));
0900 
0901         data = mapping_table[index];
0902 
0903         if (ppid & BIT(SPMI_MAPPING_BIT_INDEX(data))) {
0904             if (SPMI_MAPPING_BIT_IS_1_FLAG(data)) {
0905                 index = SPMI_MAPPING_BIT_IS_1_RESULT(data);
0906             } else {
0907                 apid = SPMI_MAPPING_BIT_IS_1_RESULT(data);
0908                 pmic_arb->ppid_to_apid[ppid]
0909                     = apid | PMIC_ARB_APID_VALID;
0910                 pmic_arb->apid_data[apid].ppid = ppid;
0911                 return apid;
0912             }
0913         } else {
0914             if (SPMI_MAPPING_BIT_IS_0_FLAG(data)) {
0915                 index = SPMI_MAPPING_BIT_IS_0_RESULT(data);
0916             } else {
0917                 apid = SPMI_MAPPING_BIT_IS_0_RESULT(data);
0918                 pmic_arb->ppid_to_apid[ppid]
0919                     = apid | PMIC_ARB_APID_VALID;
0920                 pmic_arb->apid_data[apid].ppid = ppid;
0921                 return apid;
0922             }
0923         }
0924     }
0925 
0926     return -ENODEV;
0927 }
0928 
0929 /* v1 offset per ee */
0930 static int pmic_arb_offset_v1(struct spmi_pmic_arb *pmic_arb, u8 sid, u16 addr,
0931             enum pmic_arb_channel ch_type)
0932 {
0933     return 0x800 + 0x80 * pmic_arb->channel;
0934 }
0935 
0936 static u16 pmic_arb_find_apid(struct spmi_pmic_arb *pmic_arb, u16 ppid)
0937 {
0938     struct apid_data *apidd = &pmic_arb->apid_data[pmic_arb->last_apid];
0939     u32 regval, offset;
0940     u16 id, apid;
0941 
0942     for (apid = pmic_arb->last_apid; ; apid++, apidd++) {
0943         offset = pmic_arb->ver_ops->apid_map_offset(apid);
0944         if (offset >= pmic_arb->core_size)
0945             break;
0946 
0947         regval = readl_relaxed(pmic_arb->cnfg +
0948                       SPMI_OWNERSHIP_TABLE_REG(apid));
0949         apidd->irq_ee = SPMI_OWNERSHIP_PERIPH2OWNER(regval);
0950         apidd->write_ee = apidd->irq_ee;
0951 
0952         regval = readl_relaxed(pmic_arb->core + offset);
0953         if (!regval)
0954             continue;
0955 
0956         id = (regval >> 8) & PMIC_ARB_PPID_MASK;
0957         pmic_arb->ppid_to_apid[id] = apid | PMIC_ARB_APID_VALID;
0958         apidd->ppid = id;
0959         if (id == ppid) {
0960             apid |= PMIC_ARB_APID_VALID;
0961             break;
0962         }
0963     }
0964     pmic_arb->last_apid = apid & ~PMIC_ARB_APID_VALID;
0965 
0966     return apid;
0967 }
0968 
0969 static int pmic_arb_ppid_to_apid_v2(struct spmi_pmic_arb *pmic_arb, u16 ppid)
0970 {
0971     u16 apid_valid;
0972 
0973     apid_valid = pmic_arb->ppid_to_apid[ppid];
0974     if (!(apid_valid & PMIC_ARB_APID_VALID))
0975         apid_valid = pmic_arb_find_apid(pmic_arb, ppid);
0976     if (!(apid_valid & PMIC_ARB_APID_VALID))
0977         return -ENODEV;
0978 
0979     return apid_valid & ~PMIC_ARB_APID_VALID;
0980 }
0981 
0982 static int pmic_arb_read_apid_map_v5(struct spmi_pmic_arb *pmic_arb)
0983 {
0984     struct apid_data *apidd = pmic_arb->apid_data;
0985     struct apid_data *prev_apidd;
0986     u16 i, apid, ppid;
0987     bool valid, is_irq_ee;
0988     u32 regval, offset;
0989 
0990     /*
0991      * In order to allow multiple EEs to write to a single PPID in arbiter
0992      * version 5, there is more than one APID mapped to each PPID.
0993      * The owner field for each of these mappings specifies the EE which is
0994      * allowed to write to the APID.  The owner of the last (highest) APID
0995      * for a given PPID will receive interrupts from the PPID.
0996      */
0997     for (i = 0; ; i++, apidd++) {
0998         offset = pmic_arb->ver_ops->apid_map_offset(i);
0999         if (offset >= pmic_arb->core_size)
1000             break;
1001 
1002         regval = readl_relaxed(pmic_arb->core + offset);
1003         if (!regval)
1004             continue;
1005         ppid = (regval >> 8) & PMIC_ARB_PPID_MASK;
1006         is_irq_ee = PMIC_ARB_CHAN_IS_IRQ_OWNER(regval);
1007 
1008         regval = readl_relaxed(pmic_arb->cnfg +
1009                       SPMI_OWNERSHIP_TABLE_REG(i));
1010         apidd->write_ee = SPMI_OWNERSHIP_PERIPH2OWNER(regval);
1011 
1012         apidd->irq_ee = is_irq_ee ? apidd->write_ee : INVALID_EE;
1013 
1014         valid = pmic_arb->ppid_to_apid[ppid] & PMIC_ARB_APID_VALID;
1015         apid = pmic_arb->ppid_to_apid[ppid] & ~PMIC_ARB_APID_VALID;
1016         prev_apidd = &pmic_arb->apid_data[apid];
1017 
1018         if (valid && is_irq_ee &&
1019                 prev_apidd->write_ee == pmic_arb->ee) {
1020             /*
1021              * Duplicate PPID mapping after the one for this EE;
1022              * override the irq owner
1023              */
1024             prev_apidd->irq_ee = apidd->irq_ee;
1025         } else if (!valid || is_irq_ee) {
1026             /* First PPID mapping or duplicate for another EE */
1027             pmic_arb->ppid_to_apid[ppid] = i | PMIC_ARB_APID_VALID;
1028         }
1029 
1030         apidd->ppid = ppid;
1031         pmic_arb->last_apid = i;
1032     }
1033 
1034     /* Dump the mapping table for debug purposes. */
1035     dev_dbg(&pmic_arb->spmic->dev, "PPID APID Write-EE IRQ-EE\n");
1036     for (ppid = 0; ppid < PMIC_ARB_MAX_PPID; ppid++) {
1037         apid = pmic_arb->ppid_to_apid[ppid];
1038         if (apid & PMIC_ARB_APID_VALID) {
1039             apid &= ~PMIC_ARB_APID_VALID;
1040             apidd = &pmic_arb->apid_data[apid];
1041             dev_dbg(&pmic_arb->spmic->dev, "%#03X %3u %2u %2u\n",
1042                   ppid, apid, apidd->write_ee, apidd->irq_ee);
1043         }
1044     }
1045 
1046     return 0;
1047 }
1048 
1049 static int pmic_arb_ppid_to_apid_v5(struct spmi_pmic_arb *pmic_arb, u16 ppid)
1050 {
1051     if (!(pmic_arb->ppid_to_apid[ppid] & PMIC_ARB_APID_VALID))
1052         return -ENODEV;
1053 
1054     return pmic_arb->ppid_to_apid[ppid] & ~PMIC_ARB_APID_VALID;
1055 }
1056 
1057 /* v2 offset per ppid and per ee */
1058 static int pmic_arb_offset_v2(struct spmi_pmic_arb *pmic_arb, u8 sid, u16 addr,
1059                enum pmic_arb_channel ch_type)
1060 {
1061     u16 apid;
1062     u16 ppid;
1063     int rc;
1064 
1065     ppid = sid << 8 | ((addr >> 8) & 0xFF);
1066     rc = pmic_arb_ppid_to_apid_v2(pmic_arb, ppid);
1067     if (rc < 0)
1068         return rc;
1069 
1070     apid = rc;
1071     return 0x1000 * pmic_arb->ee + 0x8000 * apid;
1072 }
1073 
1074 /*
1075  * v5 offset per ee and per apid for observer channels and per apid for
1076  * read/write channels.
1077  */
1078 static int pmic_arb_offset_v5(struct spmi_pmic_arb *pmic_arb, u8 sid, u16 addr,
1079                enum pmic_arb_channel ch_type)
1080 {
1081     u16 apid;
1082     int rc;
1083     u32 offset = 0;
1084     u16 ppid = (sid << 8) | (addr >> 8);
1085 
1086     rc = pmic_arb_ppid_to_apid_v5(pmic_arb, ppid);
1087     if (rc < 0)
1088         return rc;
1089 
1090     apid = rc;
1091     switch (ch_type) {
1092     case PMIC_ARB_CHANNEL_OBS:
1093         offset = 0x10000 * pmic_arb->ee + 0x80 * apid;
1094         break;
1095     case PMIC_ARB_CHANNEL_RW:
1096         offset = 0x10000 * apid;
1097         break;
1098     }
1099 
1100     return offset;
1101 }
1102 
1103 static u32 pmic_arb_fmt_cmd_v1(u8 opc, u8 sid, u16 addr, u8 bc)
1104 {
1105     return (opc << 27) | ((sid & 0xf) << 20) | (addr << 4) | (bc & 0x7);
1106 }
1107 
1108 static u32 pmic_arb_fmt_cmd_v2(u8 opc, u8 sid, u16 addr, u8 bc)
1109 {
1110     return (opc << 27) | ((addr & 0xff) << 4) | (bc & 0x7);
1111 }
1112 
1113 static void __iomem *
1114 pmic_arb_owner_acc_status_v1(struct spmi_pmic_arb *pmic_arb, u8 m, u16 n)
1115 {
1116     return pmic_arb->intr + 0x20 * m + 0x4 * n;
1117 }
1118 
1119 static void __iomem *
1120 pmic_arb_owner_acc_status_v2(struct spmi_pmic_arb *pmic_arb, u8 m, u16 n)
1121 {
1122     return pmic_arb->intr + 0x100000 + 0x1000 * m + 0x4 * n;
1123 }
1124 
1125 static void __iomem *
1126 pmic_arb_owner_acc_status_v3(struct spmi_pmic_arb *pmic_arb, u8 m, u16 n)
1127 {
1128     return pmic_arb->intr + 0x200000 + 0x1000 * m + 0x4 * n;
1129 }
1130 
1131 static void __iomem *
1132 pmic_arb_owner_acc_status_v5(struct spmi_pmic_arb *pmic_arb, u8 m, u16 n)
1133 {
1134     return pmic_arb->intr + 0x10000 * m + 0x4 * n;
1135 }
1136 
1137 static void __iomem *
1138 pmic_arb_acc_enable_v1(struct spmi_pmic_arb *pmic_arb, u16 n)
1139 {
1140     return pmic_arb->intr + 0x200 + 0x4 * n;
1141 }
1142 
1143 static void __iomem *
1144 pmic_arb_acc_enable_v2(struct spmi_pmic_arb *pmic_arb, u16 n)
1145 {
1146     return pmic_arb->intr + 0x1000 * n;
1147 }
1148 
1149 static void __iomem *
1150 pmic_arb_acc_enable_v5(struct spmi_pmic_arb *pmic_arb, u16 n)
1151 {
1152     return pmic_arb->wr_base + 0x100 + 0x10000 * n;
1153 }
1154 
1155 static void __iomem *
1156 pmic_arb_irq_status_v1(struct spmi_pmic_arb *pmic_arb, u16 n)
1157 {
1158     return pmic_arb->intr + 0x600 + 0x4 * n;
1159 }
1160 
1161 static void __iomem *
1162 pmic_arb_irq_status_v2(struct spmi_pmic_arb *pmic_arb, u16 n)
1163 {
1164     return pmic_arb->intr + 0x4 + 0x1000 * n;
1165 }
1166 
1167 static void __iomem *
1168 pmic_arb_irq_status_v5(struct spmi_pmic_arb *pmic_arb, u16 n)
1169 {
1170     return pmic_arb->wr_base + 0x104 + 0x10000 * n;
1171 }
1172 
1173 static void __iomem *
1174 pmic_arb_irq_clear_v1(struct spmi_pmic_arb *pmic_arb, u16 n)
1175 {
1176     return pmic_arb->intr + 0xA00 + 0x4 * n;
1177 }
1178 
1179 static void __iomem *
1180 pmic_arb_irq_clear_v2(struct spmi_pmic_arb *pmic_arb, u16 n)
1181 {
1182     return pmic_arb->intr + 0x8 + 0x1000 * n;
1183 }
1184 
1185 static void __iomem *
1186 pmic_arb_irq_clear_v5(struct spmi_pmic_arb *pmic_arb, u16 n)
1187 {
1188     return pmic_arb->wr_base + 0x108 + 0x10000 * n;
1189 }
1190 
1191 static u32 pmic_arb_apid_map_offset_v2(u16 n)
1192 {
1193     return 0x800 + 0x4 * n;
1194 }
1195 
1196 static u32 pmic_arb_apid_map_offset_v5(u16 n)
1197 {
1198     return 0x900 + 0x4 * n;
1199 }
1200 
1201 static const struct pmic_arb_ver_ops pmic_arb_v1 = {
1202     .ver_str        = "v1",
1203     .ppid_to_apid       = pmic_arb_ppid_to_apid_v1,
1204     .non_data_cmd       = pmic_arb_non_data_cmd_v1,
1205     .offset         = pmic_arb_offset_v1,
1206     .fmt_cmd        = pmic_arb_fmt_cmd_v1,
1207     .owner_acc_status   = pmic_arb_owner_acc_status_v1,
1208     .acc_enable     = pmic_arb_acc_enable_v1,
1209     .irq_status     = pmic_arb_irq_status_v1,
1210     .irq_clear      = pmic_arb_irq_clear_v1,
1211     .apid_map_offset    = pmic_arb_apid_map_offset_v2,
1212 };
1213 
1214 static const struct pmic_arb_ver_ops pmic_arb_v2 = {
1215     .ver_str        = "v2",
1216     .ppid_to_apid       = pmic_arb_ppid_to_apid_v2,
1217     .non_data_cmd       = pmic_arb_non_data_cmd_v2,
1218     .offset         = pmic_arb_offset_v2,
1219     .fmt_cmd        = pmic_arb_fmt_cmd_v2,
1220     .owner_acc_status   = pmic_arb_owner_acc_status_v2,
1221     .acc_enable     = pmic_arb_acc_enable_v2,
1222     .irq_status     = pmic_arb_irq_status_v2,
1223     .irq_clear      = pmic_arb_irq_clear_v2,
1224     .apid_map_offset    = pmic_arb_apid_map_offset_v2,
1225 };
1226 
1227 static const struct pmic_arb_ver_ops pmic_arb_v3 = {
1228     .ver_str        = "v3",
1229     .ppid_to_apid       = pmic_arb_ppid_to_apid_v2,
1230     .non_data_cmd       = pmic_arb_non_data_cmd_v2,
1231     .offset         = pmic_arb_offset_v2,
1232     .fmt_cmd        = pmic_arb_fmt_cmd_v2,
1233     .owner_acc_status   = pmic_arb_owner_acc_status_v3,
1234     .acc_enable     = pmic_arb_acc_enable_v2,
1235     .irq_status     = pmic_arb_irq_status_v2,
1236     .irq_clear      = pmic_arb_irq_clear_v2,
1237     .apid_map_offset    = pmic_arb_apid_map_offset_v2,
1238 };
1239 
1240 static const struct pmic_arb_ver_ops pmic_arb_v5 = {
1241     .ver_str        = "v5",
1242     .ppid_to_apid       = pmic_arb_ppid_to_apid_v5,
1243     .non_data_cmd       = pmic_arb_non_data_cmd_v2,
1244     .offset         = pmic_arb_offset_v5,
1245     .fmt_cmd        = pmic_arb_fmt_cmd_v2,
1246     .owner_acc_status   = pmic_arb_owner_acc_status_v5,
1247     .acc_enable     = pmic_arb_acc_enable_v5,
1248     .irq_status     = pmic_arb_irq_status_v5,
1249     .irq_clear      = pmic_arb_irq_clear_v5,
1250     .apid_map_offset    = pmic_arb_apid_map_offset_v5,
1251 };
1252 
1253 static const struct irq_domain_ops pmic_arb_irq_domain_ops = {
1254     .activate = qpnpint_irq_domain_activate,
1255     .alloc = qpnpint_irq_domain_alloc,
1256     .free = irq_domain_free_irqs_common,
1257     .translate = qpnpint_irq_domain_translate,
1258 };
1259 
1260 static int spmi_pmic_arb_probe(struct platform_device *pdev)
1261 {
1262     struct spmi_pmic_arb *pmic_arb;
1263     struct spmi_controller *ctrl;
1264     struct resource *res;
1265     void __iomem *core;
1266     u32 *mapping_table;
1267     u32 channel, ee, hw_ver;
1268     int err;
1269 
1270     ctrl = spmi_controller_alloc(&pdev->dev, sizeof(*pmic_arb));
1271     if (!ctrl)
1272         return -ENOMEM;
1273 
1274     pmic_arb = spmi_controller_get_drvdata(ctrl);
1275     pmic_arb->spmic = ctrl;
1276 
1277     res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "core");
1278     core = devm_ioremap_resource(&ctrl->dev, res);
1279     if (IS_ERR(core)) {
1280         err = PTR_ERR(core);
1281         goto err_put_ctrl;
1282     }
1283 
1284     pmic_arb->core_size = resource_size(res);
1285 
1286     pmic_arb->ppid_to_apid = devm_kcalloc(&ctrl->dev, PMIC_ARB_MAX_PPID,
1287                           sizeof(*pmic_arb->ppid_to_apid),
1288                           GFP_KERNEL);
1289     if (!pmic_arb->ppid_to_apid) {
1290         err = -ENOMEM;
1291         goto err_put_ctrl;
1292     }
1293 
1294     hw_ver = readl_relaxed(core + PMIC_ARB_VERSION);
1295 
1296     if (hw_ver < PMIC_ARB_VERSION_V2_MIN) {
1297         pmic_arb->ver_ops = &pmic_arb_v1;
1298         pmic_arb->wr_base = core;
1299         pmic_arb->rd_base = core;
1300     } else {
1301         pmic_arb->core = core;
1302 
1303         if (hw_ver < PMIC_ARB_VERSION_V3_MIN)
1304             pmic_arb->ver_ops = &pmic_arb_v2;
1305         else if (hw_ver < PMIC_ARB_VERSION_V5_MIN)
1306             pmic_arb->ver_ops = &pmic_arb_v3;
1307         else
1308             pmic_arb->ver_ops = &pmic_arb_v5;
1309 
1310         res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
1311                            "obsrvr");
1312         pmic_arb->rd_base = devm_ioremap_resource(&ctrl->dev, res);
1313         if (IS_ERR(pmic_arb->rd_base)) {
1314             err = PTR_ERR(pmic_arb->rd_base);
1315             goto err_put_ctrl;
1316         }
1317 
1318         res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
1319                            "chnls");
1320         pmic_arb->wr_base = devm_ioremap_resource(&ctrl->dev, res);
1321         if (IS_ERR(pmic_arb->wr_base)) {
1322             err = PTR_ERR(pmic_arb->wr_base);
1323             goto err_put_ctrl;
1324         }
1325     }
1326 
1327     dev_info(&ctrl->dev, "PMIC arbiter version %s (0x%x)\n",
1328          pmic_arb->ver_ops->ver_str, hw_ver);
1329 
1330     res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "intr");
1331     pmic_arb->intr = devm_ioremap_resource(&ctrl->dev, res);
1332     if (IS_ERR(pmic_arb->intr)) {
1333         err = PTR_ERR(pmic_arb->intr);
1334         goto err_put_ctrl;
1335     }
1336 
1337     res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cnfg");
1338     pmic_arb->cnfg = devm_ioremap_resource(&ctrl->dev, res);
1339     if (IS_ERR(pmic_arb->cnfg)) {
1340         err = PTR_ERR(pmic_arb->cnfg);
1341         goto err_put_ctrl;
1342     }
1343 
1344     pmic_arb->irq = platform_get_irq_byname(pdev, "periph_irq");
1345     if (pmic_arb->irq < 0) {
1346         err = pmic_arb->irq;
1347         goto err_put_ctrl;
1348     }
1349 
1350     err = of_property_read_u32(pdev->dev.of_node, "qcom,channel", &channel);
1351     if (err) {
1352         dev_err(&pdev->dev, "channel unspecified.\n");
1353         goto err_put_ctrl;
1354     }
1355 
1356     if (channel > 5) {
1357         dev_err(&pdev->dev, "invalid channel (%u) specified.\n",
1358             channel);
1359         err = -EINVAL;
1360         goto err_put_ctrl;
1361     }
1362 
1363     pmic_arb->channel = channel;
1364 
1365     err = of_property_read_u32(pdev->dev.of_node, "qcom,ee", &ee);
1366     if (err) {
1367         dev_err(&pdev->dev, "EE unspecified.\n");
1368         goto err_put_ctrl;
1369     }
1370 
1371     if (ee > 5) {
1372         dev_err(&pdev->dev, "invalid EE (%u) specified\n", ee);
1373         err = -EINVAL;
1374         goto err_put_ctrl;
1375     }
1376 
1377     pmic_arb->ee = ee;
1378     mapping_table = devm_kcalloc(&ctrl->dev, PMIC_ARB_MAX_PERIPHS,
1379                     sizeof(*mapping_table), GFP_KERNEL);
1380     if (!mapping_table) {
1381         err = -ENOMEM;
1382         goto err_put_ctrl;
1383     }
1384 
1385     pmic_arb->mapping_table = mapping_table;
1386     /* Initialize max_apid/min_apid to the opposite bounds, during
1387      * the irq domain translation, we are sure to update these */
1388     pmic_arb->max_apid = 0;
1389     pmic_arb->min_apid = PMIC_ARB_MAX_PERIPHS - 1;
1390 
1391     platform_set_drvdata(pdev, ctrl);
1392     raw_spin_lock_init(&pmic_arb->lock);
1393 
1394     ctrl->cmd = pmic_arb_cmd;
1395     ctrl->read_cmd = pmic_arb_read_cmd;
1396     ctrl->write_cmd = pmic_arb_write_cmd;
1397 
1398     if (hw_ver >= PMIC_ARB_VERSION_V5_MIN) {
1399         err = pmic_arb_read_apid_map_v5(pmic_arb);
1400         if (err) {
1401             dev_err(&pdev->dev, "could not read APID->PPID mapping table, rc= %d\n",
1402                 err);
1403             goto err_put_ctrl;
1404         }
1405     }
1406 
1407     dev_dbg(&pdev->dev, "adding irq domain\n");
1408     pmic_arb->domain = irq_domain_add_tree(pdev->dev.of_node,
1409                      &pmic_arb_irq_domain_ops, pmic_arb);
1410     if (!pmic_arb->domain) {
1411         dev_err(&pdev->dev, "unable to create irq_domain\n");
1412         err = -ENOMEM;
1413         goto err_put_ctrl;
1414     }
1415 
1416     irq_set_chained_handler_and_data(pmic_arb->irq, pmic_arb_chained_irq,
1417                     pmic_arb);
1418     err = spmi_controller_add(ctrl);
1419     if (err)
1420         goto err_domain_remove;
1421 
1422     return 0;
1423 
1424 err_domain_remove:
1425     irq_set_chained_handler_and_data(pmic_arb->irq, NULL, NULL);
1426     irq_domain_remove(pmic_arb->domain);
1427 err_put_ctrl:
1428     spmi_controller_put(ctrl);
1429     return err;
1430 }
1431 
1432 static int spmi_pmic_arb_remove(struct platform_device *pdev)
1433 {
1434     struct spmi_controller *ctrl = platform_get_drvdata(pdev);
1435     struct spmi_pmic_arb *pmic_arb = spmi_controller_get_drvdata(ctrl);
1436     spmi_controller_remove(ctrl);
1437     irq_set_chained_handler_and_data(pmic_arb->irq, NULL, NULL);
1438     irq_domain_remove(pmic_arb->domain);
1439     spmi_controller_put(ctrl);
1440     return 0;
1441 }
1442 
1443 static const struct of_device_id spmi_pmic_arb_match_table[] = {
1444     { .compatible = "qcom,spmi-pmic-arb", },
1445     {},
1446 };
1447 MODULE_DEVICE_TABLE(of, spmi_pmic_arb_match_table);
1448 
1449 static struct platform_driver spmi_pmic_arb_driver = {
1450     .probe      = spmi_pmic_arb_probe,
1451     .remove     = spmi_pmic_arb_remove,
1452     .driver     = {
1453         .name   = "spmi_pmic_arb",
1454         .of_match_table = spmi_pmic_arb_match_table,
1455     },
1456 };
1457 module_platform_driver(spmi_pmic_arb_driver);
1458 
1459 MODULE_LICENSE("GPL v2");
1460 MODULE_ALIAS("platform:spmi_pmic_arb");
[ Source navigation ] [ Diff markup ] [ Identifier search ] [ general search ]

This page was automatically generated by the 2.1.0 LXR engine.

The LXR team
Valid CSS 2.1! Valid HTML 4.01!