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0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Xilinx Zynq UltraScale+ MPSoC Quad-SPI (QSPI) controller driver
0004  * (master mode only)
0005  *
0006  * Copyright (C) 2009 - 2015 Xilinx, Inc.
0007  */
0008 
0009 #include <linux/clk.h>
0010 #include <linux/delay.h>
0011 #include <linux/dma-mapping.h>
0012 #include <linux/dmaengine.h>
0013 #include <linux/firmware/xlnx-zynqmp.h>
0014 #include <linux/interrupt.h>
0015 #include <linux/io.h>
0016 #include <linux/module.h>
0017 #include <linux/of_irq.h>
0018 #include <linux/of_address.h>
0019 #include <linux/platform_device.h>
0020 #include <linux/pm_runtime.h>
0021 #include <linux/spi/spi.h>
0022 #include <linux/spinlock.h>
0023 #include <linux/workqueue.h>
0024 #include <linux/spi/spi-mem.h>
0025 
0026 /* Generic QSPI register offsets */
0027 #define GQSPI_CONFIG_OFST       0x00000100
0028 #define GQSPI_ISR_OFST          0x00000104
0029 #define GQSPI_IDR_OFST          0x0000010C
0030 #define GQSPI_IER_OFST          0x00000108
0031 #define GQSPI_IMASK_OFST        0x00000110
0032 #define GQSPI_EN_OFST           0x00000114
0033 #define GQSPI_TXD_OFST          0x0000011C
0034 #define GQSPI_RXD_OFST          0x00000120
0035 #define GQSPI_TX_THRESHOLD_OFST     0x00000128
0036 #define GQSPI_RX_THRESHOLD_OFST     0x0000012C
0037 #define GQSPI_LPBK_DLY_ADJ_OFST     0x00000138
0038 #define GQSPI_GEN_FIFO_OFST     0x00000140
0039 #define GQSPI_SEL_OFST          0x00000144
0040 #define GQSPI_GF_THRESHOLD_OFST     0x00000150
0041 #define GQSPI_FIFO_CTRL_OFST        0x0000014C
0042 #define GQSPI_QSPIDMA_DST_CTRL_OFST 0x0000080C
0043 #define GQSPI_QSPIDMA_DST_SIZE_OFST 0x00000804
0044 #define GQSPI_QSPIDMA_DST_STS_OFST  0x00000808
0045 #define GQSPI_QSPIDMA_DST_I_STS_OFST    0x00000814
0046 #define GQSPI_QSPIDMA_DST_I_EN_OFST 0x00000818
0047 #define GQSPI_QSPIDMA_DST_I_DIS_OFST    0x0000081C
0048 #define GQSPI_QSPIDMA_DST_I_MASK_OFST   0x00000820
0049 #define GQSPI_QSPIDMA_DST_ADDR_OFST 0x00000800
0050 #define GQSPI_QSPIDMA_DST_ADDR_MSB_OFST 0x00000828
0051 
0052 /* GQSPI register bit masks */
0053 #define GQSPI_SEL_MASK              0x00000001
0054 #define GQSPI_EN_MASK               0x00000001
0055 #define GQSPI_LPBK_DLY_ADJ_USE_LPBK_MASK    0x00000020
0056 #define GQSPI_ISR_WR_TO_CLR_MASK        0x00000002
0057 #define GQSPI_IDR_ALL_MASK          0x00000FBE
0058 #define GQSPI_CFG_MODE_EN_MASK          0xC0000000
0059 #define GQSPI_CFG_GEN_FIFO_START_MODE_MASK  0x20000000
0060 #define GQSPI_CFG_ENDIAN_MASK           0x04000000
0061 #define GQSPI_CFG_EN_POLL_TO_MASK       0x00100000
0062 #define GQSPI_CFG_WP_HOLD_MASK          0x00080000
0063 #define GQSPI_CFG_BAUD_RATE_DIV_MASK        0x00000038
0064 #define GQSPI_CFG_CLK_PHA_MASK          0x00000004
0065 #define GQSPI_CFG_CLK_POL_MASK          0x00000002
0066 #define GQSPI_CFG_START_GEN_FIFO_MASK       0x10000000
0067 #define GQSPI_GENFIFO_IMM_DATA_MASK     0x000000FF
0068 #define GQSPI_GENFIFO_DATA_XFER         0x00000100
0069 #define GQSPI_GENFIFO_EXP           0x00000200
0070 #define GQSPI_GENFIFO_MODE_SPI          0x00000400
0071 #define GQSPI_GENFIFO_MODE_DUALSPI      0x00000800
0072 #define GQSPI_GENFIFO_MODE_QUADSPI      0x00000C00
0073 #define GQSPI_GENFIFO_MODE_MASK         0x00000C00
0074 #define GQSPI_GENFIFO_CS_LOWER          0x00001000
0075 #define GQSPI_GENFIFO_CS_UPPER          0x00002000
0076 #define GQSPI_GENFIFO_BUS_LOWER         0x00004000
0077 #define GQSPI_GENFIFO_BUS_UPPER         0x00008000
0078 #define GQSPI_GENFIFO_BUS_BOTH          0x0000C000
0079 #define GQSPI_GENFIFO_BUS_MASK          0x0000C000
0080 #define GQSPI_GENFIFO_TX            0x00010000
0081 #define GQSPI_GENFIFO_RX            0x00020000
0082 #define GQSPI_GENFIFO_STRIPE            0x00040000
0083 #define GQSPI_GENFIFO_POLL          0x00080000
0084 #define GQSPI_GENFIFO_EXP_START         0x00000100
0085 #define GQSPI_FIFO_CTRL_RST_RX_FIFO_MASK    0x00000004
0086 #define GQSPI_FIFO_CTRL_RST_TX_FIFO_MASK    0x00000002
0087 #define GQSPI_FIFO_CTRL_RST_GEN_FIFO_MASK   0x00000001
0088 #define GQSPI_ISR_RXEMPTY_MASK          0x00000800
0089 #define GQSPI_ISR_GENFIFOFULL_MASK      0x00000400
0090 #define GQSPI_ISR_GENFIFONOT_FULL_MASK      0x00000200
0091 #define GQSPI_ISR_TXEMPTY_MASK          0x00000100
0092 #define GQSPI_ISR_GENFIFOEMPTY_MASK     0x00000080
0093 #define GQSPI_ISR_RXFULL_MASK           0x00000020
0094 #define GQSPI_ISR_RXNEMPTY_MASK         0x00000010
0095 #define GQSPI_ISR_TXFULL_MASK           0x00000008
0096 #define GQSPI_ISR_TXNOT_FULL_MASK       0x00000004
0097 #define GQSPI_ISR_POLL_TIME_EXPIRE_MASK     0x00000002
0098 #define GQSPI_IER_TXNOT_FULL_MASK       0x00000004
0099 #define GQSPI_IER_RXEMPTY_MASK          0x00000800
0100 #define GQSPI_IER_POLL_TIME_EXPIRE_MASK     0x00000002
0101 #define GQSPI_IER_RXNEMPTY_MASK         0x00000010
0102 #define GQSPI_IER_GENFIFOEMPTY_MASK     0x00000080
0103 #define GQSPI_IER_TXEMPTY_MASK          0x00000100
0104 #define GQSPI_QSPIDMA_DST_INTR_ALL_MASK     0x000000FE
0105 #define GQSPI_QSPIDMA_DST_STS_WTC       0x0000E000
0106 #define GQSPI_CFG_MODE_EN_DMA_MASK      0x80000000
0107 #define GQSPI_ISR_IDR_MASK          0x00000994
0108 #define GQSPI_QSPIDMA_DST_I_EN_DONE_MASK    0x00000002
0109 #define GQSPI_QSPIDMA_DST_I_STS_DONE_MASK   0x00000002
0110 #define GQSPI_IRQ_MASK              0x00000980
0111 
0112 #define GQSPI_CFG_BAUD_RATE_DIV_SHIFT       3
0113 #define GQSPI_GENFIFO_CS_SETUP          0x4
0114 #define GQSPI_GENFIFO_CS_HOLD           0x3
0115 #define GQSPI_TXD_DEPTH             64
0116 #define GQSPI_RX_FIFO_THRESHOLD         32
0117 #define GQSPI_RX_FIFO_FILL  (GQSPI_RX_FIFO_THRESHOLD * 4)
0118 #define GQSPI_TX_FIFO_THRESHOLD_RESET_VAL   32
0119 #define GQSPI_TX_FIFO_FILL  (GQSPI_TXD_DEPTH -\
0120                 GQSPI_TX_FIFO_THRESHOLD_RESET_VAL)
0121 #define GQSPI_GEN_FIFO_THRESHOLD_RESET_VAL  0X10
0122 #define GQSPI_QSPIDMA_DST_CTRL_RESET_VAL    0x803FFA00
0123 #define GQSPI_SELECT_FLASH_CS_LOWER     0x1
0124 #define GQSPI_SELECT_FLASH_CS_UPPER     0x2
0125 #define GQSPI_SELECT_FLASH_CS_BOTH      0x3
0126 #define GQSPI_SELECT_FLASH_BUS_LOWER        0x1
0127 #define GQSPI_SELECT_FLASH_BUS_UPPER        0x2
0128 #define GQSPI_SELECT_FLASH_BUS_BOTH     0x3
0129 #define GQSPI_BAUD_DIV_MAX  7   /* Baud rate divisor maximum */
0130 #define GQSPI_BAUD_DIV_SHIFT    2   /* Baud rate divisor shift */
0131 #define GQSPI_SELECT_MODE_SPI       0x1
0132 #define GQSPI_SELECT_MODE_DUALSPI   0x2
0133 #define GQSPI_SELECT_MODE_QUADSPI   0x4
0134 #define GQSPI_DMA_UNALIGN       0x3
0135 #define GQSPI_DEFAULT_NUM_CS    1   /* Default number of chip selects */
0136 
0137 #define GQSPI_MAX_NUM_CS    2   /* Maximum number of chip selects */
0138 
0139 #define SPI_AUTOSUSPEND_TIMEOUT     3000
0140 enum mode_type {GQSPI_MODE_IO, GQSPI_MODE_DMA};
0141 
0142 /**
0143  * struct zynqmp_qspi - Defines qspi driver instance
0144  * @regs:       Virtual address of the QSPI controller registers
0145  * @refclk:     Pointer to the peripheral clock
0146  * @pclk:       Pointer to the APB clock
0147  * @irq:        IRQ number
0148  * @dev:        Pointer to struct device
0149  * @txbuf:      Pointer to the TX buffer
0150  * @rxbuf:      Pointer to the RX buffer
0151  * @bytes_to_transfer:  Number of bytes left to transfer
0152  * @bytes_to_receive:   Number of bytes left to receive
0153  * @genfifocs:      Used for chip select
0154  * @genfifobus:     Used to select the upper or lower bus
0155  * @dma_rx_bytes:   Remaining bytes to receive by DMA mode
0156  * @dma_addr:       DMA address after mapping the kernel buffer
0157  * @genfifoentry:   Used for storing the genfifoentry instruction.
0158  * @mode:       Defines the mode in which QSPI is operating
0159  * @data_completion:    completion structure
0160  */
0161 struct zynqmp_qspi {
0162     struct spi_controller *ctlr;
0163     void __iomem *regs;
0164     struct clk *refclk;
0165     struct clk *pclk;
0166     int irq;
0167     struct device *dev;
0168     const void *txbuf;
0169     void *rxbuf;
0170     int bytes_to_transfer;
0171     int bytes_to_receive;
0172     u32 genfifocs;
0173     u32 genfifobus;
0174     u32 dma_rx_bytes;
0175     dma_addr_t dma_addr;
0176     u32 genfifoentry;
0177     enum mode_type mode;
0178     struct completion data_completion;
0179     struct mutex op_lock;
0180 };
0181 
0182 /**
0183  * zynqmp_gqspi_read - For GQSPI controller read operation
0184  * @xqspi:  Pointer to the zynqmp_qspi structure
0185  * @offset: Offset from where to read
0186  * Return:      Value at the offset
0187  */
0188 static u32 zynqmp_gqspi_read(struct zynqmp_qspi *xqspi, u32 offset)
0189 {
0190     return readl_relaxed(xqspi->regs + offset);
0191 }
0192 
0193 /**
0194  * zynqmp_gqspi_write - For GQSPI controller write operation
0195  * @xqspi:  Pointer to the zynqmp_qspi structure
0196  * @offset: Offset where to write
0197  * @val:    Value to be written
0198  */
0199 static inline void zynqmp_gqspi_write(struct zynqmp_qspi *xqspi, u32 offset,
0200                       u32 val)
0201 {
0202     writel_relaxed(val, (xqspi->regs + offset));
0203 }
0204 
0205 /**
0206  * zynqmp_gqspi_selectslave - For selection of slave device
0207  * @instanceptr:    Pointer to the zynqmp_qspi structure
0208  * @slavecs:    For chip select
0209  * @slavebus:   To check which bus is selected- upper or lower
0210  */
0211 static void zynqmp_gqspi_selectslave(struct zynqmp_qspi *instanceptr,
0212                      u8 slavecs, u8 slavebus)
0213 {
0214     /*
0215      * Bus and CS lines selected here will be updated in the instance and
0216      * used for subsequent GENFIFO entries during transfer.
0217      */
0218 
0219     /* Choose slave select line */
0220     switch (slavecs) {
0221     case GQSPI_SELECT_FLASH_CS_BOTH:
0222         instanceptr->genfifocs = GQSPI_GENFIFO_CS_LOWER |
0223             GQSPI_GENFIFO_CS_UPPER;
0224         break;
0225     case GQSPI_SELECT_FLASH_CS_UPPER:
0226         instanceptr->genfifocs = GQSPI_GENFIFO_CS_UPPER;
0227         break;
0228     case GQSPI_SELECT_FLASH_CS_LOWER:
0229         instanceptr->genfifocs = GQSPI_GENFIFO_CS_LOWER;
0230         break;
0231     default:
0232         dev_warn(instanceptr->dev, "Invalid slave select\n");
0233     }
0234 
0235     /* Choose the bus */
0236     switch (slavebus) {
0237     case GQSPI_SELECT_FLASH_BUS_BOTH:
0238         instanceptr->genfifobus = GQSPI_GENFIFO_BUS_LOWER |
0239             GQSPI_GENFIFO_BUS_UPPER;
0240         break;
0241     case GQSPI_SELECT_FLASH_BUS_UPPER:
0242         instanceptr->genfifobus = GQSPI_GENFIFO_BUS_UPPER;
0243         break;
0244     case GQSPI_SELECT_FLASH_BUS_LOWER:
0245         instanceptr->genfifobus = GQSPI_GENFIFO_BUS_LOWER;
0246         break;
0247     default:
0248         dev_warn(instanceptr->dev, "Invalid slave bus\n");
0249     }
0250 }
0251 
0252 /**
0253  * zynqmp_qspi_init_hw - Initialize the hardware
0254  * @xqspi:  Pointer to the zynqmp_qspi structure
0255  *
0256  * The default settings of the QSPI controller's configurable parameters on
0257  * reset are
0258  *  - Master mode
0259  *  - TX threshold set to 1
0260  *  - RX threshold set to 1
0261  *  - Flash memory interface mode enabled
0262  * This function performs the following actions
0263  *  - Disable and clear all the interrupts
0264  *  - Enable manual slave select
0265  *  - Enable manual start
0266  *  - Deselect all the chip select lines
0267  *  - Set the little endian mode of TX FIFO and
0268  *  - Enable the QSPI controller
0269  */
0270 static void zynqmp_qspi_init_hw(struct zynqmp_qspi *xqspi)
0271 {
0272     u32 config_reg;
0273 
0274     /* Select the GQSPI mode */
0275     zynqmp_gqspi_write(xqspi, GQSPI_SEL_OFST, GQSPI_SEL_MASK);
0276     /* Clear and disable interrupts */
0277     zynqmp_gqspi_write(xqspi, GQSPI_ISR_OFST,
0278                zynqmp_gqspi_read(xqspi, GQSPI_ISR_OFST) |
0279                GQSPI_ISR_WR_TO_CLR_MASK);
0280     /* Clear the DMA STS */
0281     zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_I_STS_OFST,
0282                zynqmp_gqspi_read(xqspi,
0283                          GQSPI_QSPIDMA_DST_I_STS_OFST));
0284     zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_STS_OFST,
0285                zynqmp_gqspi_read(xqspi,
0286                          GQSPI_QSPIDMA_DST_STS_OFST) |
0287                          GQSPI_QSPIDMA_DST_STS_WTC);
0288     zynqmp_gqspi_write(xqspi, GQSPI_IDR_OFST, GQSPI_IDR_ALL_MASK);
0289     zynqmp_gqspi_write(xqspi,
0290                GQSPI_QSPIDMA_DST_I_DIS_OFST,
0291                GQSPI_QSPIDMA_DST_INTR_ALL_MASK);
0292     /* Disable the GQSPI */
0293     zynqmp_gqspi_write(xqspi, GQSPI_EN_OFST, 0x0);
0294     config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST);
0295     config_reg &= ~GQSPI_CFG_MODE_EN_MASK;
0296     /* Manual start */
0297     config_reg |= GQSPI_CFG_GEN_FIFO_START_MODE_MASK;
0298     /* Little endian by default */
0299     config_reg &= ~GQSPI_CFG_ENDIAN_MASK;
0300     /* Disable poll time out */
0301     config_reg &= ~GQSPI_CFG_EN_POLL_TO_MASK;
0302     /* Set hold bit */
0303     config_reg |= GQSPI_CFG_WP_HOLD_MASK;
0304     /* Clear pre-scalar by default */
0305     config_reg &= ~GQSPI_CFG_BAUD_RATE_DIV_MASK;
0306     /* CPHA 0 */
0307     config_reg &= ~GQSPI_CFG_CLK_PHA_MASK;
0308     /* CPOL 0 */
0309     config_reg &= ~GQSPI_CFG_CLK_POL_MASK;
0310     zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg);
0311 
0312     /* Clear the TX and RX FIFO */
0313     zynqmp_gqspi_write(xqspi, GQSPI_FIFO_CTRL_OFST,
0314                GQSPI_FIFO_CTRL_RST_RX_FIFO_MASK |
0315                GQSPI_FIFO_CTRL_RST_TX_FIFO_MASK |
0316                GQSPI_FIFO_CTRL_RST_GEN_FIFO_MASK);
0317     /* Set by default to allow for high frequencies */
0318     zynqmp_gqspi_write(xqspi, GQSPI_LPBK_DLY_ADJ_OFST,
0319                zynqmp_gqspi_read(xqspi, GQSPI_LPBK_DLY_ADJ_OFST) |
0320                GQSPI_LPBK_DLY_ADJ_USE_LPBK_MASK);
0321     /* Reset thresholds */
0322     zynqmp_gqspi_write(xqspi, GQSPI_TX_THRESHOLD_OFST,
0323                GQSPI_TX_FIFO_THRESHOLD_RESET_VAL);
0324     zynqmp_gqspi_write(xqspi, GQSPI_RX_THRESHOLD_OFST,
0325                GQSPI_RX_FIFO_THRESHOLD);
0326     zynqmp_gqspi_write(xqspi, GQSPI_GF_THRESHOLD_OFST,
0327                GQSPI_GEN_FIFO_THRESHOLD_RESET_VAL);
0328     zynqmp_gqspi_selectslave(xqspi,
0329                  GQSPI_SELECT_FLASH_CS_LOWER,
0330                  GQSPI_SELECT_FLASH_BUS_LOWER);
0331     /* Initialize DMA */
0332     zynqmp_gqspi_write(xqspi,
0333                GQSPI_QSPIDMA_DST_CTRL_OFST,
0334                GQSPI_QSPIDMA_DST_CTRL_RESET_VAL);
0335 
0336     /* Enable the GQSPI */
0337     zynqmp_gqspi_write(xqspi, GQSPI_EN_OFST, GQSPI_EN_MASK);
0338 }
0339 
0340 /**
0341  * zynqmp_qspi_copy_read_data - Copy data to RX buffer
0342  * @xqspi:  Pointer to the zynqmp_qspi structure
0343  * @data:   The variable where data is stored
0344  * @size:   Number of bytes to be copied from data to RX buffer
0345  */
0346 static void zynqmp_qspi_copy_read_data(struct zynqmp_qspi *xqspi,
0347                        ulong data, u8 size)
0348 {
0349     memcpy(xqspi->rxbuf, &data, size);
0350     xqspi->rxbuf += size;
0351     xqspi->bytes_to_receive -= size;
0352 }
0353 
0354 /**
0355  * zynqmp_qspi_chipselect - Select or deselect the chip select line
0356  * @qspi:   Pointer to the spi_device structure
0357  * @is_high:    Select(0) or deselect (1) the chip select line
0358  */
0359 static void zynqmp_qspi_chipselect(struct spi_device *qspi, bool is_high)
0360 {
0361     struct zynqmp_qspi *xqspi = spi_master_get_devdata(qspi->master);
0362     ulong timeout;
0363     u32 genfifoentry = 0, statusreg;
0364 
0365     genfifoentry |= GQSPI_GENFIFO_MODE_SPI;
0366 
0367     if (!is_high) {
0368         if (!qspi->chip_select) {
0369             xqspi->genfifobus = GQSPI_GENFIFO_BUS_LOWER;
0370             xqspi->genfifocs = GQSPI_GENFIFO_CS_LOWER;
0371         } else {
0372             xqspi->genfifobus = GQSPI_GENFIFO_BUS_UPPER;
0373             xqspi->genfifocs = GQSPI_GENFIFO_CS_UPPER;
0374         }
0375         genfifoentry |= xqspi->genfifobus;
0376         genfifoentry |= xqspi->genfifocs;
0377         genfifoentry |= GQSPI_GENFIFO_CS_SETUP;
0378     } else {
0379         genfifoentry |= GQSPI_GENFIFO_CS_HOLD;
0380     }
0381 
0382     zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST, genfifoentry);
0383 
0384     /* Manually start the generic FIFO command */
0385     zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST,
0386                zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST) |
0387                GQSPI_CFG_START_GEN_FIFO_MASK);
0388 
0389     timeout = jiffies + msecs_to_jiffies(1000);
0390 
0391     /* Wait until the generic FIFO command is empty */
0392     do {
0393         statusreg = zynqmp_gqspi_read(xqspi, GQSPI_ISR_OFST);
0394 
0395         if ((statusreg & GQSPI_ISR_GENFIFOEMPTY_MASK) &&
0396             (statusreg & GQSPI_ISR_TXEMPTY_MASK))
0397             break;
0398         cpu_relax();
0399     } while (!time_after_eq(jiffies, timeout));
0400 
0401     if (time_after_eq(jiffies, timeout))
0402         dev_err(xqspi->dev, "Chip select timed out\n");
0403 }
0404 
0405 /**
0406  * zynqmp_qspi_selectspimode - Selects SPI mode - x1 or x2 or x4.
0407  * @xqspi:  xqspi is a pointer to the GQSPI instance
0408  * @spimode:    spimode - SPI or DUAL or QUAD.
0409  * Return:  Mask to set desired SPI mode in GENFIFO entry.
0410  */
0411 static inline u32 zynqmp_qspi_selectspimode(struct zynqmp_qspi *xqspi,
0412                         u8 spimode)
0413 {
0414     u32 mask = 0;
0415 
0416     switch (spimode) {
0417     case GQSPI_SELECT_MODE_DUALSPI:
0418         mask = GQSPI_GENFIFO_MODE_DUALSPI;
0419         break;
0420     case GQSPI_SELECT_MODE_QUADSPI:
0421         mask = GQSPI_GENFIFO_MODE_QUADSPI;
0422         break;
0423     case GQSPI_SELECT_MODE_SPI:
0424         mask = GQSPI_GENFIFO_MODE_SPI;
0425         break;
0426     default:
0427         dev_warn(xqspi->dev, "Invalid SPI mode\n");
0428     }
0429 
0430     return mask;
0431 }
0432 
0433 /**
0434  * zynqmp_qspi_config_op - Configure QSPI controller for specified
0435  *              transfer
0436  * @xqspi:  Pointer to the zynqmp_qspi structure
0437  * @qspi:   Pointer to the spi_device structure
0438  *
0439  * Sets the operational mode of QSPI controller for the next QSPI transfer and
0440  * sets the requested clock frequency.
0441  *
0442  * Return:  Always 0
0443  *
0444  * Note:
0445  *  If the requested frequency is not an exact match with what can be
0446  *  obtained using the pre-scalar value, the driver sets the clock
0447  *  frequency which is lower than the requested frequency (maximum lower)
0448  *  for the transfer.
0449  *
0450  *  If the requested frequency is higher or lower than that is supported
0451  *  by the QSPI controller the driver will set the highest or lowest
0452  *  frequency supported by controller.
0453  */
0454 static int zynqmp_qspi_config_op(struct zynqmp_qspi *xqspi,
0455                  struct spi_device *qspi)
0456 {
0457     ulong clk_rate;
0458     u32 config_reg, baud_rate_val = 0;
0459 
0460     /* Set the clock frequency */
0461     /* If req_hz == 0, default to lowest speed */
0462     clk_rate = clk_get_rate(xqspi->refclk);
0463 
0464     while ((baud_rate_val < GQSPI_BAUD_DIV_MAX) &&
0465            (clk_rate /
0466         (GQSPI_BAUD_DIV_SHIFT << baud_rate_val)) > qspi->max_speed_hz)
0467         baud_rate_val++;
0468 
0469     config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST);
0470 
0471     /* Set the QSPI clock phase and clock polarity */
0472     config_reg &= (~GQSPI_CFG_CLK_PHA_MASK) & (~GQSPI_CFG_CLK_POL_MASK);
0473 
0474     if (qspi->mode & SPI_CPHA)
0475         config_reg |= GQSPI_CFG_CLK_PHA_MASK;
0476     if (qspi->mode & SPI_CPOL)
0477         config_reg |= GQSPI_CFG_CLK_POL_MASK;
0478 
0479     config_reg &= ~GQSPI_CFG_BAUD_RATE_DIV_MASK;
0480     config_reg |= (baud_rate_val << GQSPI_CFG_BAUD_RATE_DIV_SHIFT);
0481     zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg);
0482     return 0;
0483 }
0484 
0485 /**
0486  * zynqmp_qspi_setup_op - Configure the QSPI controller
0487  * @qspi:   Pointer to the spi_device structure
0488  *
0489  * Sets the operational mode of QSPI controller for the next QSPI transfer,
0490  * baud rate and divisor value to setup the requested qspi clock.
0491  *
0492  * Return:  0 on success; error value otherwise.
0493  */
0494 static int zynqmp_qspi_setup_op(struct spi_device *qspi)
0495 {
0496     struct spi_controller *ctlr = qspi->master;
0497     struct zynqmp_qspi *xqspi = spi_controller_get_devdata(ctlr);
0498 
0499     if (ctlr->busy)
0500         return -EBUSY;
0501 
0502     zynqmp_gqspi_write(xqspi, GQSPI_EN_OFST, GQSPI_EN_MASK);
0503 
0504     return 0;
0505 }
0506 
0507 /**
0508  * zynqmp_qspi_filltxfifo - Fills the TX FIFO as long as there is room in
0509  *              the FIFO or the bytes required to be
0510  *              transmitted.
0511  * @xqspi:  Pointer to the zynqmp_qspi structure
0512  * @size:   Number of bytes to be copied from TX buffer to TX FIFO
0513  */
0514 static void zynqmp_qspi_filltxfifo(struct zynqmp_qspi *xqspi, int size)
0515 {
0516     u32 count = 0, intermediate;
0517 
0518     while ((xqspi->bytes_to_transfer > 0) && (count < size) && (xqspi->txbuf)) {
0519         if (xqspi->bytes_to_transfer >= 4) {
0520             memcpy(&intermediate, xqspi->txbuf, 4);
0521             xqspi->txbuf += 4;
0522             xqspi->bytes_to_transfer -= 4;
0523             count += 4;
0524         } else {
0525             memcpy(&intermediate, xqspi->txbuf,
0526                    xqspi->bytes_to_transfer);
0527             xqspi->txbuf += xqspi->bytes_to_transfer;
0528             xqspi->bytes_to_transfer = 0;
0529             count += xqspi->bytes_to_transfer;
0530         }
0531         zynqmp_gqspi_write(xqspi, GQSPI_TXD_OFST, intermediate);
0532     }
0533 }
0534 
0535 /**
0536  * zynqmp_qspi_readrxfifo - Fills the RX FIFO as long as there is room in
0537  *              the FIFO.
0538  * @xqspi:  Pointer to the zynqmp_qspi structure
0539  * @size:   Number of bytes to be copied from RX buffer to RX FIFO
0540  */
0541 static void zynqmp_qspi_readrxfifo(struct zynqmp_qspi *xqspi, u32 size)
0542 {
0543     ulong data;
0544     int count = 0;
0545 
0546     while ((count < size) && (xqspi->bytes_to_receive > 0)) {
0547         if (xqspi->bytes_to_receive >= 4) {
0548             (*(u32 *)xqspi->rxbuf) =
0549             zynqmp_gqspi_read(xqspi, GQSPI_RXD_OFST);
0550             xqspi->rxbuf += 4;
0551             xqspi->bytes_to_receive -= 4;
0552             count += 4;
0553         } else {
0554             data = zynqmp_gqspi_read(xqspi, GQSPI_RXD_OFST);
0555             count += xqspi->bytes_to_receive;
0556             zynqmp_qspi_copy_read_data(xqspi, data,
0557                            xqspi->bytes_to_receive);
0558             xqspi->bytes_to_receive = 0;
0559         }
0560     }
0561 }
0562 
0563 /**
0564  * zynqmp_qspi_fillgenfifo - Fills the GENFIFO.
0565  * @xqspi:  Pointer to the zynqmp_qspi structure
0566  * @nbits:  Transfer/Receive buswidth.
0567  * @genfifoentry:       Variable in which GENFIFO mask is saved
0568  */
0569 static void zynqmp_qspi_fillgenfifo(struct zynqmp_qspi *xqspi, u8 nbits,
0570                     u32 genfifoentry)
0571 {
0572     u32 transfer_len = 0;
0573 
0574     if (xqspi->txbuf) {
0575         genfifoentry &= ~GQSPI_GENFIFO_RX;
0576         genfifoentry |= GQSPI_GENFIFO_DATA_XFER;
0577         genfifoentry |= GQSPI_GENFIFO_TX;
0578         transfer_len = xqspi->bytes_to_transfer;
0579     } else if (xqspi->rxbuf) {
0580         genfifoentry &= ~GQSPI_GENFIFO_TX;
0581         genfifoentry |= GQSPI_GENFIFO_DATA_XFER;
0582         genfifoentry |= GQSPI_GENFIFO_RX;
0583         if (xqspi->mode == GQSPI_MODE_DMA)
0584             transfer_len = xqspi->dma_rx_bytes;
0585         else
0586             transfer_len = xqspi->bytes_to_receive;
0587     } else {
0588         /* Sending dummy circles here */
0589         genfifoentry &= ~(GQSPI_GENFIFO_TX | GQSPI_GENFIFO_RX);
0590         genfifoentry |= GQSPI_GENFIFO_DATA_XFER;
0591         transfer_len = xqspi->bytes_to_transfer;
0592     }
0593     genfifoentry |= zynqmp_qspi_selectspimode(xqspi, nbits);
0594     xqspi->genfifoentry = genfifoentry;
0595 
0596     if ((transfer_len) < GQSPI_GENFIFO_IMM_DATA_MASK) {
0597         genfifoentry &= ~GQSPI_GENFIFO_IMM_DATA_MASK;
0598         genfifoentry |= transfer_len;
0599         zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST, genfifoentry);
0600     } else {
0601         int tempcount = transfer_len;
0602         u32 exponent = 8;   /* 2^8 = 256 */
0603         u8 imm_data = tempcount & 0xFF;
0604 
0605         tempcount &= ~(tempcount & 0xFF);
0606         /* Immediate entry */
0607         if (tempcount != 0) {
0608             /* Exponent entries */
0609             genfifoentry |= GQSPI_GENFIFO_EXP;
0610             while (tempcount != 0) {
0611                 if (tempcount & GQSPI_GENFIFO_EXP_START) {
0612                     genfifoentry &=
0613                         ~GQSPI_GENFIFO_IMM_DATA_MASK;
0614                     genfifoentry |= exponent;
0615                     zynqmp_gqspi_write(xqspi,
0616                                GQSPI_GEN_FIFO_OFST,
0617                                genfifoentry);
0618                 }
0619                 tempcount = tempcount >> 1;
0620                 exponent++;
0621             }
0622         }
0623         if (imm_data != 0) {
0624             genfifoentry &= ~GQSPI_GENFIFO_EXP;
0625             genfifoentry &= ~GQSPI_GENFIFO_IMM_DATA_MASK;
0626             genfifoentry |= (u8)(imm_data & 0xFF);
0627             zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST,
0628                        genfifoentry);
0629         }
0630     }
0631     if (xqspi->mode == GQSPI_MODE_IO && xqspi->rxbuf) {
0632         /* Dummy generic FIFO entry */
0633         zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST, 0x0);
0634     }
0635 }
0636 
0637 /**
0638  * zynqmp_process_dma_irq - Handler for DMA done interrupt of QSPI
0639  *              controller
0640  * @xqspi:  zynqmp_qspi instance pointer
0641  *
0642  * This function handles DMA interrupt only.
0643  */
0644 static void zynqmp_process_dma_irq(struct zynqmp_qspi *xqspi)
0645 {
0646     u32 config_reg, genfifoentry;
0647 
0648     dma_unmap_single(xqspi->dev, xqspi->dma_addr,
0649              xqspi->dma_rx_bytes, DMA_FROM_DEVICE);
0650     xqspi->rxbuf += xqspi->dma_rx_bytes;
0651     xqspi->bytes_to_receive -= xqspi->dma_rx_bytes;
0652     xqspi->dma_rx_bytes = 0;
0653 
0654     /* Disabling the DMA interrupts */
0655     zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_I_DIS_OFST,
0656                GQSPI_QSPIDMA_DST_I_EN_DONE_MASK);
0657 
0658     if (xqspi->bytes_to_receive > 0) {
0659         /* Switch to IO mode,for remaining bytes to receive */
0660         config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST);
0661         config_reg &= ~GQSPI_CFG_MODE_EN_MASK;
0662         zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg);
0663 
0664         /* Initiate the transfer of remaining bytes */
0665         genfifoentry = xqspi->genfifoentry;
0666         genfifoentry |= xqspi->bytes_to_receive;
0667         zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST, genfifoentry);
0668 
0669         /* Dummy generic FIFO entry */
0670         zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST, 0x0);
0671 
0672         /* Manual start */
0673         zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST,
0674                    (zynqmp_gqspi_read(xqspi,
0675                               GQSPI_CONFIG_OFST) |
0676                    GQSPI_CFG_START_GEN_FIFO_MASK));
0677 
0678         /* Enable the RX interrupts for IO mode */
0679         zynqmp_gqspi_write(xqspi, GQSPI_IER_OFST,
0680                    GQSPI_IER_GENFIFOEMPTY_MASK |
0681                    GQSPI_IER_RXNEMPTY_MASK |
0682                    GQSPI_IER_RXEMPTY_MASK);
0683     }
0684 }
0685 
0686 /**
0687  * zynqmp_qspi_irq - Interrupt service routine of the QSPI controller
0688  * @irq:    IRQ number
0689  * @dev_id: Pointer to the xqspi structure
0690  *
0691  * This function handles TX empty only.
0692  * On TX empty interrupt this function reads the received data from RX FIFO
0693  * and fills the TX FIFO if there is any data remaining to be transferred.
0694  *
0695  * Return:  IRQ_HANDLED when interrupt is handled
0696  *      IRQ_NONE otherwise.
0697  */
0698 static irqreturn_t zynqmp_qspi_irq(int irq, void *dev_id)
0699 {
0700     struct zynqmp_qspi *xqspi = (struct zynqmp_qspi *)dev_id;
0701     irqreturn_t ret = IRQ_NONE;
0702     u32 status, mask, dma_status = 0;
0703 
0704     status = zynqmp_gqspi_read(xqspi, GQSPI_ISR_OFST);
0705     zynqmp_gqspi_write(xqspi, GQSPI_ISR_OFST, status);
0706     mask = (status & ~(zynqmp_gqspi_read(xqspi, GQSPI_IMASK_OFST)));
0707 
0708     /* Read and clear DMA status */
0709     if (xqspi->mode == GQSPI_MODE_DMA) {
0710         dma_status =
0711             zynqmp_gqspi_read(xqspi, GQSPI_QSPIDMA_DST_I_STS_OFST);
0712         zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_I_STS_OFST,
0713                    dma_status);
0714     }
0715 
0716     if (mask & GQSPI_ISR_TXNOT_FULL_MASK) {
0717         zynqmp_qspi_filltxfifo(xqspi, GQSPI_TX_FIFO_FILL);
0718         ret = IRQ_HANDLED;
0719     }
0720 
0721     if (dma_status & GQSPI_QSPIDMA_DST_I_STS_DONE_MASK) {
0722         zynqmp_process_dma_irq(xqspi);
0723         ret = IRQ_HANDLED;
0724     } else if (!(mask & GQSPI_IER_RXEMPTY_MASK) &&
0725             (mask & GQSPI_IER_GENFIFOEMPTY_MASK)) {
0726         zynqmp_qspi_readrxfifo(xqspi, GQSPI_RX_FIFO_FILL);
0727         ret = IRQ_HANDLED;
0728     }
0729 
0730     if (xqspi->bytes_to_receive == 0 && xqspi->bytes_to_transfer == 0 &&
0731         ((status & GQSPI_IRQ_MASK) == GQSPI_IRQ_MASK)) {
0732         zynqmp_gqspi_write(xqspi, GQSPI_IDR_OFST, GQSPI_ISR_IDR_MASK);
0733         complete(&xqspi->data_completion);
0734         ret = IRQ_HANDLED;
0735     }
0736     return ret;
0737 }
0738 
0739 /**
0740  * zynqmp_qspi_setuprxdma - This function sets up the RX DMA operation
0741  * @xqspi:  xqspi is a pointer to the GQSPI instance.
0742  */
0743 static int zynqmp_qspi_setuprxdma(struct zynqmp_qspi *xqspi)
0744 {
0745     u32 rx_bytes, rx_rem, config_reg;
0746     dma_addr_t addr;
0747     u64 dma_align =  (u64)(uintptr_t)xqspi->rxbuf;
0748 
0749     if (xqspi->bytes_to_receive < 8 ||
0750         ((dma_align & GQSPI_DMA_UNALIGN) != 0x0)) {
0751         /* Setting to IO mode */
0752         config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST);
0753         config_reg &= ~GQSPI_CFG_MODE_EN_MASK;
0754         zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg);
0755         xqspi->mode = GQSPI_MODE_IO;
0756         xqspi->dma_rx_bytes = 0;
0757         return 0;
0758     }
0759 
0760     rx_rem = xqspi->bytes_to_receive % 4;
0761     rx_bytes = (xqspi->bytes_to_receive - rx_rem);
0762 
0763     addr = dma_map_single(xqspi->dev, (void *)xqspi->rxbuf,
0764                   rx_bytes, DMA_FROM_DEVICE);
0765     if (dma_mapping_error(xqspi->dev, addr)) {
0766         dev_err(xqspi->dev, "ERR:rxdma:memory not mapped\n");
0767         return -ENOMEM;
0768     }
0769 
0770     xqspi->dma_rx_bytes = rx_bytes;
0771     xqspi->dma_addr = addr;
0772     zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_ADDR_OFST,
0773                (u32)(addr & 0xffffffff));
0774     addr = ((addr >> 16) >> 16);
0775     zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_ADDR_MSB_OFST,
0776                ((u32)addr) & 0xfff);
0777 
0778     /* Enabling the DMA mode */
0779     config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST);
0780     config_reg &= ~GQSPI_CFG_MODE_EN_MASK;
0781     config_reg |= GQSPI_CFG_MODE_EN_DMA_MASK;
0782     zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg);
0783 
0784     /* Switch to DMA mode */
0785     xqspi->mode = GQSPI_MODE_DMA;
0786 
0787     /* Write the number of bytes to transfer */
0788     zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_SIZE_OFST, rx_bytes);
0789 
0790     return 0;
0791 }
0792 
0793 /**
0794  * zynqmp_qspi_write_op - This function sets up the GENFIFO entries,
0795  *          TX FIFO, and fills the TX FIFO with as many
0796  *          bytes as possible.
0797  * @xqspi:  Pointer to the GQSPI instance.
0798  * @tx_nbits:   Transfer buswidth.
0799  * @genfifoentry:   Variable in which GENFIFO mask is returned
0800  *          to calling function
0801  */
0802 static void zynqmp_qspi_write_op(struct zynqmp_qspi *xqspi, u8 tx_nbits,
0803                  u32 genfifoentry)
0804 {
0805     u32 config_reg;
0806 
0807     zynqmp_qspi_fillgenfifo(xqspi, tx_nbits, genfifoentry);
0808     zynqmp_qspi_filltxfifo(xqspi, GQSPI_TXD_DEPTH);
0809     if (xqspi->mode == GQSPI_MODE_DMA) {
0810         config_reg = zynqmp_gqspi_read(xqspi,
0811                            GQSPI_CONFIG_OFST);
0812         config_reg &= ~GQSPI_CFG_MODE_EN_MASK;
0813         zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST,
0814                    config_reg);
0815         xqspi->mode = GQSPI_MODE_IO;
0816     }
0817 }
0818 
0819 /**
0820  * zynqmp_qspi_read_op - This function sets up the GENFIFO entries and
0821  *              RX DMA operation.
0822  * @xqspi:  xqspi is a pointer to the GQSPI instance.
0823  * @rx_nbits:   Receive buswidth.
0824  * @genfifoentry:   genfifoentry is pointer to the variable in which
0825  *          GENFIFO mask is returned to calling function
0826  */
0827 static int zynqmp_qspi_read_op(struct zynqmp_qspi *xqspi, u8 rx_nbits,
0828                 u32 genfifoentry)
0829 {
0830     int ret;
0831 
0832     ret = zynqmp_qspi_setuprxdma(xqspi);
0833     if (ret)
0834         return ret;
0835     zynqmp_qspi_fillgenfifo(xqspi, rx_nbits, genfifoentry);
0836 
0837     return 0;
0838 }
0839 
0840 /**
0841  * zynqmp_qspi_suspend - Suspend method for the QSPI driver
0842  * @dev:    Address of the platform_device structure
0843  *
0844  * This function stops the QSPI driver queue and disables the QSPI controller
0845  *
0846  * Return:  Always 0
0847  */
0848 static int __maybe_unused zynqmp_qspi_suspend(struct device *dev)
0849 {
0850     struct zynqmp_qspi *xqspi = dev_get_drvdata(dev);
0851     struct spi_controller *ctlr = xqspi->ctlr;
0852     int ret;
0853 
0854     ret = spi_controller_suspend(ctlr);
0855     if (ret)
0856         return ret;
0857 
0858     zynqmp_gqspi_write(xqspi, GQSPI_EN_OFST, 0x0);
0859 
0860     return 0;
0861 }
0862 
0863 /**
0864  * zynqmp_qspi_resume - Resume method for the QSPI driver
0865  * @dev:    Address of the platform_device structure
0866  *
0867  * The function starts the QSPI driver queue and initializes the QSPI
0868  * controller
0869  *
0870  * Return:  0 on success; error value otherwise
0871  */
0872 static int __maybe_unused zynqmp_qspi_resume(struct device *dev)
0873 {
0874     struct zynqmp_qspi *xqspi = dev_get_drvdata(dev);
0875     struct spi_controller *ctlr = xqspi->ctlr;
0876 
0877     zynqmp_gqspi_write(xqspi, GQSPI_EN_OFST, GQSPI_EN_MASK);
0878 
0879     spi_controller_resume(ctlr);
0880 
0881     return 0;
0882 }
0883 
0884 /**
0885  * zynqmp_runtime_suspend - Runtime suspend method for the SPI driver
0886  * @dev:    Address of the platform_device structure
0887  *
0888  * This function disables the clocks
0889  *
0890  * Return:  Always 0
0891  */
0892 static int __maybe_unused zynqmp_runtime_suspend(struct device *dev)
0893 {
0894     struct zynqmp_qspi *xqspi = dev_get_drvdata(dev);
0895 
0896     clk_disable_unprepare(xqspi->refclk);
0897     clk_disable_unprepare(xqspi->pclk);
0898 
0899     return 0;
0900 }
0901 
0902 /**
0903  * zynqmp_runtime_resume - Runtime resume method for the SPI driver
0904  * @dev:    Address of the platform_device structure
0905  *
0906  * This function enables the clocks
0907  *
0908  * Return:  0 on success and error value on error
0909  */
0910 static int __maybe_unused zynqmp_runtime_resume(struct device *dev)
0911 {
0912     struct zynqmp_qspi *xqspi = dev_get_drvdata(dev);
0913     int ret;
0914 
0915     ret = clk_prepare_enable(xqspi->pclk);
0916     if (ret) {
0917         dev_err(dev, "Cannot enable APB clock.\n");
0918         return ret;
0919     }
0920 
0921     ret = clk_prepare_enable(xqspi->refclk);
0922     if (ret) {
0923         dev_err(dev, "Cannot enable device clock.\n");
0924         clk_disable_unprepare(xqspi->pclk);
0925         return ret;
0926     }
0927 
0928     return 0;
0929 }
0930 
0931 /**
0932  * zynqmp_qspi_exec_op() - Initiates the QSPI transfer
0933  * @mem: The SPI memory
0934  * @op: The memory operation to execute
0935  *
0936  * Executes a memory operation.
0937  *
0938  * This function first selects the chip and starts the memory operation.
0939  *
0940  * Return: 0 in case of success, a negative error code otherwise.
0941  */
0942 static int zynqmp_qspi_exec_op(struct spi_mem *mem,
0943                    const struct spi_mem_op *op)
0944 {
0945     struct zynqmp_qspi *xqspi = spi_controller_get_devdata
0946                     (mem->spi->master);
0947     int err = 0, i;
0948     u32 genfifoentry = 0;
0949     u16 opcode = op->cmd.opcode;
0950     u64 opaddr;
0951 
0952     dev_dbg(xqspi->dev, "cmd:%#x mode:%d.%d.%d.%d\n",
0953         op->cmd.opcode, op->cmd.buswidth, op->addr.buswidth,
0954         op->dummy.buswidth, op->data.buswidth);
0955 
0956     mutex_lock(&xqspi->op_lock);
0957     zynqmp_qspi_config_op(xqspi, mem->spi);
0958     zynqmp_qspi_chipselect(mem->spi, false);
0959     genfifoentry |= xqspi->genfifocs;
0960     genfifoentry |= xqspi->genfifobus;
0961 
0962     if (op->cmd.opcode) {
0963         reinit_completion(&xqspi->data_completion);
0964         xqspi->txbuf = &opcode;
0965         xqspi->rxbuf = NULL;
0966         xqspi->bytes_to_transfer = op->cmd.nbytes;
0967         xqspi->bytes_to_receive = 0;
0968         zynqmp_qspi_write_op(xqspi, op->cmd.buswidth, genfifoentry);
0969         zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST,
0970                    zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST) |
0971                    GQSPI_CFG_START_GEN_FIFO_MASK);
0972         zynqmp_gqspi_write(xqspi, GQSPI_IER_OFST,
0973                    GQSPI_IER_GENFIFOEMPTY_MASK |
0974                    GQSPI_IER_TXNOT_FULL_MASK);
0975         if (!wait_for_completion_timeout
0976             (&xqspi->data_completion, msecs_to_jiffies(1000))) {
0977             err = -ETIMEDOUT;
0978             goto return_err;
0979         }
0980     }
0981 
0982     if (op->addr.nbytes) {
0983         xqspi->txbuf = &opaddr;
0984         for (i = 0; i < op->addr.nbytes; i++) {
0985             *(((u8 *)xqspi->txbuf) + i) = op->addr.val >>
0986                     (8 * (op->addr.nbytes - i - 1));
0987         }
0988 
0989         reinit_completion(&xqspi->data_completion);
0990         xqspi->rxbuf = NULL;
0991         xqspi->bytes_to_transfer = op->addr.nbytes;
0992         xqspi->bytes_to_receive = 0;
0993         zynqmp_qspi_write_op(xqspi, op->addr.buswidth, genfifoentry);
0994         zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST,
0995                    zynqmp_gqspi_read(xqspi,
0996                              GQSPI_CONFIG_OFST) |
0997                    GQSPI_CFG_START_GEN_FIFO_MASK);
0998         zynqmp_gqspi_write(xqspi, GQSPI_IER_OFST,
0999                    GQSPI_IER_TXEMPTY_MASK |
1000                    GQSPI_IER_GENFIFOEMPTY_MASK |
1001                    GQSPI_IER_TXNOT_FULL_MASK);
1002         if (!wait_for_completion_timeout
1003             (&xqspi->data_completion, msecs_to_jiffies(1000))) {
1004             err = -ETIMEDOUT;
1005             goto return_err;
1006         }
1007     }
1008 
1009     if (op->dummy.nbytes) {
1010         xqspi->txbuf = NULL;
1011         xqspi->rxbuf = NULL;
1012         /*
1013          * xqspi->bytes_to_transfer here represents the dummy circles
1014          * which need to be sent.
1015          */
1016         xqspi->bytes_to_transfer = op->dummy.nbytes * 8 / op->dummy.buswidth;
1017         xqspi->bytes_to_receive = 0;
1018         /*
1019          * Using op->data.buswidth instead of op->dummy.buswidth here because
1020          * we need to use it to configure the correct SPI mode.
1021          */
1022         zynqmp_qspi_write_op(xqspi, op->data.buswidth,
1023                      genfifoentry);
1024         zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST,
1025                    zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST) |
1026                    GQSPI_CFG_START_GEN_FIFO_MASK);
1027     }
1028 
1029     if (op->data.nbytes) {
1030         reinit_completion(&xqspi->data_completion);
1031         if (op->data.dir == SPI_MEM_DATA_OUT) {
1032             xqspi->txbuf = (u8 *)op->data.buf.out;
1033             xqspi->rxbuf = NULL;
1034             xqspi->bytes_to_transfer = op->data.nbytes;
1035             xqspi->bytes_to_receive = 0;
1036             zynqmp_qspi_write_op(xqspi, op->data.buswidth,
1037                          genfifoentry);
1038             zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST,
1039                        zynqmp_gqspi_read
1040                        (xqspi, GQSPI_CONFIG_OFST) |
1041                        GQSPI_CFG_START_GEN_FIFO_MASK);
1042             zynqmp_gqspi_write(xqspi, GQSPI_IER_OFST,
1043                        GQSPI_IER_TXEMPTY_MASK |
1044                        GQSPI_IER_GENFIFOEMPTY_MASK |
1045                        GQSPI_IER_TXNOT_FULL_MASK);
1046         } else {
1047             xqspi->txbuf = NULL;
1048             xqspi->rxbuf = (u8 *)op->data.buf.in;
1049             xqspi->bytes_to_receive = op->data.nbytes;
1050             xqspi->bytes_to_transfer = 0;
1051             err = zynqmp_qspi_read_op(xqspi, op->data.buswidth,
1052                         genfifoentry);
1053             if (err)
1054                 goto return_err;
1055 
1056             zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST,
1057                        zynqmp_gqspi_read
1058                        (xqspi, GQSPI_CONFIG_OFST) |
1059                        GQSPI_CFG_START_GEN_FIFO_MASK);
1060             if (xqspi->mode == GQSPI_MODE_DMA) {
1061                 zynqmp_gqspi_write
1062                     (xqspi, GQSPI_QSPIDMA_DST_I_EN_OFST,
1063                      GQSPI_QSPIDMA_DST_I_EN_DONE_MASK);
1064             } else {
1065                 zynqmp_gqspi_write(xqspi, GQSPI_IER_OFST,
1066                            GQSPI_IER_GENFIFOEMPTY_MASK |
1067                            GQSPI_IER_RXNEMPTY_MASK |
1068                            GQSPI_IER_RXEMPTY_MASK);
1069             }
1070         }
1071         if (!wait_for_completion_timeout
1072             (&xqspi->data_completion, msecs_to_jiffies(1000)))
1073             err = -ETIMEDOUT;
1074     }
1075 
1076 return_err:
1077 
1078     zynqmp_qspi_chipselect(mem->spi, true);
1079     mutex_unlock(&xqspi->op_lock);
1080 
1081     return err;
1082 }
1083 
1084 static const struct dev_pm_ops zynqmp_qspi_dev_pm_ops = {
1085     SET_RUNTIME_PM_OPS(zynqmp_runtime_suspend,
1086                zynqmp_runtime_resume, NULL)
1087     SET_SYSTEM_SLEEP_PM_OPS(zynqmp_qspi_suspend, zynqmp_qspi_resume)
1088 };
1089 
1090 static const struct spi_controller_mem_ops zynqmp_qspi_mem_ops = {
1091     .exec_op = zynqmp_qspi_exec_op,
1092 };
1093 
1094 /**
1095  * zynqmp_qspi_probe - Probe method for the QSPI driver
1096  * @pdev:   Pointer to the platform_device structure
1097  *
1098  * This function initializes the driver data structures and the hardware.
1099  *
1100  * Return:  0 on success; error value otherwise
1101  */
1102 static int zynqmp_qspi_probe(struct platform_device *pdev)
1103 {
1104     int ret = 0;
1105     struct spi_controller *ctlr;
1106     struct zynqmp_qspi *xqspi;
1107     struct device *dev = &pdev->dev;
1108     struct device_node *np = dev->of_node;
1109     u32 num_cs;
1110 
1111     ctlr = spi_alloc_master(&pdev->dev, sizeof(*xqspi));
1112     if (!ctlr)
1113         return -ENOMEM;
1114 
1115     xqspi = spi_controller_get_devdata(ctlr);
1116     xqspi->dev = dev;
1117     xqspi->ctlr = ctlr;
1118     platform_set_drvdata(pdev, xqspi);
1119 
1120     xqspi->regs = devm_platform_ioremap_resource(pdev, 0);
1121     if (IS_ERR(xqspi->regs)) {
1122         ret = PTR_ERR(xqspi->regs);
1123         goto remove_master;
1124     }
1125 
1126     xqspi->pclk = devm_clk_get(&pdev->dev, "pclk");
1127     if (IS_ERR(xqspi->pclk)) {
1128         dev_err(dev, "pclk clock not found.\n");
1129         ret = PTR_ERR(xqspi->pclk);
1130         goto remove_master;
1131     }
1132 
1133     xqspi->refclk = devm_clk_get(&pdev->dev, "ref_clk");
1134     if (IS_ERR(xqspi->refclk)) {
1135         dev_err(dev, "ref_clk clock not found.\n");
1136         ret = PTR_ERR(xqspi->refclk);
1137         goto remove_master;
1138     }
1139 
1140     ret = clk_prepare_enable(xqspi->pclk);
1141     if (ret) {
1142         dev_err(dev, "Unable to enable APB clock.\n");
1143         goto remove_master;
1144     }
1145 
1146     ret = clk_prepare_enable(xqspi->refclk);
1147     if (ret) {
1148         dev_err(dev, "Unable to enable device clock.\n");
1149         goto clk_dis_pclk;
1150     }
1151 
1152     init_completion(&xqspi->data_completion);
1153 
1154     mutex_init(&xqspi->op_lock);
1155 
1156     pm_runtime_use_autosuspend(&pdev->dev);
1157     pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT);
1158     pm_runtime_set_active(&pdev->dev);
1159     pm_runtime_enable(&pdev->dev);
1160 
1161     ret = pm_runtime_get_sync(&pdev->dev);
1162     if (ret < 0) {
1163         dev_err(&pdev->dev, "Failed to pm_runtime_get_sync: %d\n", ret);
1164         goto clk_dis_all;
1165     }
1166 
1167     /* QSPI controller initializations */
1168     zynqmp_qspi_init_hw(xqspi);
1169 
1170     xqspi->irq = platform_get_irq(pdev, 0);
1171     if (xqspi->irq <= 0) {
1172         ret = -ENXIO;
1173         goto clk_dis_all;
1174     }
1175     ret = devm_request_irq(&pdev->dev, xqspi->irq, zynqmp_qspi_irq,
1176                    0, pdev->name, xqspi);
1177     if (ret != 0) {
1178         ret = -ENXIO;
1179         dev_err(dev, "request_irq failed\n");
1180         goto clk_dis_all;
1181     }
1182 
1183     ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(44));
1184     if (ret)
1185         goto clk_dis_all;
1186 
1187     ret = of_property_read_u32(np, "num-cs", &num_cs);
1188     if (ret < 0) {
1189         ctlr->num_chipselect = GQSPI_DEFAULT_NUM_CS;
1190     } else if (num_cs > GQSPI_MAX_NUM_CS) {
1191         ret = -EINVAL;
1192         dev_err(&pdev->dev, "only %d chip selects are available\n",
1193             GQSPI_MAX_NUM_CS);
1194         goto clk_dis_all;
1195     } else {
1196         ctlr->num_chipselect = num_cs;
1197     }
1198 
1199     ctlr->bits_per_word_mask = SPI_BPW_MASK(8);
1200     ctlr->mem_ops = &zynqmp_qspi_mem_ops;
1201     ctlr->setup = zynqmp_qspi_setup_op;
1202     ctlr->max_speed_hz = clk_get_rate(xqspi->refclk) / 2;
1203     ctlr->bits_per_word_mask = SPI_BPW_MASK(8);
1204     ctlr->mode_bits = SPI_CPOL | SPI_CPHA | SPI_RX_DUAL | SPI_RX_QUAD |
1205                 SPI_TX_DUAL | SPI_TX_QUAD;
1206     ctlr->dev.of_node = np;
1207     ctlr->auto_runtime_pm = true;
1208 
1209     ret = devm_spi_register_controller(&pdev->dev, ctlr);
1210     if (ret) {
1211         dev_err(&pdev->dev, "spi_register_controller failed\n");
1212         goto clk_dis_all;
1213     }
1214 
1215     pm_runtime_mark_last_busy(&pdev->dev);
1216     pm_runtime_put_autosuspend(&pdev->dev);
1217 
1218     return 0;
1219 
1220 clk_dis_all:
1221     pm_runtime_put_sync(&pdev->dev);
1222     pm_runtime_set_suspended(&pdev->dev);
1223     pm_runtime_disable(&pdev->dev);
1224     clk_disable_unprepare(xqspi->refclk);
1225 clk_dis_pclk:
1226     clk_disable_unprepare(xqspi->pclk);
1227 remove_master:
1228     spi_controller_put(ctlr);
1229 
1230     return ret;
1231 }
1232 
1233 /**
1234  * zynqmp_qspi_remove - Remove method for the QSPI driver
1235  * @pdev:   Pointer to the platform_device structure
1236  *
1237  * This function is called if a device is physically removed from the system or
1238  * if the driver module is being unloaded. It frees all resources allocated to
1239  * the device.
1240  *
1241  * Return:  0 Always
1242  */
1243 static int zynqmp_qspi_remove(struct platform_device *pdev)
1244 {
1245     struct zynqmp_qspi *xqspi = platform_get_drvdata(pdev);
1246 
1247     zynqmp_gqspi_write(xqspi, GQSPI_EN_OFST, 0x0);
1248     clk_disable_unprepare(xqspi->refclk);
1249     clk_disable_unprepare(xqspi->pclk);
1250     pm_runtime_set_suspended(&pdev->dev);
1251     pm_runtime_disable(&pdev->dev);
1252 
1253     return 0;
1254 }
1255 
1256 static const struct of_device_id zynqmp_qspi_of_match[] = {
1257     { .compatible = "xlnx,zynqmp-qspi-1.0", },
1258     { /* End of table */ }
1259 };
1260 
1261 MODULE_DEVICE_TABLE(of, zynqmp_qspi_of_match);
1262 
1263 static struct platform_driver zynqmp_qspi_driver = {
1264     .probe = zynqmp_qspi_probe,
1265     .remove = zynqmp_qspi_remove,
1266     .driver = {
1267         .name = "zynqmp-qspi",
1268         .of_match_table = zynqmp_qspi_of_match,
1269         .pm = &zynqmp_qspi_dev_pm_ops,
1270     },
1271 };
1272 
1273 module_platform_driver(zynqmp_qspi_driver);
1274 
1275 MODULE_AUTHOR("Xilinx, Inc.");
1276 MODULE_DESCRIPTION("Xilinx Zynqmp QSPI driver");
1277 MODULE_LICENSE("GPL");
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