drivers/spi/spi-xlp.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (C) 2003-2015 Broadcom Corporation
0004  * All Rights Reserved
0005  */
0006 #include <linux/acpi.h>
0007 #include <linux/clk.h>
0008 #include <linux/kernel.h>
0009 #include <linux/module.h>
0010 #include <linux/platform_device.h>
0011 #include <linux/spi/spi.h>
0012 #include <linux/interrupt.h>
0013
0014 /* SPI Configuration Register */
0015 #define XLP_SPI_CONFIG          0x00
0016 #define XLP_SPI_CPHA            BIT(0)
0017 #define XLP_SPI_CPOL            BIT(1)
0018 #define XLP_SPI_CS_POL          BIT(2)
0019 #define XLP_SPI_TXMISO_EN       BIT(3)
0020 #define XLP_SPI_TXMOSI_EN       BIT(4)
0021 #define XLP_SPI_RXMISO_EN       BIT(5)
0022 #define XLP_SPI_CS_LSBFE        BIT(10)
0023 #define XLP_SPI_RXCAP_EN        BIT(11)
0024
0025 /* SPI Frequency Divider Register */
0026 #define XLP_SPI_FDIV            0x04
0027
0028 /* SPI Command Register */
0029 #define XLP_SPI_CMD         0x08
0030 #define XLP_SPI_CMD_IDLE_MASK       0x0
0031 #define XLP_SPI_CMD_TX_MASK     0x1
0032 #define XLP_SPI_CMD_RX_MASK     0x2
0033 #define XLP_SPI_CMD_TXRX_MASK       0x3
0034 #define XLP_SPI_CMD_CONT        BIT(4)
0035 #define XLP_SPI_XFR_BITCNT_SHIFT    16
0036
0037 /* SPI Status Register */
0038 #define XLP_SPI_STATUS          0x0c
0039 #define XLP_SPI_XFR_PENDING     BIT(0)
0040 #define XLP_SPI_XFR_DONE        BIT(1)
0041 #define XLP_SPI_TX_INT          BIT(2)
0042 #define XLP_SPI_RX_INT          BIT(3)
0043 #define XLP_SPI_TX_UF           BIT(4)
0044 #define XLP_SPI_RX_OF           BIT(5)
0045 #define XLP_SPI_STAT_MASK       0x3f
0046
0047 /* SPI Interrupt Enable Register */
0048 #define XLP_SPI_INTR_EN         0x10
0049 #define XLP_SPI_INTR_DONE       BIT(0)
0050 #define XLP_SPI_INTR_TXTH       BIT(1)
0051 #define XLP_SPI_INTR_RXTH       BIT(2)
0052 #define XLP_SPI_INTR_TXUF       BIT(3)
0053 #define XLP_SPI_INTR_RXOF       BIT(4)
0054
0055 /* SPI FIFO Threshold Register */
0056 #define XLP_SPI_FIFO_THRESH     0x14
0057
0058 /* SPI FIFO Word Count Register */
0059 #define XLP_SPI_FIFO_WCNT       0x18
0060 #define XLP_SPI_RXFIFO_WCNT_MASK    0xf
0061 #define XLP_SPI_TXFIFO_WCNT_MASK    0xf0
0062 #define XLP_SPI_TXFIFO_WCNT_SHIFT   4
0063
0064 /* SPI Transmit Data FIFO Register */
0065 #define XLP_SPI_TXDATA_FIFO     0x1c
0066
0067 /* SPI Receive Data FIFO Register */
0068 #define XLP_SPI_RXDATA_FIFO     0x20
0069
0070 /* SPI System Control Register */
0071 #define XLP_SPI_SYSCTRL         0x100
0072 #define XLP_SPI_SYS_RESET       BIT(0)
0073 #define XLP_SPI_SYS_CLKDIS      BIT(1)
0074 #define XLP_SPI_SYS_PMEN        BIT(8)
0075
0076 #define SPI_CS_OFFSET           0x40
0077 #define XLP_SPI_TXRXTH          0x80
0078 #define XLP_SPI_FIFO_SIZE       8
0079 #define XLP_SPI_MAX_CS          4
0080 #define XLP_SPI_DEFAULT_FREQ        133333333
0081 #define XLP_SPI_FDIV_MIN        4
0082 #define XLP_SPI_FDIV_MAX        65535
0083 /*
0084  * SPI can transfer only 28 bytes properly at a time. So split the
0085  * transfer into 28 bytes size.
0086  */
0087 #define XLP_SPI_XFER_SIZE       28
0088
0089 struct xlp_spi_priv {
0090     struct device       dev;        /* device structure */
0091     void __iomem        *base;      /* spi registers base address */
0092     const u8        *tx_buf;    /* tx data buffer */
0093     u8          *rx_buf;    /* rx data buffer */
0094     int         tx_len;     /* tx xfer length */
0095     int         rx_len;     /* rx xfer length */
0096     int         txerrors;   /* TXFIFO underflow count */
0097     int         rxerrors;   /* RXFIFO overflow count */
0098     int         cs;     /* slave device chip select */
0099     u32         spi_clk;    /* spi clock frequency */
0100     bool            cmd_cont;   /* cs active */
0101     struct completion   done;       /* completion notification */
0102 };
0103
0104 static inline u32 xlp_spi_reg_read(struct xlp_spi_priv *priv,
0105                 int cs, int regoff)
0106 {
0107     return readl(priv->base + regoff + cs * SPI_CS_OFFSET);
0108 }
0109
0110 static inline void xlp_spi_reg_write(struct xlp_spi_priv *priv, int cs,
0111                 int regoff, u32 val)
0112 {
0113     writel(val, priv->base + regoff + cs * SPI_CS_OFFSET);
0114 }
0115
0116 static inline void xlp_spi_sysctl_write(struct xlp_spi_priv *priv,
0117                 int regoff, u32 val)
0118 {
0119     writel(val, priv->base + regoff);
0120 }
0121
0122 /*
0123  * Setup global SPI_SYSCTRL register for all SPI channels.
0124  */
0125 static void xlp_spi_sysctl_setup(struct xlp_spi_priv *xspi)
0126 {
0127     int cs;
0128
0129     for (cs = 0; cs < XLP_SPI_MAX_CS; cs++)
0130         xlp_spi_sysctl_write(xspi, XLP_SPI_SYSCTRL,
0131                 XLP_SPI_SYS_RESET << cs);
0132     xlp_spi_sysctl_write(xspi, XLP_SPI_SYSCTRL, XLP_SPI_SYS_PMEN);
0133 }
0134
0135 static int xlp_spi_setup(struct spi_device *spi)
0136 {
0137     struct xlp_spi_priv *xspi;
0138     u32 fdiv, cfg;
0139     int cs;
0140
0141     xspi = spi_master_get_devdata(spi->master);
0142     cs = spi->chip_select;
0143     /*
0144      * The value of fdiv must be between 4 and 65535.
0145      */
0146     fdiv = DIV_ROUND_UP(xspi->spi_clk, spi->max_speed_hz);
0147     if (fdiv > XLP_SPI_FDIV_MAX)
0148         fdiv = XLP_SPI_FDIV_MAX;
0149     else if (fdiv < XLP_SPI_FDIV_MIN)
0150         fdiv = XLP_SPI_FDIV_MIN;
0151
0152     xlp_spi_reg_write(xspi, cs, XLP_SPI_FDIV, fdiv);
0153     xlp_spi_reg_write(xspi, cs, XLP_SPI_FIFO_THRESH, XLP_SPI_TXRXTH);
0154     cfg = xlp_spi_reg_read(xspi, cs, XLP_SPI_CONFIG);
0155     if (spi->mode & SPI_CPHA)
0156         cfg |= XLP_SPI_CPHA;
0157     else
0158         cfg &= ~XLP_SPI_CPHA;
0159     if (spi->mode & SPI_CPOL)
0160         cfg |= XLP_SPI_CPOL;
0161     else
0162         cfg &= ~XLP_SPI_CPOL;
0163     if (!(spi->mode & SPI_CS_HIGH))
0164         cfg |= XLP_SPI_CS_POL;
0165     else
0166         cfg &= ~XLP_SPI_CS_POL;
0167     if (spi->mode & SPI_LSB_FIRST)
0168         cfg |= XLP_SPI_CS_LSBFE;
0169     else
0170         cfg &= ~XLP_SPI_CS_LSBFE;
0171
0172     cfg |= XLP_SPI_TXMOSI_EN | XLP_SPI_RXMISO_EN;
0173     if (fdiv == 4)
0174         cfg |= XLP_SPI_RXCAP_EN;
0175     xlp_spi_reg_write(xspi, cs, XLP_SPI_CONFIG, cfg);
0176
0177     return 0;
0178 }
0179
0180 static void xlp_spi_read_rxfifo(struct xlp_spi_priv *xspi)
0181 {
0182     u32 rx_data, rxfifo_cnt;
0183     int i, j, nbytes;
0184
0185     rxfifo_cnt = xlp_spi_reg_read(xspi, xspi->cs, XLP_SPI_FIFO_WCNT);
0186     rxfifo_cnt &= XLP_SPI_RXFIFO_WCNT_MASK;
0187     while (rxfifo_cnt) {
0188         rx_data = xlp_spi_reg_read(xspi, xspi->cs, XLP_SPI_RXDATA_FIFO);
0189         j = 0;
0190         nbytes = min(xspi->rx_len, 4);
0191         for (i = nbytes - 1; i >= 0; i--, j++)
0192             xspi->rx_buf[i] = (rx_data >> (j * 8)) & 0xff;
0193
0194         xspi->rx_len -= nbytes;
0195         xspi->rx_buf += nbytes;
0196         rxfifo_cnt--;
0197     }
0198 }
0199
0200 static void xlp_spi_fill_txfifo(struct xlp_spi_priv *xspi)
0201 {
0202     u32 tx_data, txfifo_cnt;
0203     int i, j, nbytes;
0204
0205     txfifo_cnt = xlp_spi_reg_read(xspi, xspi->cs, XLP_SPI_FIFO_WCNT);
0206     txfifo_cnt &= XLP_SPI_TXFIFO_WCNT_MASK;
0207     txfifo_cnt >>= XLP_SPI_TXFIFO_WCNT_SHIFT;
0208     while (xspi->tx_len && (txfifo_cnt < XLP_SPI_FIFO_SIZE)) {
0209         j = 0;
0210         tx_data = 0;
0211         nbytes = min(xspi->tx_len, 4);
0212         for (i = nbytes - 1; i >= 0; i--, j++)
0213             tx_data |= xspi->tx_buf[i] << (j * 8);
0214
0215         xlp_spi_reg_write(xspi, xspi->cs, XLP_SPI_TXDATA_FIFO, tx_data);
0216         xspi->tx_len -= nbytes;
0217         xspi->tx_buf += nbytes;
0218         txfifo_cnt++;
0219     }
0220 }
0221
0222 static irqreturn_t xlp_spi_interrupt(int irq, void *dev_id)
0223 {
0224     struct xlp_spi_priv *xspi = dev_id;
0225     u32 stat;
0226
0227     stat = xlp_spi_reg_read(xspi, xspi->cs, XLP_SPI_STATUS) &
0228         XLP_SPI_STAT_MASK;
0229     if (!stat)
0230         return IRQ_NONE;
0231
0232     if (stat & XLP_SPI_TX_INT) {
0233         if (xspi->tx_len)
0234             xlp_spi_fill_txfifo(xspi);
0235         if (stat & XLP_SPI_TX_UF)
0236             xspi->txerrors++;
0237     }
0238
0239     if (stat & XLP_SPI_RX_INT) {
0240         if (xspi->rx_len)
0241             xlp_spi_read_rxfifo(xspi);
0242         if (stat & XLP_SPI_RX_OF)
0243             xspi->rxerrors++;
0244     }
0245
0246     /* write status back to clear interrupts */
0247     xlp_spi_reg_write(xspi, xspi->cs, XLP_SPI_STATUS, stat);
0248     if (stat & XLP_SPI_XFR_DONE)
0249         complete(&xspi->done);
0250
0251     return IRQ_HANDLED;
0252 }
0253
0254 static void xlp_spi_send_cmd(struct xlp_spi_priv *xspi, int xfer_len,
0255             int cmd_cont)
0256 {
0257     u32 cmd = 0;
0258
0259     if (xspi->tx_buf)
0260         cmd |= XLP_SPI_CMD_TX_MASK;
0261     if (xspi->rx_buf)
0262         cmd |= XLP_SPI_CMD_RX_MASK;
0263     if (cmd_cont)
0264         cmd |= XLP_SPI_CMD_CONT;
0265     cmd |= ((xfer_len * 8 - 1) << XLP_SPI_XFR_BITCNT_SHIFT);
0266     xlp_spi_reg_write(xspi, xspi->cs, XLP_SPI_CMD, cmd);
0267 }
0268
0269 static int xlp_spi_xfer_block(struct  xlp_spi_priv *xs,
0270         const unsigned char *tx_buf,
0271         unsigned char *rx_buf, int xfer_len, int cmd_cont)
0272 {
0273     int timeout;
0274     u32 intr_mask = 0;
0275
0276     xs->tx_buf = tx_buf;
0277     xs->rx_buf = rx_buf;
0278     xs->tx_len = (xs->tx_buf == NULL) ? 0 : xfer_len;
0279     xs->rx_len = (xs->rx_buf == NULL) ? 0 : xfer_len;
0280     xs->txerrors = xs->rxerrors = 0;
0281
0282     /* fill TXDATA_FIFO, then send the CMD */
0283     if (xs->tx_len)
0284         xlp_spi_fill_txfifo(xs);
0285
0286     xlp_spi_send_cmd(xs, xfer_len, cmd_cont);
0287
0288     /*
0289      * We are getting some spurious tx interrupts, so avoid enabling
0290      * tx interrupts when only rx is in process.
0291      * Enable all the interrupts in tx case.
0292      */
0293     if (xs->tx_len)
0294         intr_mask |= XLP_SPI_INTR_TXTH | XLP_SPI_INTR_TXUF |
0295                 XLP_SPI_INTR_RXTH | XLP_SPI_INTR_RXOF;
0296     else
0297         intr_mask |= XLP_SPI_INTR_RXTH | XLP_SPI_INTR_RXOF;
0298
0299     intr_mask |= XLP_SPI_INTR_DONE;
0300     xlp_spi_reg_write(xs, xs->cs, XLP_SPI_INTR_EN, intr_mask);
0301
0302     timeout = wait_for_completion_timeout(&xs->done,
0303                 msecs_to_jiffies(1000));
0304     /* Disable interrupts */
0305     xlp_spi_reg_write(xs, xs->cs, XLP_SPI_INTR_EN, 0x0);
0306     if (!timeout) {
0307         dev_err(&xs->dev, "xfer timedout!\n");
0308         goto out;
0309     }
0310     if (xs->txerrors || xs->rxerrors)
0311         dev_err(&xs->dev, "Over/Underflow rx %d tx %d xfer %d!\n",
0312                 xs->rxerrors, xs->txerrors, xfer_len);
0313
0314     return xfer_len;
0315 out:
0316     return -ETIMEDOUT;
0317 }
0318
0319 static int xlp_spi_txrx_bufs(struct xlp_spi_priv *xs, struct spi_transfer *t)
0320 {
0321     int bytesleft, sz;
0322     unsigned char *rx_buf;
0323     const unsigned char *tx_buf;
0324
0325     tx_buf = t->tx_buf;
0326     rx_buf = t->rx_buf;
0327     bytesleft = t->len;
0328     while (bytesleft) {
0329         if (bytesleft > XLP_SPI_XFER_SIZE)
0330             sz = xlp_spi_xfer_block(xs, tx_buf, rx_buf,
0331                     XLP_SPI_XFER_SIZE, 1);
0332         else
0333             sz = xlp_spi_xfer_block(xs, tx_buf, rx_buf,
0334                     bytesleft, xs->cmd_cont);
0335         if (sz < 0)
0336             return sz;
0337         bytesleft -= sz;
0338         if (tx_buf)
0339             tx_buf += sz;
0340         if (rx_buf)
0341             rx_buf += sz;
0342     }
0343     return bytesleft;
0344 }
0345
0346 static int xlp_spi_transfer_one(struct spi_master *master,
0347                     struct spi_device *spi,
0348                     struct spi_transfer *t)
0349 {
0350     struct xlp_spi_priv *xspi = spi_master_get_devdata(master);
0351     int ret = 0;
0352
0353     xspi->cs = spi->chip_select;
0354     xspi->dev = spi->dev;
0355
0356     if (spi_transfer_is_last(master, t))
0357         xspi->cmd_cont = 0;
0358     else
0359         xspi->cmd_cont = 1;
0360
0361     if (xlp_spi_txrx_bufs(xspi, t))
0362         ret = -EIO;
0363
0364     spi_finalize_current_transfer(master);
0365     return ret;
0366 }
0367
0368 static int xlp_spi_probe(struct platform_device *pdev)
0369 {
0370     struct spi_master *master;
0371     struct xlp_spi_priv *xspi;
0372     struct clk *clk;
0373     int irq, err;
0374
0375     xspi = devm_kzalloc(&pdev->dev, sizeof(*xspi), GFP_KERNEL);
0376     if (!xspi)
0377         return -ENOMEM;
0378
0379     xspi->base = devm_platform_ioremap_resource(pdev, 0);
0380     if (IS_ERR(xspi->base))
0381         return PTR_ERR(xspi->base);
0382
0383     irq = platform_get_irq(pdev, 0);
0384     if (irq < 0)
0385         return irq;
0386     err = devm_request_irq(&pdev->dev, irq, xlp_spi_interrupt, 0,
0387             pdev->name, xspi);
0388     if (err) {
0389         dev_err(&pdev->dev, "unable to request irq %d\n", irq);
0390         return err;
0391     }
0392
0393     clk = devm_clk_get(&pdev->dev, NULL);
0394     if (IS_ERR(clk)) {
0395         dev_err(&pdev->dev, "could not get spi clock\n");
0396         return PTR_ERR(clk);
0397     }
0398
0399     xspi->spi_clk = clk_get_rate(clk);
0400
0401     master = spi_alloc_master(&pdev->dev, 0);
0402     if (!master) {
0403         dev_err(&pdev->dev, "could not alloc master\n");
0404         return -ENOMEM;
0405     }
0406
0407     master->bus_num = 0;
0408     master->num_chipselect = XLP_SPI_MAX_CS;
0409     master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
0410     master->setup = xlp_spi_setup;
0411     master->transfer_one = xlp_spi_transfer_one;
0412     master->dev.of_node = pdev->dev.of_node;
0413
0414     init_completion(&xspi->done);
0415     spi_master_set_devdata(master, xspi);
0416     xlp_spi_sysctl_setup(xspi);
0417
0418     /* register spi controller */
0419     err = devm_spi_register_master(&pdev->dev, master);
0420     if (err) {
0421         dev_err(&pdev->dev, "spi register master failed!\n");
0422         spi_master_put(master);
0423         return err;
0424     }
0425
0426     return 0;
0427 }
0428
0429 #ifdef CONFIG_ACPI
0430 static const struct acpi_device_id xlp_spi_acpi_match[] = {
0431     { "BRCM900D", 0 },
0432     { "CAV900D",  0 },
0433     { },
0434 };
0435 MODULE_DEVICE_TABLE(acpi, xlp_spi_acpi_match);
0436 #endif
0437
0438 static struct platform_driver xlp_spi_driver = {
0439     .probe  = xlp_spi_probe,
0440     .driver = {
0441         .name   = "xlp-spi",
0442         .acpi_match_table = ACPI_PTR(xlp_spi_acpi_match),
0443     },
0444 };
0445 module_platform_driver(xlp_spi_driver);
0446
0447 MODULE_AUTHOR("Kamlakant Patel <kamlakant.patel@broadcom.com>");
0448 MODULE_DESCRIPTION("Netlogic XLP SPI controller driver");
0449 MODULE_LICENSE("GPL v2");