drivers/spi/spi-xilinx.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Xilinx SPI controller driver (master mode only)
0004  *
0005  * Author: MontaVista Software, Inc.
0006  *  source@mvista.com
0007  *
0008  * Copyright (c) 2010 Secret Lab Technologies, Ltd.
0009  * Copyright (c) 2009 Intel Corporation
0010  * 2002-2007 (c) MontaVista Software, Inc.
0011
0012  */
0013
0014 #include <linux/module.h>
0015 #include <linux/interrupt.h>
0016 #include <linux/of.h>
0017 #include <linux/platform_device.h>
0018 #include <linux/spi/spi.h>
0019 #include <linux/spi/spi_bitbang.h>
0020 #include <linux/spi/xilinx_spi.h>
0021 #include <linux/io.h>
0022
0023 #define XILINX_SPI_MAX_CS   32
0024
0025 #define XILINX_SPI_NAME "xilinx_spi"
0026
0027 /* Register definitions as per "OPB Serial Peripheral Interface (SPI) (v1.00e)
0028  * Product Specification", DS464
0029  */
0030 #define XSPI_CR_OFFSET      0x60    /* Control Register */
0031
0032 #define XSPI_CR_LOOP        0x01
0033 #define XSPI_CR_ENABLE      0x02
0034 #define XSPI_CR_MASTER_MODE 0x04
0035 #define XSPI_CR_CPOL        0x08
0036 #define XSPI_CR_CPHA        0x10
0037 #define XSPI_CR_MODE_MASK   (XSPI_CR_CPHA | XSPI_CR_CPOL | \
0038                  XSPI_CR_LSB_FIRST | XSPI_CR_LOOP)
0039 #define XSPI_CR_TXFIFO_RESET    0x20
0040 #define XSPI_CR_RXFIFO_RESET    0x40
0041 #define XSPI_CR_MANUAL_SSELECT  0x80
0042 #define XSPI_CR_TRANS_INHIBIT   0x100
0043 #define XSPI_CR_LSB_FIRST   0x200
0044
0045 #define XSPI_SR_OFFSET      0x64    /* Status Register */
0046
0047 #define XSPI_SR_RX_EMPTY_MASK   0x01    /* Receive FIFO is empty */
0048 #define XSPI_SR_RX_FULL_MASK    0x02    /* Receive FIFO is full */
0049 #define XSPI_SR_TX_EMPTY_MASK   0x04    /* Transmit FIFO is empty */
0050 #define XSPI_SR_TX_FULL_MASK    0x08    /* Transmit FIFO is full */
0051 #define XSPI_SR_MODE_FAULT_MASK 0x10    /* Mode fault error */
0052
0053 #define XSPI_TXD_OFFSET     0x68    /* Data Transmit Register */
0054 #define XSPI_RXD_OFFSET     0x6c    /* Data Receive Register */
0055
0056 #define XSPI_SSR_OFFSET     0x70    /* 32-bit Slave Select Register */
0057
0058 /* Register definitions as per "OPB IPIF (v3.01c) Product Specification", DS414
0059  * IPIF registers are 32 bit
0060  */
0061 #define XIPIF_V123B_DGIER_OFFSET    0x1c    /* IPIF global int enable reg */
0062 #define XIPIF_V123B_GINTR_ENABLE    0x80000000
0063
0064 #define XIPIF_V123B_IISR_OFFSET     0x20    /* IPIF interrupt status reg */
0065 #define XIPIF_V123B_IIER_OFFSET     0x28    /* IPIF interrupt enable reg */
0066
0067 #define XSPI_INTR_MODE_FAULT        0x01    /* Mode fault error */
0068 #define XSPI_INTR_SLAVE_MODE_FAULT  0x02    /* Selected as slave while
0069                          * disabled */
0070 #define XSPI_INTR_TX_EMPTY      0x04    /* TxFIFO is empty */
0071 #define XSPI_INTR_TX_UNDERRUN       0x08    /* TxFIFO was underrun */
0072 #define XSPI_INTR_RX_FULL       0x10    /* RxFIFO is full */
0073 #define XSPI_INTR_RX_OVERRUN        0x20    /* RxFIFO was overrun */
0074 #define XSPI_INTR_TX_HALF_EMPTY     0x40    /* TxFIFO is half empty */
0075
0076 #define XIPIF_V123B_RESETR_OFFSET   0x40    /* IPIF reset register */
0077 #define XIPIF_V123B_RESET_MASK      0x0a    /* the value to write */
0078
0079 struct xilinx_spi {
0080     /* bitbang has to be first */
0081     struct spi_bitbang bitbang;
0082     struct completion done;
0083     void __iomem    *regs;  /* virt. address of the control registers */
0084
0085     int     irq;
0086
0087     u8 *rx_ptr;     /* pointer in the Tx buffer */
0088     const u8 *tx_ptr;   /* pointer in the Rx buffer */
0089     u8 bytes_per_word;
0090     int buffer_size;    /* buffer size in words */
0091     u32 cs_inactive;    /* Level of the CS pins when inactive*/
0092     unsigned int (*read_fn)(void __iomem *);
0093     void (*write_fn)(u32, void __iomem *);
0094 };
0095
0096 static void xspi_write32(u32 val, void __iomem *addr)
0097 {
0098     iowrite32(val, addr);
0099 }
0100
0101 static unsigned int xspi_read32(void __iomem *addr)
0102 {
0103     return ioread32(addr);
0104 }
0105
0106 static void xspi_write32_be(u32 val, void __iomem *addr)
0107 {
0108     iowrite32be(val, addr);
0109 }
0110
0111 static unsigned int xspi_read32_be(void __iomem *addr)
0112 {
0113     return ioread32be(addr);
0114 }
0115
0116 static void xilinx_spi_tx(struct xilinx_spi *xspi)
0117 {
0118     u32 data = 0;
0119
0120     if (!xspi->tx_ptr) {
0121         xspi->write_fn(0, xspi->regs + XSPI_TXD_OFFSET);
0122         return;
0123     }
0124
0125     switch (xspi->bytes_per_word) {
0126     case 1:
0127         data = *(u8 *)(xspi->tx_ptr);
0128         break;
0129     case 2:
0130         data = *(u16 *)(xspi->tx_ptr);
0131         break;
0132     case 4:
0133         data = *(u32 *)(xspi->tx_ptr);
0134         break;
0135     }
0136
0137     xspi->write_fn(data, xspi->regs + XSPI_TXD_OFFSET);
0138     xspi->tx_ptr += xspi->bytes_per_word;
0139 }
0140
0141 static void xilinx_spi_rx(struct xilinx_spi *xspi)
0142 {
0143     u32 data = xspi->read_fn(xspi->regs + XSPI_RXD_OFFSET);
0144
0145     if (!xspi->rx_ptr)
0146         return;
0147
0148     switch (xspi->bytes_per_word) {
0149     case 1:
0150         *(u8 *)(xspi->rx_ptr) = data;
0151         break;
0152     case 2:
0153         *(u16 *)(xspi->rx_ptr) = data;
0154         break;
0155     case 4:
0156         *(u32 *)(xspi->rx_ptr) = data;
0157         break;
0158     }
0159
0160     xspi->rx_ptr += xspi->bytes_per_word;
0161 }
0162
0163 static void xspi_init_hw(struct xilinx_spi *xspi)
0164 {
0165     void __iomem *regs_base = xspi->regs;
0166
0167     /* Reset the SPI device */
0168     xspi->write_fn(XIPIF_V123B_RESET_MASK,
0169         regs_base + XIPIF_V123B_RESETR_OFFSET);
0170     /* Enable the transmit empty interrupt, which we use to determine
0171      * progress on the transmission.
0172      */
0173     xspi->write_fn(XSPI_INTR_TX_EMPTY,
0174             regs_base + XIPIF_V123B_IIER_OFFSET);
0175     /* Disable the global IPIF interrupt */
0176     xspi->write_fn(0, regs_base + XIPIF_V123B_DGIER_OFFSET);
0177     /* Deselect the slave on the SPI bus */
0178     xspi->write_fn(0xffff, regs_base + XSPI_SSR_OFFSET);
0179     /* Disable the transmitter, enable Manual Slave Select Assertion,
0180      * put SPI controller into master mode, and enable it */
0181     xspi->write_fn(XSPI_CR_MANUAL_SSELECT | XSPI_CR_MASTER_MODE |
0182         XSPI_CR_ENABLE | XSPI_CR_TXFIFO_RESET | XSPI_CR_RXFIFO_RESET,
0183         regs_base + XSPI_CR_OFFSET);
0184 }
0185
0186 static void xilinx_spi_chipselect(struct spi_device *spi, int is_on)
0187 {
0188     struct xilinx_spi *xspi = spi_master_get_devdata(spi->master);
0189     u16 cr;
0190     u32 cs;
0191
0192     if (is_on == BITBANG_CS_INACTIVE) {
0193         /* Deselect the slave on the SPI bus */
0194         xspi->write_fn(xspi->cs_inactive, xspi->regs + XSPI_SSR_OFFSET);
0195         return;
0196     }
0197
0198     /* Set the SPI clock phase and polarity */
0199     cr = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET) & ~XSPI_CR_MODE_MASK;
0200     if (spi->mode & SPI_CPHA)
0201         cr |= XSPI_CR_CPHA;
0202     if (spi->mode & SPI_CPOL)
0203         cr |= XSPI_CR_CPOL;
0204     if (spi->mode & SPI_LSB_FIRST)
0205         cr |= XSPI_CR_LSB_FIRST;
0206     if (spi->mode & SPI_LOOP)
0207         cr |= XSPI_CR_LOOP;
0208     xspi->write_fn(cr, xspi->regs + XSPI_CR_OFFSET);
0209
0210     /* We do not check spi->max_speed_hz here as the SPI clock
0211      * frequency is not software programmable (the IP block design
0212      * parameter)
0213      */
0214
0215     cs = xspi->cs_inactive;
0216     cs ^= BIT(spi->chip_select);
0217
0218     /* Activate the chip select */
0219     xspi->write_fn(cs, xspi->regs + XSPI_SSR_OFFSET);
0220 }
0221
0222 /* spi_bitbang requires custom setup_transfer() to be defined if there is a
0223  * custom txrx_bufs().
0224  */
0225 static int xilinx_spi_setup_transfer(struct spi_device *spi,
0226         struct spi_transfer *t)
0227 {
0228     struct xilinx_spi *xspi = spi_master_get_devdata(spi->master);
0229
0230     if (spi->mode & SPI_CS_HIGH)
0231         xspi->cs_inactive &= ~BIT(spi->chip_select);
0232     else
0233         xspi->cs_inactive |= BIT(spi->chip_select);
0234
0235     return 0;
0236 }
0237
0238 static int xilinx_spi_txrx_bufs(struct spi_device *spi, struct spi_transfer *t)
0239 {
0240     struct xilinx_spi *xspi = spi_master_get_devdata(spi->master);
0241     int remaining_words;    /* the number of words left to transfer */
0242     bool use_irq = false;
0243     u16 cr = 0;
0244
0245     /* We get here with transmitter inhibited */
0246
0247     xspi->tx_ptr = t->tx_buf;
0248     xspi->rx_ptr = t->rx_buf;
0249     remaining_words = t->len / xspi->bytes_per_word;
0250
0251     if (xspi->irq >= 0 &&  remaining_words > xspi->buffer_size) {
0252         u32 isr;
0253         use_irq = true;
0254         /* Inhibit irq to avoid spurious irqs on tx_empty*/
0255         cr = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET);
0256         xspi->write_fn(cr | XSPI_CR_TRANS_INHIBIT,
0257                    xspi->regs + XSPI_CR_OFFSET);
0258         /* ACK old irqs (if any) */
0259         isr = xspi->read_fn(xspi->regs + XIPIF_V123B_IISR_OFFSET);
0260         if (isr)
0261             xspi->write_fn(isr,
0262                        xspi->regs + XIPIF_V123B_IISR_OFFSET);
0263         /* Enable the global IPIF interrupt */
0264         xspi->write_fn(XIPIF_V123B_GINTR_ENABLE,
0265                 xspi->regs + XIPIF_V123B_DGIER_OFFSET);
0266         reinit_completion(&xspi->done);
0267     }
0268
0269     while (remaining_words) {
0270         int n_words, tx_words, rx_words;
0271         u32 sr;
0272         int stalled;
0273
0274         n_words = min(remaining_words, xspi->buffer_size);
0275
0276         tx_words = n_words;
0277         while (tx_words--)
0278             xilinx_spi_tx(xspi);
0279
0280         /* Start the transfer by not inhibiting the transmitter any
0281          * longer
0282          */
0283
0284         if (use_irq) {
0285             xspi->write_fn(cr, xspi->regs + XSPI_CR_OFFSET);
0286             wait_for_completion(&xspi->done);
0287             /* A transmit has just completed. Process received data
0288              * and check for more data to transmit. Always inhibit
0289              * the transmitter while the Isr refills the transmit
0290              * register/FIFO, or make sure it is stopped if we're
0291              * done.
0292              */
0293             xspi->write_fn(cr | XSPI_CR_TRANS_INHIBIT,
0294                        xspi->regs + XSPI_CR_OFFSET);
0295             sr = XSPI_SR_TX_EMPTY_MASK;
0296         } else
0297             sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET);
0298
0299         /* Read out all the data from the Rx FIFO */
0300         rx_words = n_words;
0301         stalled = 10;
0302         while (rx_words) {
0303             if (rx_words == n_words && !(stalled--) &&
0304                 !(sr & XSPI_SR_TX_EMPTY_MASK) &&
0305                 (sr & XSPI_SR_RX_EMPTY_MASK)) {
0306                 dev_err(&spi->dev,
0307                     "Detected stall. Check C_SPI_MODE and C_SPI_MEMORY\n");
0308                 xspi_init_hw(xspi);
0309                 return -EIO;
0310             }
0311
0312             if ((sr & XSPI_SR_TX_EMPTY_MASK) && (rx_words > 1)) {
0313                 xilinx_spi_rx(xspi);
0314                 rx_words--;
0315                 continue;
0316             }
0317
0318             sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET);
0319             if (!(sr & XSPI_SR_RX_EMPTY_MASK)) {
0320                 xilinx_spi_rx(xspi);
0321                 rx_words--;
0322             }
0323         }
0324
0325         remaining_words -= n_words;
0326     }
0327
0328     if (use_irq) {
0329         xspi->write_fn(0, xspi->regs + XIPIF_V123B_DGIER_OFFSET);
0330         xspi->write_fn(cr, xspi->regs + XSPI_CR_OFFSET);
0331     }
0332
0333     return t->len;
0334 }
0335
0336
0337 /* This driver supports single master mode only. Hence Tx FIFO Empty
0338  * is the only interrupt we care about.
0339  * Receive FIFO Overrun, Transmit FIFO Underrun, Mode Fault, and Slave Mode
0340  * Fault are not to happen.
0341  */
0342 static irqreturn_t xilinx_spi_irq(int irq, void *dev_id)
0343 {
0344     struct xilinx_spi *xspi = dev_id;
0345     u32 ipif_isr;
0346
0347     /* Get the IPIF interrupts, and clear them immediately */
0348     ipif_isr = xspi->read_fn(xspi->regs + XIPIF_V123B_IISR_OFFSET);
0349     xspi->write_fn(ipif_isr, xspi->regs + XIPIF_V123B_IISR_OFFSET);
0350
0351     if (ipif_isr & XSPI_INTR_TX_EMPTY) {    /* Transmission completed */
0352         complete(&xspi->done);
0353         return IRQ_HANDLED;
0354     }
0355
0356     return IRQ_NONE;
0357 }
0358
0359 static int xilinx_spi_find_buffer_size(struct xilinx_spi *xspi)
0360 {
0361     u8 sr;
0362     int n_words = 0;
0363
0364     /*
0365      * Before the buffer_size detection we reset the core
0366      * to make sure we start with a clean state.
0367      */
0368     xspi->write_fn(XIPIF_V123B_RESET_MASK,
0369         xspi->regs + XIPIF_V123B_RESETR_OFFSET);
0370
0371     /* Fill the Tx FIFO with as many words as possible */
0372     do {
0373         xspi->write_fn(0, xspi->regs + XSPI_TXD_OFFSET);
0374         sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET);
0375         n_words++;
0376     } while (!(sr & XSPI_SR_TX_FULL_MASK));
0377
0378     return n_words;
0379 }
0380
0381 static const struct of_device_id xilinx_spi_of_match[] = {
0382     { .compatible = "xlnx,axi-quad-spi-1.00.a", },
0383     { .compatible = "xlnx,xps-spi-2.00.a", },
0384     { .compatible = "xlnx,xps-spi-2.00.b", },
0385     {}
0386 };
0387 MODULE_DEVICE_TABLE(of, xilinx_spi_of_match);
0388
0389 static int xilinx_spi_probe(struct platform_device *pdev)
0390 {
0391     struct xilinx_spi *xspi;
0392     struct xspi_platform_data *pdata;
0393     struct resource *res;
0394     int ret, num_cs = 0, bits_per_word;
0395     struct spi_master *master;
0396     u32 tmp;
0397     u8 i;
0398
0399     pdata = dev_get_platdata(&pdev->dev);
0400     if (pdata) {
0401         num_cs = pdata->num_chipselect;
0402         bits_per_word = pdata->bits_per_word;
0403     } else {
0404         of_property_read_u32(pdev->dev.of_node, "xlnx,num-ss-bits",
0405                       &num_cs);
0406         ret = of_property_read_u32(pdev->dev.of_node,
0407                        "xlnx,num-transfer-bits",
0408                        &bits_per_word);
0409         if (ret)
0410             bits_per_word = 8;
0411     }
0412
0413     if (!num_cs) {
0414         dev_err(&pdev->dev,
0415             "Missing slave select configuration data\n");
0416         return -EINVAL;
0417     }
0418
0419     if (num_cs > XILINX_SPI_MAX_CS) {
0420         dev_err(&pdev->dev, "Invalid number of spi slaves\n");
0421         return -EINVAL;
0422     }
0423
0424     master = spi_alloc_master(&pdev->dev, sizeof(struct xilinx_spi));
0425     if (!master)
0426         return -ENODEV;
0427
0428     /* the spi->mode bits understood by this driver: */
0429     master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST | SPI_LOOP |
0430                 SPI_CS_HIGH;
0431
0432     xspi = spi_master_get_devdata(master);
0433     xspi->cs_inactive = 0xffffffff;
0434     xspi->bitbang.master = master;
0435     xspi->bitbang.chipselect = xilinx_spi_chipselect;
0436     xspi->bitbang.setup_transfer = xilinx_spi_setup_transfer;
0437     xspi->bitbang.txrx_bufs = xilinx_spi_txrx_bufs;
0438     init_completion(&xspi->done);
0439
0440     res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
0441     xspi->regs = devm_ioremap_resource(&pdev->dev, res);
0442     if (IS_ERR(xspi->regs)) {
0443         ret = PTR_ERR(xspi->regs);
0444         goto put_master;
0445     }
0446
0447     master->bus_num = pdev->id;
0448     master->num_chipselect = num_cs;
0449     master->dev.of_node = pdev->dev.of_node;
0450
0451     /*
0452      * Detect endianess on the IP via loop bit in CR. Detection
0453      * must be done before reset is sent because incorrect reset
0454      * value generates error interrupt.
0455      * Setup little endian helper functions first and try to use them
0456      * and check if bit was correctly setup or not.
0457      */
0458     xspi->read_fn = xspi_read32;
0459     xspi->write_fn = xspi_write32;
0460
0461     xspi->write_fn(XSPI_CR_LOOP, xspi->regs + XSPI_CR_OFFSET);
0462     tmp = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET);
0463     tmp &= XSPI_CR_LOOP;
0464     if (tmp != XSPI_CR_LOOP) {
0465         xspi->read_fn = xspi_read32_be;
0466         xspi->write_fn = xspi_write32_be;
0467     }
0468
0469     master->bits_per_word_mask = SPI_BPW_MASK(bits_per_word);
0470     xspi->bytes_per_word = bits_per_word / 8;
0471     xspi->buffer_size = xilinx_spi_find_buffer_size(xspi);
0472
0473     xspi->irq = platform_get_irq(pdev, 0);
0474     if (xspi->irq < 0 && xspi->irq != -ENXIO) {
0475         ret = xspi->irq;
0476         goto put_master;
0477     } else if (xspi->irq >= 0) {
0478         /* Register for SPI Interrupt */
0479         ret = devm_request_irq(&pdev->dev, xspi->irq, xilinx_spi_irq, 0,
0480                 dev_name(&pdev->dev), xspi);
0481         if (ret)
0482             goto put_master;
0483     }
0484
0485     /* SPI controller initializations */
0486     xspi_init_hw(xspi);
0487
0488     ret = spi_bitbang_start(&xspi->bitbang);
0489     if (ret) {
0490         dev_err(&pdev->dev, "spi_bitbang_start FAILED\n");
0491         goto put_master;
0492     }
0493
0494     dev_info(&pdev->dev, "at %pR, irq=%d\n", res, xspi->irq);
0495
0496     if (pdata) {
0497         for (i = 0; i < pdata->num_devices; i++)
0498             spi_new_device(master, pdata->devices + i);
0499     }
0500
0501     platform_set_drvdata(pdev, master);
0502     return 0;
0503
0504 put_master:
0505     spi_master_put(master);
0506
0507     return ret;
0508 }
0509
0510 static int xilinx_spi_remove(struct platform_device *pdev)
0511 {
0512     struct spi_master *master = platform_get_drvdata(pdev);
0513     struct xilinx_spi *xspi = spi_master_get_devdata(master);
0514     void __iomem *regs_base = xspi->regs;
0515
0516     spi_bitbang_stop(&xspi->bitbang);
0517
0518     /* Disable all the interrupts just in case */
0519     xspi->write_fn(0, regs_base + XIPIF_V123B_IIER_OFFSET);
0520     /* Disable the global IPIF interrupt */
0521     xspi->write_fn(0, regs_base + XIPIF_V123B_DGIER_OFFSET);
0522
0523     spi_master_put(xspi->bitbang.master);
0524
0525     return 0;
0526 }
0527
0528 /* work with hotplug and coldplug */
0529 MODULE_ALIAS("platform:" XILINX_SPI_NAME);
0530
0531 static struct platform_driver xilinx_spi_driver = {
0532     .probe = xilinx_spi_probe,
0533     .remove = xilinx_spi_remove,
0534     .driver = {
0535         .name = XILINX_SPI_NAME,
0536         .of_match_table = xilinx_spi_of_match,
0537     },
0538 };
0539 module_platform_driver(xilinx_spi_driver);
0540
0541 MODULE_AUTHOR("MontaVista Software, Inc. <source@mvista.com>");
0542 MODULE_DESCRIPTION("Xilinx SPI driver");
0543 MODULE_LICENSE("GPL");