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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * SPI driver for Nvidia's Tegra20/Tegra30 SLINK Controller.
0004  *
0005  * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
0006  */
0007 
0008 #include <linux/clk.h>
0009 #include <linux/completion.h>
0010 #include <linux/delay.h>
0011 #include <linux/dmaengine.h>
0012 #include <linux/dma-mapping.h>
0013 #include <linux/dmapool.h>
0014 #include <linux/err.h>
0015 #include <linux/interrupt.h>
0016 #include <linux/io.h>
0017 #include <linux/kernel.h>
0018 #include <linux/kthread.h>
0019 #include <linux/module.h>
0020 #include <linux/platform_device.h>
0021 #include <linux/pm_opp.h>
0022 #include <linux/pm_runtime.h>
0023 #include <linux/of.h>
0024 #include <linux/of_device.h>
0025 #include <linux/reset.h>
0026 #include <linux/spi/spi.h>
0027 
0028 #include <soc/tegra/common.h>
0029 
0030 #define SLINK_COMMAND           0x000
0031 #define SLINK_BIT_LENGTH(x)     (((x) & 0x1f) << 0)
0032 #define SLINK_WORD_SIZE(x)      (((x) & 0x1f) << 5)
0033 #define SLINK_BOTH_EN           (1 << 10)
0034 #define SLINK_CS_SW         (1 << 11)
0035 #define SLINK_CS_VALUE          (1 << 12)
0036 #define SLINK_CS_POLARITY       (1 << 13)
0037 #define SLINK_IDLE_SDA_DRIVE_LOW    (0 << 16)
0038 #define SLINK_IDLE_SDA_DRIVE_HIGH   (1 << 16)
0039 #define SLINK_IDLE_SDA_PULL_LOW     (2 << 16)
0040 #define SLINK_IDLE_SDA_PULL_HIGH    (3 << 16)
0041 #define SLINK_IDLE_SDA_MASK     (3 << 16)
0042 #define SLINK_CS_POLARITY1      (1 << 20)
0043 #define SLINK_CK_SDA            (1 << 21)
0044 #define SLINK_CS_POLARITY2      (1 << 22)
0045 #define SLINK_CS_POLARITY3      (1 << 23)
0046 #define SLINK_IDLE_SCLK_DRIVE_LOW   (0 << 24)
0047 #define SLINK_IDLE_SCLK_DRIVE_HIGH  (1 << 24)
0048 #define SLINK_IDLE_SCLK_PULL_LOW    (2 << 24)
0049 #define SLINK_IDLE_SCLK_PULL_HIGH   (3 << 24)
0050 #define SLINK_IDLE_SCLK_MASK        (3 << 24)
0051 #define SLINK_M_S           (1 << 28)
0052 #define SLINK_WAIT          (1 << 29)
0053 #define SLINK_GO            (1 << 30)
0054 #define SLINK_ENB           (1 << 31)
0055 
0056 #define SLINK_MODES         (SLINK_IDLE_SCLK_MASK | SLINK_CK_SDA)
0057 
0058 #define SLINK_COMMAND2          0x004
0059 #define SLINK_LSBFE         (1 << 0)
0060 #define SLINK_SSOE          (1 << 1)
0061 #define SLINK_SPIE          (1 << 4)
0062 #define SLINK_BIDIROE           (1 << 6)
0063 #define SLINK_MODFEN            (1 << 7)
0064 #define SLINK_INT_SIZE(x)       (((x) & 0x1f) << 8)
0065 #define SLINK_CS_ACTIVE_BETWEEN     (1 << 17)
0066 #define SLINK_SS_EN_CS(x)       (((x) & 0x3) << 18)
0067 #define SLINK_SS_SETUP(x)       (((x) & 0x3) << 20)
0068 #define SLINK_FIFO_REFILLS_0        (0 << 22)
0069 #define SLINK_FIFO_REFILLS_1        (1 << 22)
0070 #define SLINK_FIFO_REFILLS_2        (2 << 22)
0071 #define SLINK_FIFO_REFILLS_3        (3 << 22)
0072 #define SLINK_FIFO_REFILLS_MASK     (3 << 22)
0073 #define SLINK_WAIT_PACK_INT(x)      (((x) & 0x7) << 26)
0074 #define SLINK_SPC0          (1 << 29)
0075 #define SLINK_TXEN          (1 << 30)
0076 #define SLINK_RXEN          (1 << 31)
0077 
0078 #define SLINK_STATUS            0x008
0079 #define SLINK_COUNT(val)        (((val) >> 0) & 0x1f)
0080 #define SLINK_WORD(val)         (((val) >> 5) & 0x1f)
0081 #define SLINK_BLK_CNT(val)      (((val) >> 0) & 0xffff)
0082 #define SLINK_MODF          (1 << 16)
0083 #define SLINK_RX_UNF            (1 << 18)
0084 #define SLINK_TX_OVF            (1 << 19)
0085 #define SLINK_TX_FULL           (1 << 20)
0086 #define SLINK_TX_EMPTY          (1 << 21)
0087 #define SLINK_RX_FULL           (1 << 22)
0088 #define SLINK_RX_EMPTY          (1 << 23)
0089 #define SLINK_TX_UNF            (1 << 24)
0090 #define SLINK_RX_OVF            (1 << 25)
0091 #define SLINK_TX_FLUSH          (1 << 26)
0092 #define SLINK_RX_FLUSH          (1 << 27)
0093 #define SLINK_SCLK          (1 << 28)
0094 #define SLINK_ERR           (1 << 29)
0095 #define SLINK_RDY           (1 << 30)
0096 #define SLINK_BSY           (1 << 31)
0097 #define SLINK_FIFO_ERROR        (SLINK_TX_OVF | SLINK_RX_UNF |  \
0098                     SLINK_TX_UNF | SLINK_RX_OVF)
0099 
0100 #define SLINK_FIFO_EMPTY        (SLINK_TX_EMPTY | SLINK_RX_EMPTY)
0101 
0102 #define SLINK_MAS_DATA          0x010
0103 #define SLINK_SLAVE_DATA        0x014
0104 
0105 #define SLINK_DMA_CTL           0x018
0106 #define SLINK_DMA_BLOCK_SIZE(x)     (((x) & 0xffff) << 0)
0107 #define SLINK_TX_TRIG_1         (0 << 16)
0108 #define SLINK_TX_TRIG_4         (1 << 16)
0109 #define SLINK_TX_TRIG_8         (2 << 16)
0110 #define SLINK_TX_TRIG_16        (3 << 16)
0111 #define SLINK_TX_TRIG_MASK      (3 << 16)
0112 #define SLINK_RX_TRIG_1         (0 << 18)
0113 #define SLINK_RX_TRIG_4         (1 << 18)
0114 #define SLINK_RX_TRIG_8         (2 << 18)
0115 #define SLINK_RX_TRIG_16        (3 << 18)
0116 #define SLINK_RX_TRIG_MASK      (3 << 18)
0117 #define SLINK_PACKED            (1 << 20)
0118 #define SLINK_PACK_SIZE_4       (0 << 21)
0119 #define SLINK_PACK_SIZE_8       (1 << 21)
0120 #define SLINK_PACK_SIZE_16      (2 << 21)
0121 #define SLINK_PACK_SIZE_32      (3 << 21)
0122 #define SLINK_PACK_SIZE_MASK        (3 << 21)
0123 #define SLINK_IE_TXC            (1 << 26)
0124 #define SLINK_IE_RXC            (1 << 27)
0125 #define SLINK_DMA_EN            (1 << 31)
0126 
0127 #define SLINK_STATUS2           0x01c
0128 #define SLINK_TX_FIFO_EMPTY_COUNT(val)  (((val) & 0x3f) >> 0)
0129 #define SLINK_RX_FIFO_FULL_COUNT(val)   (((val) & 0x3f0000) >> 16)
0130 #define SLINK_SS_HOLD_TIME(val)     (((val) & 0xF) << 6)
0131 
0132 #define SLINK_TX_FIFO           0x100
0133 #define SLINK_RX_FIFO           0x180
0134 
0135 #define DATA_DIR_TX         (1 << 0)
0136 #define DATA_DIR_RX         (1 << 1)
0137 
0138 #define SLINK_DMA_TIMEOUT       (msecs_to_jiffies(1000))
0139 
0140 #define DEFAULT_SPI_DMA_BUF_LEN     (16*1024)
0141 #define TX_FIFO_EMPTY_COUNT_MAX     SLINK_TX_FIFO_EMPTY_COUNT(0x20)
0142 #define RX_FIFO_FULL_COUNT_ZERO     SLINK_RX_FIFO_FULL_COUNT(0)
0143 
0144 #define SLINK_STATUS2_RESET \
0145     (TX_FIFO_EMPTY_COUNT_MAX | RX_FIFO_FULL_COUNT_ZERO << 16)
0146 
0147 #define MAX_CHIP_SELECT         4
0148 #define SLINK_FIFO_DEPTH        32
0149 
0150 struct tegra_slink_chip_data {
0151     bool cs_hold_time;
0152 };
0153 
0154 struct tegra_slink_data {
0155     struct device               *dev;
0156     struct spi_master           *master;
0157     const struct tegra_slink_chip_data  *chip_data;
0158     spinlock_t              lock;
0159 
0160     struct clk              *clk;
0161     struct reset_control            *rst;
0162     void __iomem                *base;
0163     phys_addr_t             phys;
0164     unsigned                irq;
0165     u32                 cur_speed;
0166 
0167     struct spi_device           *cur_spi;
0168     unsigned                cur_pos;
0169     unsigned                cur_len;
0170     unsigned                words_per_32bit;
0171     unsigned                bytes_per_word;
0172     unsigned                curr_dma_words;
0173     unsigned                cur_direction;
0174 
0175     unsigned                cur_rx_pos;
0176     unsigned                cur_tx_pos;
0177 
0178     unsigned                dma_buf_size;
0179     unsigned                max_buf_size;
0180     bool                    is_curr_dma_xfer;
0181 
0182     struct completion           rx_dma_complete;
0183     struct completion           tx_dma_complete;
0184 
0185     u32                 tx_status;
0186     u32                 rx_status;
0187     u32                 status_reg;
0188     bool                    is_packed;
0189     u32                 packed_size;
0190 
0191     u32                 command_reg;
0192     u32                 command2_reg;
0193     u32                 dma_control_reg;
0194     u32                 def_command_reg;
0195     u32                 def_command2_reg;
0196 
0197     struct completion           xfer_completion;
0198     struct spi_transfer         *curr_xfer;
0199     struct dma_chan             *rx_dma_chan;
0200     u32                 *rx_dma_buf;
0201     dma_addr_t              rx_dma_phys;
0202     struct dma_async_tx_descriptor      *rx_dma_desc;
0203 
0204     struct dma_chan             *tx_dma_chan;
0205     u32                 *tx_dma_buf;
0206     dma_addr_t              tx_dma_phys;
0207     struct dma_async_tx_descriptor      *tx_dma_desc;
0208 };
0209 
0210 static inline u32 tegra_slink_readl(struct tegra_slink_data *tspi,
0211         unsigned long reg)
0212 {
0213     return readl(tspi->base + reg);
0214 }
0215 
0216 static inline void tegra_slink_writel(struct tegra_slink_data *tspi,
0217         u32 val, unsigned long reg)
0218 {
0219     writel(val, tspi->base + reg);
0220 
0221     /* Read back register to make sure that register writes completed */
0222     if (reg != SLINK_TX_FIFO)
0223         readl(tspi->base + SLINK_MAS_DATA);
0224 }
0225 
0226 static void tegra_slink_clear_status(struct tegra_slink_data *tspi)
0227 {
0228     u32 val_write;
0229 
0230     tegra_slink_readl(tspi, SLINK_STATUS);
0231 
0232     /* Write 1 to clear status register */
0233     val_write = SLINK_RDY | SLINK_FIFO_ERROR;
0234     tegra_slink_writel(tspi, val_write, SLINK_STATUS);
0235 }
0236 
0237 static u32 tegra_slink_get_packed_size(struct tegra_slink_data *tspi,
0238                   struct spi_transfer *t)
0239 {
0240     switch (tspi->bytes_per_word) {
0241     case 0:
0242         return SLINK_PACK_SIZE_4;
0243     case 1:
0244         return SLINK_PACK_SIZE_8;
0245     case 2:
0246         return SLINK_PACK_SIZE_16;
0247     case 4:
0248         return SLINK_PACK_SIZE_32;
0249     default:
0250         return 0;
0251     }
0252 }
0253 
0254 static unsigned tegra_slink_calculate_curr_xfer_param(
0255     struct spi_device *spi, struct tegra_slink_data *tspi,
0256     struct spi_transfer *t)
0257 {
0258     unsigned remain_len = t->len - tspi->cur_pos;
0259     unsigned max_word;
0260     unsigned bits_per_word;
0261     unsigned max_len;
0262     unsigned total_fifo_words;
0263 
0264     bits_per_word = t->bits_per_word;
0265     tspi->bytes_per_word = DIV_ROUND_UP(bits_per_word, 8);
0266 
0267     if (bits_per_word == 8 || bits_per_word == 16) {
0268         tspi->is_packed = true;
0269         tspi->words_per_32bit = 32/bits_per_word;
0270     } else {
0271         tspi->is_packed = false;
0272         tspi->words_per_32bit = 1;
0273     }
0274     tspi->packed_size = tegra_slink_get_packed_size(tspi, t);
0275 
0276     if (tspi->is_packed) {
0277         max_len = min(remain_len, tspi->max_buf_size);
0278         tspi->curr_dma_words = max_len/tspi->bytes_per_word;
0279         total_fifo_words = max_len/4;
0280     } else {
0281         max_word = (remain_len - 1) / tspi->bytes_per_word + 1;
0282         max_word = min(max_word, tspi->max_buf_size/4);
0283         tspi->curr_dma_words = max_word;
0284         total_fifo_words = max_word;
0285     }
0286     return total_fifo_words;
0287 }
0288 
0289 static unsigned tegra_slink_fill_tx_fifo_from_client_txbuf(
0290     struct tegra_slink_data *tspi, struct spi_transfer *t)
0291 {
0292     unsigned nbytes;
0293     unsigned tx_empty_count;
0294     u32 fifo_status;
0295     unsigned max_n_32bit;
0296     unsigned i, count;
0297     unsigned int written_words;
0298     unsigned fifo_words_left;
0299     u8 *tx_buf = (u8 *)t->tx_buf + tspi->cur_tx_pos;
0300 
0301     fifo_status = tegra_slink_readl(tspi, SLINK_STATUS2);
0302     tx_empty_count = SLINK_TX_FIFO_EMPTY_COUNT(fifo_status);
0303 
0304     if (tspi->is_packed) {
0305         fifo_words_left = tx_empty_count * tspi->words_per_32bit;
0306         written_words = min(fifo_words_left, tspi->curr_dma_words);
0307         nbytes = written_words * tspi->bytes_per_word;
0308         max_n_32bit = DIV_ROUND_UP(nbytes, 4);
0309         for (count = 0; count < max_n_32bit; count++) {
0310             u32 x = 0;
0311             for (i = 0; (i < 4) && nbytes; i++, nbytes--)
0312                 x |= (u32)(*tx_buf++) << (i * 8);
0313             tegra_slink_writel(tspi, x, SLINK_TX_FIFO);
0314         }
0315     } else {
0316         max_n_32bit = min(tspi->curr_dma_words,  tx_empty_count);
0317         written_words = max_n_32bit;
0318         nbytes = written_words * tspi->bytes_per_word;
0319         for (count = 0; count < max_n_32bit; count++) {
0320             u32 x = 0;
0321             for (i = 0; nbytes && (i < tspi->bytes_per_word);
0322                             i++, nbytes--)
0323                 x |= (u32)(*tx_buf++) << (i * 8);
0324             tegra_slink_writel(tspi, x, SLINK_TX_FIFO);
0325         }
0326     }
0327     tspi->cur_tx_pos += written_words * tspi->bytes_per_word;
0328     return written_words;
0329 }
0330 
0331 static unsigned int tegra_slink_read_rx_fifo_to_client_rxbuf(
0332         struct tegra_slink_data *tspi, struct spi_transfer *t)
0333 {
0334     unsigned rx_full_count;
0335     u32 fifo_status;
0336     unsigned i, count;
0337     unsigned int read_words = 0;
0338     unsigned len;
0339     u8 *rx_buf = (u8 *)t->rx_buf + tspi->cur_rx_pos;
0340 
0341     fifo_status = tegra_slink_readl(tspi, SLINK_STATUS2);
0342     rx_full_count = SLINK_RX_FIFO_FULL_COUNT(fifo_status);
0343     if (tspi->is_packed) {
0344         len = tspi->curr_dma_words * tspi->bytes_per_word;
0345         for (count = 0; count < rx_full_count; count++) {
0346             u32 x = tegra_slink_readl(tspi, SLINK_RX_FIFO);
0347             for (i = 0; len && (i < 4); i++, len--)
0348                 *rx_buf++ = (x >> i*8) & 0xFF;
0349         }
0350         tspi->cur_rx_pos += tspi->curr_dma_words * tspi->bytes_per_word;
0351         read_words += tspi->curr_dma_words;
0352     } else {
0353         for (count = 0; count < rx_full_count; count++) {
0354             u32 x = tegra_slink_readl(tspi, SLINK_RX_FIFO);
0355             for (i = 0; (i < tspi->bytes_per_word); i++)
0356                 *rx_buf++ = (x >> (i*8)) & 0xFF;
0357         }
0358         tspi->cur_rx_pos += rx_full_count * tspi->bytes_per_word;
0359         read_words += rx_full_count;
0360     }
0361     return read_words;
0362 }
0363 
0364 static void tegra_slink_copy_client_txbuf_to_spi_txbuf(
0365         struct tegra_slink_data *tspi, struct spi_transfer *t)
0366 {
0367     /* Make the dma buffer to read by cpu */
0368     dma_sync_single_for_cpu(tspi->dev, tspi->tx_dma_phys,
0369                 tspi->dma_buf_size, DMA_TO_DEVICE);
0370 
0371     if (tspi->is_packed) {
0372         unsigned len = tspi->curr_dma_words * tspi->bytes_per_word;
0373         memcpy(tspi->tx_dma_buf, t->tx_buf + tspi->cur_pos, len);
0374     } else {
0375         unsigned int i;
0376         unsigned int count;
0377         u8 *tx_buf = (u8 *)t->tx_buf + tspi->cur_tx_pos;
0378         unsigned consume = tspi->curr_dma_words * tspi->bytes_per_word;
0379 
0380         for (count = 0; count < tspi->curr_dma_words; count++) {
0381             u32 x = 0;
0382             for (i = 0; consume && (i < tspi->bytes_per_word);
0383                             i++, consume--)
0384                 x |= (u32)(*tx_buf++) << (i * 8);
0385             tspi->tx_dma_buf[count] = x;
0386         }
0387     }
0388     tspi->cur_tx_pos += tspi->curr_dma_words * tspi->bytes_per_word;
0389 
0390     /* Make the dma buffer to read by dma */
0391     dma_sync_single_for_device(tspi->dev, tspi->tx_dma_phys,
0392                 tspi->dma_buf_size, DMA_TO_DEVICE);
0393 }
0394 
0395 static void tegra_slink_copy_spi_rxbuf_to_client_rxbuf(
0396         struct tegra_slink_data *tspi, struct spi_transfer *t)
0397 {
0398     unsigned len;
0399 
0400     /* Make the dma buffer to read by cpu */
0401     dma_sync_single_for_cpu(tspi->dev, tspi->rx_dma_phys,
0402         tspi->dma_buf_size, DMA_FROM_DEVICE);
0403 
0404     if (tspi->is_packed) {
0405         len = tspi->curr_dma_words * tspi->bytes_per_word;
0406         memcpy(t->rx_buf + tspi->cur_rx_pos, tspi->rx_dma_buf, len);
0407     } else {
0408         unsigned int i;
0409         unsigned int count;
0410         unsigned char *rx_buf = t->rx_buf + tspi->cur_rx_pos;
0411         u32 rx_mask = ((u32)1 << t->bits_per_word) - 1;
0412 
0413         for (count = 0; count < tspi->curr_dma_words; count++) {
0414             u32 x = tspi->rx_dma_buf[count] & rx_mask;
0415             for (i = 0; (i < tspi->bytes_per_word); i++)
0416                 *rx_buf++ = (x >> (i*8)) & 0xFF;
0417         }
0418     }
0419     tspi->cur_rx_pos += tspi->curr_dma_words * tspi->bytes_per_word;
0420 
0421     /* Make the dma buffer to read by dma */
0422     dma_sync_single_for_device(tspi->dev, tspi->rx_dma_phys,
0423         tspi->dma_buf_size, DMA_FROM_DEVICE);
0424 }
0425 
0426 static void tegra_slink_dma_complete(void *args)
0427 {
0428     struct completion *dma_complete = args;
0429 
0430     complete(dma_complete);
0431 }
0432 
0433 static int tegra_slink_start_tx_dma(struct tegra_slink_data *tspi, int len)
0434 {
0435     reinit_completion(&tspi->tx_dma_complete);
0436     tspi->tx_dma_desc = dmaengine_prep_slave_single(tspi->tx_dma_chan,
0437                 tspi->tx_dma_phys, len, DMA_MEM_TO_DEV,
0438                 DMA_PREP_INTERRUPT |  DMA_CTRL_ACK);
0439     if (!tspi->tx_dma_desc) {
0440         dev_err(tspi->dev, "Not able to get desc for Tx\n");
0441         return -EIO;
0442     }
0443 
0444     tspi->tx_dma_desc->callback = tegra_slink_dma_complete;
0445     tspi->tx_dma_desc->callback_param = &tspi->tx_dma_complete;
0446 
0447     dmaengine_submit(tspi->tx_dma_desc);
0448     dma_async_issue_pending(tspi->tx_dma_chan);
0449     return 0;
0450 }
0451 
0452 static int tegra_slink_start_rx_dma(struct tegra_slink_data *tspi, int len)
0453 {
0454     reinit_completion(&tspi->rx_dma_complete);
0455     tspi->rx_dma_desc = dmaengine_prep_slave_single(tspi->rx_dma_chan,
0456                 tspi->rx_dma_phys, len, DMA_DEV_TO_MEM,
0457                 DMA_PREP_INTERRUPT |  DMA_CTRL_ACK);
0458     if (!tspi->rx_dma_desc) {
0459         dev_err(tspi->dev, "Not able to get desc for Rx\n");
0460         return -EIO;
0461     }
0462 
0463     tspi->rx_dma_desc->callback = tegra_slink_dma_complete;
0464     tspi->rx_dma_desc->callback_param = &tspi->rx_dma_complete;
0465 
0466     dmaengine_submit(tspi->rx_dma_desc);
0467     dma_async_issue_pending(tspi->rx_dma_chan);
0468     return 0;
0469 }
0470 
0471 static int tegra_slink_start_dma_based_transfer(
0472         struct tegra_slink_data *tspi, struct spi_transfer *t)
0473 {
0474     u32 val;
0475     unsigned int len;
0476     int ret = 0;
0477     u32 status;
0478 
0479     /* Make sure that Rx and Tx fifo are empty */
0480     status = tegra_slink_readl(tspi, SLINK_STATUS);
0481     if ((status & SLINK_FIFO_EMPTY) != SLINK_FIFO_EMPTY) {
0482         dev_err(tspi->dev, "Rx/Tx fifo are not empty status 0x%08x\n",
0483             (unsigned)status);
0484         return -EIO;
0485     }
0486 
0487     val = SLINK_DMA_BLOCK_SIZE(tspi->curr_dma_words - 1);
0488     val |= tspi->packed_size;
0489     if (tspi->is_packed)
0490         len = DIV_ROUND_UP(tspi->curr_dma_words * tspi->bytes_per_word,
0491                     4) * 4;
0492     else
0493         len = tspi->curr_dma_words * 4;
0494 
0495     /* Set attention level based on length of transfer */
0496     if (len & 0xF)
0497         val |= SLINK_TX_TRIG_1 | SLINK_RX_TRIG_1;
0498     else if (((len) >> 4) & 0x1)
0499         val |= SLINK_TX_TRIG_4 | SLINK_RX_TRIG_4;
0500     else
0501         val |= SLINK_TX_TRIG_8 | SLINK_RX_TRIG_8;
0502 
0503     if (tspi->cur_direction & DATA_DIR_TX)
0504         val |= SLINK_IE_TXC;
0505 
0506     if (tspi->cur_direction & DATA_DIR_RX)
0507         val |= SLINK_IE_RXC;
0508 
0509     tegra_slink_writel(tspi, val, SLINK_DMA_CTL);
0510     tspi->dma_control_reg = val;
0511 
0512     if (tspi->cur_direction & DATA_DIR_TX) {
0513         tegra_slink_copy_client_txbuf_to_spi_txbuf(tspi, t);
0514         wmb();
0515         ret = tegra_slink_start_tx_dma(tspi, len);
0516         if (ret < 0) {
0517             dev_err(tspi->dev,
0518                 "Starting tx dma failed, err %d\n", ret);
0519             return ret;
0520         }
0521 
0522         /* Wait for tx fifo to be fill before starting slink */
0523         status = tegra_slink_readl(tspi, SLINK_STATUS);
0524         while (!(status & SLINK_TX_FULL))
0525             status = tegra_slink_readl(tspi, SLINK_STATUS);
0526     }
0527 
0528     if (tspi->cur_direction & DATA_DIR_RX) {
0529         /* Make the dma buffer to read by dma */
0530         dma_sync_single_for_device(tspi->dev, tspi->rx_dma_phys,
0531                 tspi->dma_buf_size, DMA_FROM_DEVICE);
0532 
0533         ret = tegra_slink_start_rx_dma(tspi, len);
0534         if (ret < 0) {
0535             dev_err(tspi->dev,
0536                 "Starting rx dma failed, err %d\n", ret);
0537             if (tspi->cur_direction & DATA_DIR_TX)
0538                 dmaengine_terminate_all(tspi->tx_dma_chan);
0539             return ret;
0540         }
0541     }
0542     tspi->is_curr_dma_xfer = true;
0543     if (tspi->is_packed) {
0544         val |= SLINK_PACKED;
0545         tegra_slink_writel(tspi, val, SLINK_DMA_CTL);
0546         /* HW need small delay after settign Packed mode */
0547         udelay(1);
0548     }
0549     tspi->dma_control_reg = val;
0550 
0551     val |= SLINK_DMA_EN;
0552     tegra_slink_writel(tspi, val, SLINK_DMA_CTL);
0553     return ret;
0554 }
0555 
0556 static int tegra_slink_start_cpu_based_transfer(
0557         struct tegra_slink_data *tspi, struct spi_transfer *t)
0558 {
0559     u32 val;
0560     unsigned cur_words;
0561 
0562     val = tspi->packed_size;
0563     if (tspi->cur_direction & DATA_DIR_TX)
0564         val |= SLINK_IE_TXC;
0565 
0566     if (tspi->cur_direction & DATA_DIR_RX)
0567         val |= SLINK_IE_RXC;
0568 
0569     tegra_slink_writel(tspi, val, SLINK_DMA_CTL);
0570     tspi->dma_control_reg = val;
0571 
0572     if (tspi->cur_direction & DATA_DIR_TX)
0573         cur_words = tegra_slink_fill_tx_fifo_from_client_txbuf(tspi, t);
0574     else
0575         cur_words = tspi->curr_dma_words;
0576     val |= SLINK_DMA_BLOCK_SIZE(cur_words - 1);
0577     tegra_slink_writel(tspi, val, SLINK_DMA_CTL);
0578     tspi->dma_control_reg = val;
0579 
0580     tspi->is_curr_dma_xfer = false;
0581     if (tspi->is_packed) {
0582         val |= SLINK_PACKED;
0583         tegra_slink_writel(tspi, val, SLINK_DMA_CTL);
0584         udelay(1);
0585         wmb();
0586     }
0587     tspi->dma_control_reg = val;
0588     val |= SLINK_DMA_EN;
0589     tegra_slink_writel(tspi, val, SLINK_DMA_CTL);
0590     return 0;
0591 }
0592 
0593 static int tegra_slink_init_dma_param(struct tegra_slink_data *tspi,
0594             bool dma_to_memory)
0595 {
0596     struct dma_chan *dma_chan;
0597     u32 *dma_buf;
0598     dma_addr_t dma_phys;
0599     int ret;
0600     struct dma_slave_config dma_sconfig;
0601 
0602     dma_chan = dma_request_chan(tspi->dev, dma_to_memory ? "rx" : "tx");
0603     if (IS_ERR(dma_chan))
0604         return dev_err_probe(tspi->dev, PTR_ERR(dma_chan),
0605                      "Dma channel is not available\n");
0606 
0607     dma_buf = dma_alloc_coherent(tspi->dev, tspi->dma_buf_size,
0608                 &dma_phys, GFP_KERNEL);
0609     if (!dma_buf) {
0610         dev_err(tspi->dev, " Not able to allocate the dma buffer\n");
0611         dma_release_channel(dma_chan);
0612         return -ENOMEM;
0613     }
0614 
0615     if (dma_to_memory) {
0616         dma_sconfig.src_addr = tspi->phys + SLINK_RX_FIFO;
0617         dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
0618         dma_sconfig.src_maxburst = 0;
0619     } else {
0620         dma_sconfig.dst_addr = tspi->phys + SLINK_TX_FIFO;
0621         dma_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
0622         dma_sconfig.dst_maxburst = 0;
0623     }
0624 
0625     ret = dmaengine_slave_config(dma_chan, &dma_sconfig);
0626     if (ret)
0627         goto scrub;
0628     if (dma_to_memory) {
0629         tspi->rx_dma_chan = dma_chan;
0630         tspi->rx_dma_buf = dma_buf;
0631         tspi->rx_dma_phys = dma_phys;
0632     } else {
0633         tspi->tx_dma_chan = dma_chan;
0634         tspi->tx_dma_buf = dma_buf;
0635         tspi->tx_dma_phys = dma_phys;
0636     }
0637     return 0;
0638 
0639 scrub:
0640     dma_free_coherent(tspi->dev, tspi->dma_buf_size, dma_buf, dma_phys);
0641     dma_release_channel(dma_chan);
0642     return ret;
0643 }
0644 
0645 static void tegra_slink_deinit_dma_param(struct tegra_slink_data *tspi,
0646     bool dma_to_memory)
0647 {
0648     u32 *dma_buf;
0649     dma_addr_t dma_phys;
0650     struct dma_chan *dma_chan;
0651 
0652     if (dma_to_memory) {
0653         dma_buf = tspi->rx_dma_buf;
0654         dma_chan = tspi->rx_dma_chan;
0655         dma_phys = tspi->rx_dma_phys;
0656         tspi->rx_dma_chan = NULL;
0657         tspi->rx_dma_buf = NULL;
0658     } else {
0659         dma_buf = tspi->tx_dma_buf;
0660         dma_chan = tspi->tx_dma_chan;
0661         dma_phys = tspi->tx_dma_phys;
0662         tspi->tx_dma_buf = NULL;
0663         tspi->tx_dma_chan = NULL;
0664     }
0665     if (!dma_chan)
0666         return;
0667 
0668     dma_free_coherent(tspi->dev, tspi->dma_buf_size, dma_buf, dma_phys);
0669     dma_release_channel(dma_chan);
0670 }
0671 
0672 static int tegra_slink_start_transfer_one(struct spi_device *spi,
0673         struct spi_transfer *t)
0674 {
0675     struct tegra_slink_data *tspi = spi_master_get_devdata(spi->master);
0676     u32 speed;
0677     u8 bits_per_word;
0678     unsigned total_fifo_words;
0679     int ret;
0680     u32 command;
0681     u32 command2;
0682 
0683     bits_per_word = t->bits_per_word;
0684     speed = t->speed_hz;
0685     if (speed != tspi->cur_speed) {
0686         dev_pm_opp_set_rate(tspi->dev, speed * 4);
0687         tspi->cur_speed = speed;
0688     }
0689 
0690     tspi->cur_spi = spi;
0691     tspi->cur_pos = 0;
0692     tspi->cur_rx_pos = 0;
0693     tspi->cur_tx_pos = 0;
0694     tspi->curr_xfer = t;
0695     total_fifo_words = tegra_slink_calculate_curr_xfer_param(spi, tspi, t);
0696 
0697     command = tspi->command_reg;
0698     command &= ~SLINK_BIT_LENGTH(~0);
0699     command |= SLINK_BIT_LENGTH(bits_per_word - 1);
0700 
0701     command2 = tspi->command2_reg;
0702     command2 &= ~(SLINK_RXEN | SLINK_TXEN);
0703 
0704     tspi->cur_direction = 0;
0705     if (t->rx_buf) {
0706         command2 |= SLINK_RXEN;
0707         tspi->cur_direction |= DATA_DIR_RX;
0708     }
0709     if (t->tx_buf) {
0710         command2 |= SLINK_TXEN;
0711         tspi->cur_direction |= DATA_DIR_TX;
0712     }
0713 
0714     /*
0715      * Writing to the command2 register bevore the command register prevents
0716      * a spike in chip_select line 0. This selects the chip_select line
0717      * before changing the chip_select value.
0718      */
0719     tegra_slink_writel(tspi, command2, SLINK_COMMAND2);
0720     tspi->command2_reg = command2;
0721 
0722     tegra_slink_writel(tspi, command, SLINK_COMMAND);
0723     tspi->command_reg = command;
0724 
0725     if (total_fifo_words > SLINK_FIFO_DEPTH)
0726         ret = tegra_slink_start_dma_based_transfer(tspi, t);
0727     else
0728         ret = tegra_slink_start_cpu_based_transfer(tspi, t);
0729     return ret;
0730 }
0731 
0732 static int tegra_slink_setup(struct spi_device *spi)
0733 {
0734     static const u32 cs_pol_bit[MAX_CHIP_SELECT] = {
0735             SLINK_CS_POLARITY,
0736             SLINK_CS_POLARITY1,
0737             SLINK_CS_POLARITY2,
0738             SLINK_CS_POLARITY3,
0739     };
0740 
0741     struct tegra_slink_data *tspi = spi_master_get_devdata(spi->master);
0742     u32 val;
0743     unsigned long flags;
0744     int ret;
0745 
0746     dev_dbg(&spi->dev, "setup %d bpw, %scpol, %scpha, %dHz\n",
0747         spi->bits_per_word,
0748         spi->mode & SPI_CPOL ? "" : "~",
0749         spi->mode & SPI_CPHA ? "" : "~",
0750         spi->max_speed_hz);
0751 
0752     ret = pm_runtime_resume_and_get(tspi->dev);
0753     if (ret < 0) {
0754         dev_err(tspi->dev, "pm runtime failed, e = %d\n", ret);
0755         return ret;
0756     }
0757 
0758     spin_lock_irqsave(&tspi->lock, flags);
0759     val = tspi->def_command_reg;
0760     if (spi->mode & SPI_CS_HIGH)
0761         val |= cs_pol_bit[spi->chip_select];
0762     else
0763         val &= ~cs_pol_bit[spi->chip_select];
0764     tspi->def_command_reg = val;
0765     tegra_slink_writel(tspi, tspi->def_command_reg, SLINK_COMMAND);
0766     spin_unlock_irqrestore(&tspi->lock, flags);
0767 
0768     pm_runtime_put(tspi->dev);
0769     return 0;
0770 }
0771 
0772 static int tegra_slink_prepare_message(struct spi_master *master,
0773                        struct spi_message *msg)
0774 {
0775     struct tegra_slink_data *tspi = spi_master_get_devdata(master);
0776     struct spi_device *spi = msg->spi;
0777 
0778     tegra_slink_clear_status(tspi);
0779 
0780     tspi->command_reg = tspi->def_command_reg;
0781     tspi->command_reg |= SLINK_CS_SW | SLINK_CS_VALUE;
0782 
0783     tspi->command2_reg = tspi->def_command2_reg;
0784     tspi->command2_reg |= SLINK_SS_EN_CS(spi->chip_select);
0785 
0786     tspi->command_reg &= ~SLINK_MODES;
0787     if (spi->mode & SPI_CPHA)
0788         tspi->command_reg |= SLINK_CK_SDA;
0789 
0790     if (spi->mode & SPI_CPOL)
0791         tspi->command_reg |= SLINK_IDLE_SCLK_DRIVE_HIGH;
0792     else
0793         tspi->command_reg |= SLINK_IDLE_SCLK_DRIVE_LOW;
0794 
0795     return 0;
0796 }
0797 
0798 static int tegra_slink_transfer_one(struct spi_master *master,
0799                     struct spi_device *spi,
0800                     struct spi_transfer *xfer)
0801 {
0802     struct tegra_slink_data *tspi = spi_master_get_devdata(master);
0803     int ret;
0804 
0805     reinit_completion(&tspi->xfer_completion);
0806     ret = tegra_slink_start_transfer_one(spi, xfer);
0807     if (ret < 0) {
0808         dev_err(tspi->dev,
0809             "spi can not start transfer, err %d\n", ret);
0810         return ret;
0811     }
0812 
0813     ret = wait_for_completion_timeout(&tspi->xfer_completion,
0814                       SLINK_DMA_TIMEOUT);
0815     if (WARN_ON(ret == 0)) {
0816         dev_err(tspi->dev,
0817             "spi transfer timeout, err %d\n", ret);
0818         return -EIO;
0819     }
0820 
0821     if (tspi->tx_status)
0822         return tspi->tx_status;
0823     if (tspi->rx_status)
0824         return tspi->rx_status;
0825 
0826     return 0;
0827 }
0828 
0829 static int tegra_slink_unprepare_message(struct spi_master *master,
0830                      struct spi_message *msg)
0831 {
0832     struct tegra_slink_data *tspi = spi_master_get_devdata(master);
0833 
0834     tegra_slink_writel(tspi, tspi->def_command_reg, SLINK_COMMAND);
0835     tegra_slink_writel(tspi, tspi->def_command2_reg, SLINK_COMMAND2);
0836 
0837     return 0;
0838 }
0839 
0840 static irqreturn_t handle_cpu_based_xfer(struct tegra_slink_data *tspi)
0841 {
0842     struct spi_transfer *t = tspi->curr_xfer;
0843     unsigned long flags;
0844 
0845     spin_lock_irqsave(&tspi->lock, flags);
0846     if (tspi->tx_status ||  tspi->rx_status ||
0847                 (tspi->status_reg & SLINK_BSY)) {
0848         dev_err(tspi->dev,
0849             "CpuXfer ERROR bit set 0x%x\n", tspi->status_reg);
0850         dev_err(tspi->dev,
0851             "CpuXfer 0x%08x:0x%08x:0x%08x\n", tspi->command_reg,
0852                 tspi->command2_reg, tspi->dma_control_reg);
0853         reset_control_assert(tspi->rst);
0854         udelay(2);
0855         reset_control_deassert(tspi->rst);
0856         complete(&tspi->xfer_completion);
0857         goto exit;
0858     }
0859 
0860     if (tspi->cur_direction & DATA_DIR_RX)
0861         tegra_slink_read_rx_fifo_to_client_rxbuf(tspi, t);
0862 
0863     if (tspi->cur_direction & DATA_DIR_TX)
0864         tspi->cur_pos = tspi->cur_tx_pos;
0865     else
0866         tspi->cur_pos = tspi->cur_rx_pos;
0867 
0868     if (tspi->cur_pos == t->len) {
0869         complete(&tspi->xfer_completion);
0870         goto exit;
0871     }
0872 
0873     tegra_slink_calculate_curr_xfer_param(tspi->cur_spi, tspi, t);
0874     tegra_slink_start_cpu_based_transfer(tspi, t);
0875 exit:
0876     spin_unlock_irqrestore(&tspi->lock, flags);
0877     return IRQ_HANDLED;
0878 }
0879 
0880 static irqreturn_t handle_dma_based_xfer(struct tegra_slink_data *tspi)
0881 {
0882     struct spi_transfer *t = tspi->curr_xfer;
0883     long wait_status;
0884     int err = 0;
0885     unsigned total_fifo_words;
0886     unsigned long flags;
0887 
0888     /* Abort dmas if any error */
0889     if (tspi->cur_direction & DATA_DIR_TX) {
0890         if (tspi->tx_status) {
0891             dmaengine_terminate_all(tspi->tx_dma_chan);
0892             err += 1;
0893         } else {
0894             wait_status = wait_for_completion_interruptible_timeout(
0895                 &tspi->tx_dma_complete, SLINK_DMA_TIMEOUT);
0896             if (wait_status <= 0) {
0897                 dmaengine_terminate_all(tspi->tx_dma_chan);
0898                 dev_err(tspi->dev, "TxDma Xfer failed\n");
0899                 err += 1;
0900             }
0901         }
0902     }
0903 
0904     if (tspi->cur_direction & DATA_DIR_RX) {
0905         if (tspi->rx_status) {
0906             dmaengine_terminate_all(tspi->rx_dma_chan);
0907             err += 2;
0908         } else {
0909             wait_status = wait_for_completion_interruptible_timeout(
0910                 &tspi->rx_dma_complete, SLINK_DMA_TIMEOUT);
0911             if (wait_status <= 0) {
0912                 dmaengine_terminate_all(tspi->rx_dma_chan);
0913                 dev_err(tspi->dev, "RxDma Xfer failed\n");
0914                 err += 2;
0915             }
0916         }
0917     }
0918 
0919     spin_lock_irqsave(&tspi->lock, flags);
0920     if (err) {
0921         dev_err(tspi->dev,
0922             "DmaXfer: ERROR bit set 0x%x\n", tspi->status_reg);
0923         dev_err(tspi->dev,
0924             "DmaXfer 0x%08x:0x%08x:0x%08x\n", tspi->command_reg,
0925                 tspi->command2_reg, tspi->dma_control_reg);
0926         reset_control_assert(tspi->rst);
0927         udelay(2);
0928         reset_control_assert(tspi->rst);
0929         complete(&tspi->xfer_completion);
0930         spin_unlock_irqrestore(&tspi->lock, flags);
0931         return IRQ_HANDLED;
0932     }
0933 
0934     if (tspi->cur_direction & DATA_DIR_RX)
0935         tegra_slink_copy_spi_rxbuf_to_client_rxbuf(tspi, t);
0936 
0937     if (tspi->cur_direction & DATA_DIR_TX)
0938         tspi->cur_pos = tspi->cur_tx_pos;
0939     else
0940         tspi->cur_pos = tspi->cur_rx_pos;
0941 
0942     if (tspi->cur_pos == t->len) {
0943         complete(&tspi->xfer_completion);
0944         goto exit;
0945     }
0946 
0947     /* Continue transfer in current message */
0948     total_fifo_words = tegra_slink_calculate_curr_xfer_param(tspi->cur_spi,
0949                             tspi, t);
0950     if (total_fifo_words > SLINK_FIFO_DEPTH)
0951         err = tegra_slink_start_dma_based_transfer(tspi, t);
0952     else
0953         err = tegra_slink_start_cpu_based_transfer(tspi, t);
0954 
0955 exit:
0956     spin_unlock_irqrestore(&tspi->lock, flags);
0957     return IRQ_HANDLED;
0958 }
0959 
0960 static irqreturn_t tegra_slink_isr_thread(int irq, void *context_data)
0961 {
0962     struct tegra_slink_data *tspi = context_data;
0963 
0964     if (!tspi->is_curr_dma_xfer)
0965         return handle_cpu_based_xfer(tspi);
0966     return handle_dma_based_xfer(tspi);
0967 }
0968 
0969 static irqreturn_t tegra_slink_isr(int irq, void *context_data)
0970 {
0971     struct tegra_slink_data *tspi = context_data;
0972 
0973     tspi->status_reg = tegra_slink_readl(tspi, SLINK_STATUS);
0974     if (tspi->cur_direction & DATA_DIR_TX)
0975         tspi->tx_status = tspi->status_reg &
0976                     (SLINK_TX_OVF | SLINK_TX_UNF);
0977 
0978     if (tspi->cur_direction & DATA_DIR_RX)
0979         tspi->rx_status = tspi->status_reg &
0980                     (SLINK_RX_OVF | SLINK_RX_UNF);
0981     tegra_slink_clear_status(tspi);
0982 
0983     return IRQ_WAKE_THREAD;
0984 }
0985 
0986 static const struct tegra_slink_chip_data tegra30_spi_cdata = {
0987     .cs_hold_time = true,
0988 };
0989 
0990 static const struct tegra_slink_chip_data tegra20_spi_cdata = {
0991     .cs_hold_time = false,
0992 };
0993 
0994 static const struct of_device_id tegra_slink_of_match[] = {
0995     { .compatible = "nvidia,tegra30-slink", .data = &tegra30_spi_cdata, },
0996     { .compatible = "nvidia,tegra20-slink", .data = &tegra20_spi_cdata, },
0997     {}
0998 };
0999 MODULE_DEVICE_TABLE(of, tegra_slink_of_match);
1000 
1001 static int tegra_slink_probe(struct platform_device *pdev)
1002 {
1003     struct spi_master   *master;
1004     struct tegra_slink_data *tspi;
1005     struct resource     *r;
1006     int ret, spi_irq;
1007     const struct tegra_slink_chip_data *cdata = NULL;
1008 
1009     cdata = of_device_get_match_data(&pdev->dev);
1010 
1011     master = spi_alloc_master(&pdev->dev, sizeof(*tspi));
1012     if (!master) {
1013         dev_err(&pdev->dev, "master allocation failed\n");
1014         return -ENOMEM;
1015     }
1016 
1017     /* the spi->mode bits understood by this driver: */
1018     master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1019     master->setup = tegra_slink_setup;
1020     master->prepare_message = tegra_slink_prepare_message;
1021     master->transfer_one = tegra_slink_transfer_one;
1022     master->unprepare_message = tegra_slink_unprepare_message;
1023     master->auto_runtime_pm = true;
1024     master->num_chipselect = MAX_CHIP_SELECT;
1025 
1026     platform_set_drvdata(pdev, master);
1027     tspi = spi_master_get_devdata(master);
1028     tspi->master = master;
1029     tspi->dev = &pdev->dev;
1030     tspi->chip_data = cdata;
1031     spin_lock_init(&tspi->lock);
1032 
1033     if (of_property_read_u32(tspi->dev->of_node, "spi-max-frequency",
1034                  &master->max_speed_hz))
1035         master->max_speed_hz = 25000000; /* 25MHz */
1036 
1037     r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1038     if (!r) {
1039         dev_err(&pdev->dev, "No IO memory resource\n");
1040         ret = -ENODEV;
1041         goto exit_free_master;
1042     }
1043     tspi->phys = r->start;
1044     tspi->base = devm_ioremap_resource(&pdev->dev, r);
1045     if (IS_ERR(tspi->base)) {
1046         ret = PTR_ERR(tspi->base);
1047         goto exit_free_master;
1048     }
1049 
1050     /* disabled clock may cause interrupt storm upon request */
1051     tspi->clk = devm_clk_get(&pdev->dev, NULL);
1052     if (IS_ERR(tspi->clk)) {
1053         ret = PTR_ERR(tspi->clk);
1054         dev_err(&pdev->dev, "Can not get clock %d\n", ret);
1055         goto exit_free_master;
1056     }
1057 
1058     tspi->rst = devm_reset_control_get_exclusive(&pdev->dev, "spi");
1059     if (IS_ERR(tspi->rst)) {
1060         dev_err(&pdev->dev, "can not get reset\n");
1061         ret = PTR_ERR(tspi->rst);
1062         goto exit_free_master;
1063     }
1064 
1065     ret = devm_tegra_core_dev_init_opp_table_common(&pdev->dev);
1066     if (ret)
1067         goto exit_free_master;
1068 
1069     tspi->max_buf_size = SLINK_FIFO_DEPTH << 2;
1070     tspi->dma_buf_size = DEFAULT_SPI_DMA_BUF_LEN;
1071 
1072     ret = tegra_slink_init_dma_param(tspi, true);
1073     if (ret < 0)
1074         goto exit_free_master;
1075     ret = tegra_slink_init_dma_param(tspi, false);
1076     if (ret < 0)
1077         goto exit_rx_dma_free;
1078     tspi->max_buf_size = tspi->dma_buf_size;
1079     init_completion(&tspi->tx_dma_complete);
1080     init_completion(&tspi->rx_dma_complete);
1081 
1082     init_completion(&tspi->xfer_completion);
1083 
1084     pm_runtime_enable(&pdev->dev);
1085     ret = pm_runtime_resume_and_get(&pdev->dev);
1086     if (ret) {
1087         dev_err(&pdev->dev, "pm runtime get failed, e = %d\n", ret);
1088         goto exit_pm_disable;
1089     }
1090 
1091     reset_control_assert(tspi->rst);
1092     udelay(2);
1093     reset_control_deassert(tspi->rst);
1094 
1095     spi_irq = platform_get_irq(pdev, 0);
1096     tspi->irq = spi_irq;
1097     ret = request_threaded_irq(tspi->irq, tegra_slink_isr,
1098                    tegra_slink_isr_thread, IRQF_ONESHOT,
1099                    dev_name(&pdev->dev), tspi);
1100     if (ret < 0) {
1101         dev_err(&pdev->dev, "Failed to register ISR for IRQ %d\n",
1102             tspi->irq);
1103         goto exit_pm_put;
1104     }
1105 
1106     tspi->def_command_reg  = SLINK_M_S;
1107     tspi->def_command2_reg = SLINK_CS_ACTIVE_BETWEEN;
1108     tegra_slink_writel(tspi, tspi->def_command_reg, SLINK_COMMAND);
1109     tegra_slink_writel(tspi, tspi->def_command2_reg, SLINK_COMMAND2);
1110 
1111     master->dev.of_node = pdev->dev.of_node;
1112     ret = spi_register_master(master);
1113     if (ret < 0) {
1114         dev_err(&pdev->dev, "can not register to master err %d\n", ret);
1115         goto exit_free_irq;
1116     }
1117 
1118     pm_runtime_put(&pdev->dev);
1119 
1120     return ret;
1121 
1122 exit_free_irq:
1123     free_irq(spi_irq, tspi);
1124 exit_pm_put:
1125     pm_runtime_put(&pdev->dev);
1126 exit_pm_disable:
1127     pm_runtime_force_suspend(&pdev->dev);
1128 
1129     tegra_slink_deinit_dma_param(tspi, false);
1130 exit_rx_dma_free:
1131     tegra_slink_deinit_dma_param(tspi, true);
1132 exit_free_master:
1133     spi_master_put(master);
1134     return ret;
1135 }
1136 
1137 static int tegra_slink_remove(struct platform_device *pdev)
1138 {
1139     struct spi_master *master = spi_master_get(platform_get_drvdata(pdev));
1140     struct tegra_slink_data *tspi = spi_master_get_devdata(master);
1141 
1142     spi_unregister_master(master);
1143 
1144     free_irq(tspi->irq, tspi);
1145 
1146     pm_runtime_force_suspend(&pdev->dev);
1147 
1148     if (tspi->tx_dma_chan)
1149         tegra_slink_deinit_dma_param(tspi, false);
1150 
1151     if (tspi->rx_dma_chan)
1152         tegra_slink_deinit_dma_param(tspi, true);
1153 
1154     spi_master_put(master);
1155     return 0;
1156 }
1157 
1158 #ifdef CONFIG_PM_SLEEP
1159 static int tegra_slink_suspend(struct device *dev)
1160 {
1161     struct spi_master *master = dev_get_drvdata(dev);
1162 
1163     return spi_master_suspend(master);
1164 }
1165 
1166 static int tegra_slink_resume(struct device *dev)
1167 {
1168     struct spi_master *master = dev_get_drvdata(dev);
1169     struct tegra_slink_data *tspi = spi_master_get_devdata(master);
1170     int ret;
1171 
1172     ret = pm_runtime_resume_and_get(dev);
1173     if (ret < 0) {
1174         dev_err(dev, "pm runtime failed, e = %d\n", ret);
1175         return ret;
1176     }
1177     tegra_slink_writel(tspi, tspi->command_reg, SLINK_COMMAND);
1178     tegra_slink_writel(tspi, tspi->command2_reg, SLINK_COMMAND2);
1179     pm_runtime_put(dev);
1180 
1181     return spi_master_resume(master);
1182 }
1183 #endif
1184 
1185 static int __maybe_unused tegra_slink_runtime_suspend(struct device *dev)
1186 {
1187     struct spi_master *master = dev_get_drvdata(dev);
1188     struct tegra_slink_data *tspi = spi_master_get_devdata(master);
1189 
1190     /* Flush all write which are in PPSB queue by reading back */
1191     tegra_slink_readl(tspi, SLINK_MAS_DATA);
1192 
1193     clk_disable_unprepare(tspi->clk);
1194     return 0;
1195 }
1196 
1197 static int __maybe_unused tegra_slink_runtime_resume(struct device *dev)
1198 {
1199     struct spi_master *master = dev_get_drvdata(dev);
1200     struct tegra_slink_data *tspi = spi_master_get_devdata(master);
1201     int ret;
1202 
1203     ret = clk_prepare_enable(tspi->clk);
1204     if (ret < 0) {
1205         dev_err(tspi->dev, "clk_prepare failed: %d\n", ret);
1206         return ret;
1207     }
1208     return 0;
1209 }
1210 
1211 static const struct dev_pm_ops slink_pm_ops = {
1212     SET_RUNTIME_PM_OPS(tegra_slink_runtime_suspend,
1213         tegra_slink_runtime_resume, NULL)
1214     SET_SYSTEM_SLEEP_PM_OPS(tegra_slink_suspend, tegra_slink_resume)
1215 };
1216 static struct platform_driver tegra_slink_driver = {
1217     .driver = {
1218         .name       = "spi-tegra-slink",
1219         .pm     = &slink_pm_ops,
1220         .of_match_table = tegra_slink_of_match,
1221     },
1222     .probe =    tegra_slink_probe,
1223     .remove =   tegra_slink_remove,
1224 };
1225 module_platform_driver(tegra_slink_driver);
1226 
1227 MODULE_ALIAS("platform:spi-tegra-slink");
1228 MODULE_DESCRIPTION("NVIDIA Tegra20/Tegra30 SLINK Controller Driver");
1229 MODULE_AUTHOR("Laxman Dewangan <ldewangan@nvidia.com>");
1230 MODULE_LICENSE("GPL v2");
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