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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * SPI driver for Nvidia's Tegra20 Serial Flash Controller.
0004  *
0005  * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
0006  *
0007  * Author: Laxman Dewangan <ldewangan@nvidia.com>
0008  */
0009 
0010 #include <linux/clk.h>
0011 #include <linux/completion.h>
0012 #include <linux/delay.h>
0013 #include <linux/err.h>
0014 #include <linux/interrupt.h>
0015 #include <linux/io.h>
0016 #include <linux/kernel.h>
0017 #include <linux/kthread.h>
0018 #include <linux/module.h>
0019 #include <linux/platform_device.h>
0020 #include <linux/pm_runtime.h>
0021 #include <linux/of.h>
0022 #include <linux/of_device.h>
0023 #include <linux/reset.h>
0024 #include <linux/spi/spi.h>
0025 
0026 #define SPI_COMMAND             0x000
0027 #define SPI_GO                  BIT(30)
0028 #define SPI_M_S                 BIT(28)
0029 #define SPI_ACTIVE_SCLK_MASK            (0x3 << 26)
0030 #define SPI_ACTIVE_SCLK_DRIVE_LOW       (0 << 26)
0031 #define SPI_ACTIVE_SCLK_DRIVE_HIGH      (1 << 26)
0032 #define SPI_ACTIVE_SCLK_PULL_LOW        (2 << 26)
0033 #define SPI_ACTIVE_SCLK_PULL_HIGH       (3 << 26)
0034 
0035 #define SPI_CK_SDA_FALLING          (1 << 21)
0036 #define SPI_CK_SDA_RISING           (0 << 21)
0037 #define SPI_CK_SDA_MASK             (1 << 21)
0038 #define SPI_ACTIVE_SDA              (0x3 << 18)
0039 #define SPI_ACTIVE_SDA_DRIVE_LOW        (0 << 18)
0040 #define SPI_ACTIVE_SDA_DRIVE_HIGH       (1 << 18)
0041 #define SPI_ACTIVE_SDA_PULL_LOW         (2 << 18)
0042 #define SPI_ACTIVE_SDA_PULL_HIGH        (3 << 18)
0043 
0044 #define SPI_CS_POL_INVERT           BIT(16)
0045 #define SPI_TX_EN               BIT(15)
0046 #define SPI_RX_EN               BIT(14)
0047 #define SPI_CS_VAL_HIGH             BIT(13)
0048 #define SPI_CS_VAL_LOW              0x0
0049 #define SPI_CS_SW               BIT(12)
0050 #define SPI_CS_HW               0x0
0051 #define SPI_CS_DELAY_MASK           (7 << 9)
0052 #define SPI_CS3_EN              BIT(8)
0053 #define SPI_CS2_EN              BIT(7)
0054 #define SPI_CS1_EN              BIT(6)
0055 #define SPI_CS0_EN              BIT(5)
0056 
0057 #define SPI_CS_MASK         (SPI_CS3_EN | SPI_CS2_EN |  \
0058                     SPI_CS1_EN | SPI_CS0_EN)
0059 #define SPI_BIT_LENGTH(x)       (((x) & 0x1f) << 0)
0060 
0061 #define SPI_MODES           (SPI_ACTIVE_SCLK_MASK | SPI_CK_SDA_MASK)
0062 
0063 #define SPI_STATUS          0x004
0064 #define SPI_BSY             BIT(31)
0065 #define SPI_RDY             BIT(30)
0066 #define SPI_TXF_FLUSH           BIT(29)
0067 #define SPI_RXF_FLUSH           BIT(28)
0068 #define SPI_RX_UNF          BIT(27)
0069 #define SPI_TX_OVF          BIT(26)
0070 #define SPI_RXF_EMPTY           BIT(25)
0071 #define SPI_RXF_FULL            BIT(24)
0072 #define SPI_TXF_EMPTY           BIT(23)
0073 #define SPI_TXF_FULL            BIT(22)
0074 #define SPI_BLK_CNT(count)      (((count) & 0xffff) + 1)
0075 
0076 #define SPI_FIFO_ERROR          (SPI_RX_UNF | SPI_TX_OVF)
0077 #define SPI_FIFO_EMPTY          (SPI_TX_EMPTY | SPI_RX_EMPTY)
0078 
0079 #define SPI_RX_CMP          0x8
0080 #define SPI_DMA_CTL         0x0C
0081 #define SPI_DMA_EN          BIT(31)
0082 #define SPI_IE_RXC          BIT(27)
0083 #define SPI_IE_TXC          BIT(26)
0084 #define SPI_PACKED          BIT(20)
0085 #define SPI_RX_TRIG_MASK        (0x3 << 18)
0086 #define SPI_RX_TRIG_1W          (0x0 << 18)
0087 #define SPI_RX_TRIG_4W          (0x1 << 18)
0088 #define SPI_TX_TRIG_MASK        (0x3 << 16)
0089 #define SPI_TX_TRIG_1W          (0x0 << 16)
0090 #define SPI_TX_TRIG_4W          (0x1 << 16)
0091 #define SPI_DMA_BLK_COUNT(count)    (((count) - 1) & 0xFFFF)
0092 
0093 #define SPI_TX_FIFO         0x10
0094 #define SPI_RX_FIFO         0x20
0095 
0096 #define DATA_DIR_TX         (1 << 0)
0097 #define DATA_DIR_RX         (1 << 1)
0098 
0099 #define MAX_CHIP_SELECT         4
0100 #define SPI_FIFO_DEPTH          4
0101 #define SPI_DMA_TIMEOUT               (msecs_to_jiffies(1000))
0102 
0103 struct tegra_sflash_data {
0104     struct device               *dev;
0105     struct spi_master           *master;
0106     spinlock_t              lock;
0107 
0108     struct clk              *clk;
0109     struct reset_control            *rst;
0110     void __iomem                *base;
0111     unsigned                irq;
0112     u32                 cur_speed;
0113 
0114     struct spi_device           *cur_spi;
0115     unsigned                cur_pos;
0116     unsigned                cur_len;
0117     unsigned                bytes_per_word;
0118     unsigned                cur_direction;
0119     unsigned                curr_xfer_words;
0120 
0121     unsigned                cur_rx_pos;
0122     unsigned                cur_tx_pos;
0123 
0124     u32                 tx_status;
0125     u32                 rx_status;
0126     u32                 status_reg;
0127 
0128     u32                 def_command_reg;
0129     u32                 command_reg;
0130     u32                 dma_control_reg;
0131 
0132     struct completion           xfer_completion;
0133     struct spi_transfer         *curr_xfer;
0134 };
0135 
0136 static int tegra_sflash_runtime_suspend(struct device *dev);
0137 static int tegra_sflash_runtime_resume(struct device *dev);
0138 
0139 static inline u32 tegra_sflash_readl(struct tegra_sflash_data *tsd,
0140         unsigned long reg)
0141 {
0142     return readl(tsd->base + reg);
0143 }
0144 
0145 static inline void tegra_sflash_writel(struct tegra_sflash_data *tsd,
0146         u32 val, unsigned long reg)
0147 {
0148     writel(val, tsd->base + reg);
0149 }
0150 
0151 static void tegra_sflash_clear_status(struct tegra_sflash_data *tsd)
0152 {
0153     /* Write 1 to clear status register */
0154     tegra_sflash_writel(tsd, SPI_RDY | SPI_FIFO_ERROR, SPI_STATUS);
0155 }
0156 
0157 static unsigned tegra_sflash_calculate_curr_xfer_param(
0158     struct spi_device *spi, struct tegra_sflash_data *tsd,
0159     struct spi_transfer *t)
0160 {
0161     unsigned remain_len = t->len - tsd->cur_pos;
0162     unsigned max_word;
0163 
0164     tsd->bytes_per_word = DIV_ROUND_UP(t->bits_per_word, 8);
0165     max_word = remain_len / tsd->bytes_per_word;
0166     if (max_word > SPI_FIFO_DEPTH)
0167         max_word = SPI_FIFO_DEPTH;
0168     tsd->curr_xfer_words = max_word;
0169     return max_word;
0170 }
0171 
0172 static unsigned tegra_sflash_fill_tx_fifo_from_client_txbuf(
0173     struct tegra_sflash_data *tsd, struct spi_transfer *t)
0174 {
0175     unsigned nbytes;
0176     u32 status;
0177     unsigned max_n_32bit = tsd->curr_xfer_words;
0178     u8 *tx_buf = (u8 *)t->tx_buf + tsd->cur_tx_pos;
0179 
0180     if (max_n_32bit > SPI_FIFO_DEPTH)
0181         max_n_32bit = SPI_FIFO_DEPTH;
0182     nbytes = max_n_32bit * tsd->bytes_per_word;
0183 
0184     status = tegra_sflash_readl(tsd, SPI_STATUS);
0185     while (!(status & SPI_TXF_FULL)) {
0186         int i;
0187         u32 x = 0;
0188 
0189         for (i = 0; nbytes && (i < tsd->bytes_per_word);
0190                             i++, nbytes--)
0191             x |= (u32)(*tx_buf++) << (i * 8);
0192         tegra_sflash_writel(tsd, x, SPI_TX_FIFO);
0193         if (!nbytes)
0194             break;
0195 
0196         status = tegra_sflash_readl(tsd, SPI_STATUS);
0197     }
0198     tsd->cur_tx_pos += max_n_32bit * tsd->bytes_per_word;
0199     return max_n_32bit;
0200 }
0201 
0202 static int tegra_sflash_read_rx_fifo_to_client_rxbuf(
0203         struct tegra_sflash_data *tsd, struct spi_transfer *t)
0204 {
0205     u32 status;
0206     unsigned int read_words = 0;
0207     u8 *rx_buf = (u8 *)t->rx_buf + tsd->cur_rx_pos;
0208 
0209     status = tegra_sflash_readl(tsd, SPI_STATUS);
0210     while (!(status & SPI_RXF_EMPTY)) {
0211         int i;
0212         u32 x = tegra_sflash_readl(tsd, SPI_RX_FIFO);
0213 
0214         for (i = 0; (i < tsd->bytes_per_word); i++)
0215             *rx_buf++ = (x >> (i*8)) & 0xFF;
0216         read_words++;
0217         status = tegra_sflash_readl(tsd, SPI_STATUS);
0218     }
0219     tsd->cur_rx_pos += read_words * tsd->bytes_per_word;
0220     return 0;
0221 }
0222 
0223 static int tegra_sflash_start_cpu_based_transfer(
0224         struct tegra_sflash_data *tsd, struct spi_transfer *t)
0225 {
0226     u32 val = 0;
0227     unsigned cur_words;
0228 
0229     if (tsd->cur_direction & DATA_DIR_TX)
0230         val |= SPI_IE_TXC;
0231 
0232     if (tsd->cur_direction & DATA_DIR_RX)
0233         val |= SPI_IE_RXC;
0234 
0235     tegra_sflash_writel(tsd, val, SPI_DMA_CTL);
0236     tsd->dma_control_reg = val;
0237 
0238     if (tsd->cur_direction & DATA_DIR_TX)
0239         cur_words = tegra_sflash_fill_tx_fifo_from_client_txbuf(tsd, t);
0240     else
0241         cur_words = tsd->curr_xfer_words;
0242     val |= SPI_DMA_BLK_COUNT(cur_words);
0243     tegra_sflash_writel(tsd, val, SPI_DMA_CTL);
0244     tsd->dma_control_reg = val;
0245     val |= SPI_DMA_EN;
0246     tegra_sflash_writel(tsd, val, SPI_DMA_CTL);
0247     return 0;
0248 }
0249 
0250 static int tegra_sflash_start_transfer_one(struct spi_device *spi,
0251         struct spi_transfer *t, bool is_first_of_msg,
0252         bool is_single_xfer)
0253 {
0254     struct tegra_sflash_data *tsd = spi_master_get_devdata(spi->master);
0255     u32 speed;
0256     u32 command;
0257 
0258     speed = t->speed_hz;
0259     if (speed != tsd->cur_speed) {
0260         clk_set_rate(tsd->clk, speed);
0261         tsd->cur_speed = speed;
0262     }
0263 
0264     tsd->cur_spi = spi;
0265     tsd->cur_pos = 0;
0266     tsd->cur_rx_pos = 0;
0267     tsd->cur_tx_pos = 0;
0268     tsd->curr_xfer = t;
0269     tegra_sflash_calculate_curr_xfer_param(spi, tsd, t);
0270     if (is_first_of_msg) {
0271         command = tsd->def_command_reg;
0272         command |= SPI_BIT_LENGTH(t->bits_per_word - 1);
0273         command |= SPI_CS_VAL_HIGH;
0274 
0275         command &= ~SPI_MODES;
0276         if (spi->mode & SPI_CPHA)
0277             command |= SPI_CK_SDA_FALLING;
0278 
0279         if (spi->mode & SPI_CPOL)
0280             command |= SPI_ACTIVE_SCLK_DRIVE_HIGH;
0281         else
0282             command |= SPI_ACTIVE_SCLK_DRIVE_LOW;
0283         command |= SPI_CS0_EN << spi->chip_select;
0284     } else {
0285         command = tsd->command_reg;
0286         command &= ~SPI_BIT_LENGTH(~0);
0287         command |= SPI_BIT_LENGTH(t->bits_per_word - 1);
0288         command &= ~(SPI_RX_EN | SPI_TX_EN);
0289     }
0290 
0291     tsd->cur_direction = 0;
0292     if (t->rx_buf) {
0293         command |= SPI_RX_EN;
0294         tsd->cur_direction |= DATA_DIR_RX;
0295     }
0296     if (t->tx_buf) {
0297         command |= SPI_TX_EN;
0298         tsd->cur_direction |= DATA_DIR_TX;
0299     }
0300     tegra_sflash_writel(tsd, command, SPI_COMMAND);
0301     tsd->command_reg = command;
0302 
0303     return tegra_sflash_start_cpu_based_transfer(tsd, t);
0304 }
0305 
0306 static int tegra_sflash_transfer_one_message(struct spi_master *master,
0307             struct spi_message *msg)
0308 {
0309     bool is_first_msg = true;
0310     int single_xfer;
0311     struct tegra_sflash_data *tsd = spi_master_get_devdata(master);
0312     struct spi_transfer *xfer;
0313     struct spi_device *spi = msg->spi;
0314     int ret;
0315 
0316     msg->status = 0;
0317     msg->actual_length = 0;
0318     single_xfer = list_is_singular(&msg->transfers);
0319     list_for_each_entry(xfer, &msg->transfers, transfer_list) {
0320         reinit_completion(&tsd->xfer_completion);
0321         ret = tegra_sflash_start_transfer_one(spi, xfer,
0322                     is_first_msg, single_xfer);
0323         if (ret < 0) {
0324             dev_err(tsd->dev,
0325                 "spi can not start transfer, err %d\n", ret);
0326             goto exit;
0327         }
0328         is_first_msg = false;
0329         ret = wait_for_completion_timeout(&tsd->xfer_completion,
0330                         SPI_DMA_TIMEOUT);
0331         if (WARN_ON(ret == 0)) {
0332             dev_err(tsd->dev,
0333                 "spi transfer timeout, err %d\n", ret);
0334             ret = -EIO;
0335             goto exit;
0336         }
0337 
0338         if (tsd->tx_status ||  tsd->rx_status) {
0339             dev_err(tsd->dev, "Error in Transfer\n");
0340             ret = -EIO;
0341             goto exit;
0342         }
0343         msg->actual_length += xfer->len;
0344         if (xfer->cs_change && xfer->delay.value) {
0345             tegra_sflash_writel(tsd, tsd->def_command_reg,
0346                     SPI_COMMAND);
0347             spi_transfer_delay_exec(xfer);
0348         }
0349     }
0350     ret = 0;
0351 exit:
0352     tegra_sflash_writel(tsd, tsd->def_command_reg, SPI_COMMAND);
0353     msg->status = ret;
0354     spi_finalize_current_message(master);
0355     return ret;
0356 }
0357 
0358 static irqreturn_t handle_cpu_based_xfer(struct tegra_sflash_data *tsd)
0359 {
0360     struct spi_transfer *t = tsd->curr_xfer;
0361 
0362     spin_lock(&tsd->lock);
0363     if (tsd->tx_status || tsd->rx_status || (tsd->status_reg & SPI_BSY)) {
0364         dev_err(tsd->dev,
0365             "CpuXfer ERROR bit set 0x%x\n", tsd->status_reg);
0366         dev_err(tsd->dev,
0367             "CpuXfer 0x%08x:0x%08x\n", tsd->command_reg,
0368                 tsd->dma_control_reg);
0369         reset_control_assert(tsd->rst);
0370         udelay(2);
0371         reset_control_deassert(tsd->rst);
0372         complete(&tsd->xfer_completion);
0373         goto exit;
0374     }
0375 
0376     if (tsd->cur_direction & DATA_DIR_RX)
0377         tegra_sflash_read_rx_fifo_to_client_rxbuf(tsd, t);
0378 
0379     if (tsd->cur_direction & DATA_DIR_TX)
0380         tsd->cur_pos = tsd->cur_tx_pos;
0381     else
0382         tsd->cur_pos = tsd->cur_rx_pos;
0383 
0384     if (tsd->cur_pos == t->len) {
0385         complete(&tsd->xfer_completion);
0386         goto exit;
0387     }
0388 
0389     tegra_sflash_calculate_curr_xfer_param(tsd->cur_spi, tsd, t);
0390     tegra_sflash_start_cpu_based_transfer(tsd, t);
0391 exit:
0392     spin_unlock(&tsd->lock);
0393     return IRQ_HANDLED;
0394 }
0395 
0396 static irqreturn_t tegra_sflash_isr(int irq, void *context_data)
0397 {
0398     struct tegra_sflash_data *tsd = context_data;
0399 
0400     tsd->status_reg = tegra_sflash_readl(tsd, SPI_STATUS);
0401     if (tsd->cur_direction & DATA_DIR_TX)
0402         tsd->tx_status = tsd->status_reg & SPI_TX_OVF;
0403 
0404     if (tsd->cur_direction & DATA_DIR_RX)
0405         tsd->rx_status = tsd->status_reg & SPI_RX_UNF;
0406     tegra_sflash_clear_status(tsd);
0407 
0408     return handle_cpu_based_xfer(tsd);
0409 }
0410 
0411 static const struct of_device_id tegra_sflash_of_match[] = {
0412     { .compatible = "nvidia,tegra20-sflash", },
0413     {}
0414 };
0415 MODULE_DEVICE_TABLE(of, tegra_sflash_of_match);
0416 
0417 static int tegra_sflash_probe(struct platform_device *pdev)
0418 {
0419     struct spi_master   *master;
0420     struct tegra_sflash_data    *tsd;
0421     int ret;
0422     const struct of_device_id *match;
0423 
0424     match = of_match_device(tegra_sflash_of_match, &pdev->dev);
0425     if (!match) {
0426         dev_err(&pdev->dev, "Error: No device match found\n");
0427         return -ENODEV;
0428     }
0429 
0430     master = spi_alloc_master(&pdev->dev, sizeof(*tsd));
0431     if (!master) {
0432         dev_err(&pdev->dev, "master allocation failed\n");
0433         return -ENOMEM;
0434     }
0435 
0436     /* the spi->mode bits understood by this driver: */
0437     master->mode_bits = SPI_CPOL | SPI_CPHA;
0438     master->transfer_one_message = tegra_sflash_transfer_one_message;
0439     master->auto_runtime_pm = true;
0440     master->num_chipselect = MAX_CHIP_SELECT;
0441 
0442     platform_set_drvdata(pdev, master);
0443     tsd = spi_master_get_devdata(master);
0444     tsd->master = master;
0445     tsd->dev = &pdev->dev;
0446     spin_lock_init(&tsd->lock);
0447 
0448     if (of_property_read_u32(tsd->dev->of_node, "spi-max-frequency",
0449                  &master->max_speed_hz))
0450         master->max_speed_hz = 25000000; /* 25MHz */
0451 
0452     tsd->base = devm_platform_ioremap_resource(pdev, 0);
0453     if (IS_ERR(tsd->base)) {
0454         ret = PTR_ERR(tsd->base);
0455         goto exit_free_master;
0456     }
0457 
0458     tsd->irq = platform_get_irq(pdev, 0);
0459     ret = request_irq(tsd->irq, tegra_sflash_isr, 0,
0460             dev_name(&pdev->dev), tsd);
0461     if (ret < 0) {
0462         dev_err(&pdev->dev, "Failed to register ISR for IRQ %d\n",
0463                     tsd->irq);
0464         goto exit_free_master;
0465     }
0466 
0467     tsd->clk = devm_clk_get(&pdev->dev, NULL);
0468     if (IS_ERR(tsd->clk)) {
0469         dev_err(&pdev->dev, "can not get clock\n");
0470         ret = PTR_ERR(tsd->clk);
0471         goto exit_free_irq;
0472     }
0473 
0474     tsd->rst = devm_reset_control_get_exclusive(&pdev->dev, "spi");
0475     if (IS_ERR(tsd->rst)) {
0476         dev_err(&pdev->dev, "can not get reset\n");
0477         ret = PTR_ERR(tsd->rst);
0478         goto exit_free_irq;
0479     }
0480 
0481     init_completion(&tsd->xfer_completion);
0482     pm_runtime_enable(&pdev->dev);
0483     if (!pm_runtime_enabled(&pdev->dev)) {
0484         ret = tegra_sflash_runtime_resume(&pdev->dev);
0485         if (ret)
0486             goto exit_pm_disable;
0487     }
0488 
0489     ret = pm_runtime_resume_and_get(&pdev->dev);
0490     if (ret < 0) {
0491         dev_err(&pdev->dev, "pm runtime get failed, e = %d\n", ret);
0492         goto exit_pm_disable;
0493     }
0494 
0495     /* Reset controller */
0496     reset_control_assert(tsd->rst);
0497     udelay(2);
0498     reset_control_deassert(tsd->rst);
0499 
0500     tsd->def_command_reg  = SPI_M_S | SPI_CS_SW;
0501     tegra_sflash_writel(tsd, tsd->def_command_reg, SPI_COMMAND);
0502     pm_runtime_put(&pdev->dev);
0503 
0504     master->dev.of_node = pdev->dev.of_node;
0505     ret = devm_spi_register_master(&pdev->dev, master);
0506     if (ret < 0) {
0507         dev_err(&pdev->dev, "can not register to master err %d\n", ret);
0508         goto exit_pm_disable;
0509     }
0510     return ret;
0511 
0512 exit_pm_disable:
0513     pm_runtime_disable(&pdev->dev);
0514     if (!pm_runtime_status_suspended(&pdev->dev))
0515         tegra_sflash_runtime_suspend(&pdev->dev);
0516 exit_free_irq:
0517     free_irq(tsd->irq, tsd);
0518 exit_free_master:
0519     spi_master_put(master);
0520     return ret;
0521 }
0522 
0523 static int tegra_sflash_remove(struct platform_device *pdev)
0524 {
0525     struct spi_master *master = platform_get_drvdata(pdev);
0526     struct tegra_sflash_data    *tsd = spi_master_get_devdata(master);
0527 
0528     free_irq(tsd->irq, tsd);
0529 
0530     pm_runtime_disable(&pdev->dev);
0531     if (!pm_runtime_status_suspended(&pdev->dev))
0532         tegra_sflash_runtime_suspend(&pdev->dev);
0533 
0534     return 0;
0535 }
0536 
0537 #ifdef CONFIG_PM_SLEEP
0538 static int tegra_sflash_suspend(struct device *dev)
0539 {
0540     struct spi_master *master = dev_get_drvdata(dev);
0541 
0542     return spi_master_suspend(master);
0543 }
0544 
0545 static int tegra_sflash_resume(struct device *dev)
0546 {
0547     struct spi_master *master = dev_get_drvdata(dev);
0548     struct tegra_sflash_data *tsd = spi_master_get_devdata(master);
0549     int ret;
0550 
0551     ret = pm_runtime_resume_and_get(dev);
0552     if (ret < 0) {
0553         dev_err(dev, "pm runtime failed, e = %d\n", ret);
0554         return ret;
0555     }
0556     tegra_sflash_writel(tsd, tsd->command_reg, SPI_COMMAND);
0557     pm_runtime_put(dev);
0558 
0559     return spi_master_resume(master);
0560 }
0561 #endif
0562 
0563 static int tegra_sflash_runtime_suspend(struct device *dev)
0564 {
0565     struct spi_master *master = dev_get_drvdata(dev);
0566     struct tegra_sflash_data *tsd = spi_master_get_devdata(master);
0567 
0568     /* Flush all write which are in PPSB queue by reading back */
0569     tegra_sflash_readl(tsd, SPI_COMMAND);
0570 
0571     clk_disable_unprepare(tsd->clk);
0572     return 0;
0573 }
0574 
0575 static int tegra_sflash_runtime_resume(struct device *dev)
0576 {
0577     struct spi_master *master = dev_get_drvdata(dev);
0578     struct tegra_sflash_data *tsd = spi_master_get_devdata(master);
0579     int ret;
0580 
0581     ret = clk_prepare_enable(tsd->clk);
0582     if (ret < 0) {
0583         dev_err(tsd->dev, "clk_prepare failed: %d\n", ret);
0584         return ret;
0585     }
0586     return 0;
0587 }
0588 
0589 static const struct dev_pm_ops slink_pm_ops = {
0590     SET_RUNTIME_PM_OPS(tegra_sflash_runtime_suspend,
0591         tegra_sflash_runtime_resume, NULL)
0592     SET_SYSTEM_SLEEP_PM_OPS(tegra_sflash_suspend, tegra_sflash_resume)
0593 };
0594 static struct platform_driver tegra_sflash_driver = {
0595     .driver = {
0596         .name       = "spi-tegra-sflash",
0597         .pm     = &slink_pm_ops,
0598         .of_match_table = tegra_sflash_of_match,
0599     },
0600     .probe =    tegra_sflash_probe,
0601     .remove =   tegra_sflash_remove,
0602 };
0603 module_platform_driver(tegra_sflash_driver);
0604 
0605 MODULE_ALIAS("platform:spi-tegra-sflash");
0606 MODULE_DESCRIPTION("NVIDIA Tegra20 Serial Flash Controller Driver");
0607 MODULE_AUTHOR("Laxman Dewangan <ldewangan@nvidia.com>");
0608 MODULE_LICENSE("GPL v2");
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