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0005 #include <linux/bitfield.h>
0006 #include <linux/clk.h>
0007 #include <linux/delay.h>
0008 #include <linux/dma-mapping.h>
0009 #include <linux/interrupt.h>
0010 #include <linux/module.h>
0011 #include <linux/of.h>
0012 #include <linux/platform_device.h>
0013 #include <linux/pm_runtime.h>
0014 #include <linux/reset.h>
0015 #include <linux/spi/spi.h>
0016
0017 #define SP7021_DATA_RDY_REG 0x0044
0018 #define SP7021_SLAVE_DMA_CTRL_REG 0x0048
0019 #define SP7021_SLAVE_DMA_LENGTH_REG 0x004c
0020 #define SP7021_SLAVE_DMA_ADDR_REG 0x004c
0021
0022 #define SP7021_SLAVE_DATA_RDY BIT(0)
0023 #define SP7021_SLAVE_SW_RST BIT(1)
0024 #define SP7021_SLA_DMA_W_INT BIT(8)
0025 #define SP7021_SLAVE_CLR_INT BIT(8)
0026 #define SP7021_SLAVE_DMA_EN BIT(0)
0027 #define SP7021_SLAVE_DMA_RW BIT(6)
0028 #define SP7021_SLAVE_DMA_CMD GENMASK(3, 2)
0029
0030 #define SP7021_FIFO_REG 0x0034
0031 #define SP7021_SPI_STATUS_REG 0x0038
0032 #define SP7021_SPI_CONFIG_REG 0x003c
0033 #define SP7021_INT_BUSY_REG 0x004c
0034 #define SP7021_DMA_CTRL_REG 0x0050
0035
0036 #define SP7021_SPI_START_FD BIT(0)
0037 #define SP7021_FD_SW_RST BIT(1)
0038 #define SP7021_TX_EMP_FLAG BIT(2)
0039 #define SP7021_RX_EMP_FLAG BIT(4)
0040 #define SP7021_RX_FULL_FLAG BIT(5)
0041 #define SP7021_FINISH_FLAG BIT(6)
0042
0043 #define SP7021_TX_CNT_MASK GENMASK(11, 8)
0044 #define SP7021_RX_CNT_MASK GENMASK(15, 12)
0045 #define SP7021_TX_LEN_MASK GENMASK(23, 16)
0046 #define SP7021_GET_LEN_MASK GENMASK(31, 24)
0047 #define SP7021_SET_TX_LEN GENMASK(23, 16)
0048 #define SP7021_SET_XFER_LEN GENMASK(31, 24)
0049
0050 #define SP7021_CPOL_FD BIT(0)
0051 #define SP7021_CPHA_R BIT(1)
0052 #define SP7021_CPHA_W BIT(2)
0053 #define SP7021_LSB_SEL BIT(4)
0054 #define SP7021_CS_POR BIT(5)
0055 #define SP7021_FD_SEL BIT(6)
0056
0057 #define SP7021_RX_UNIT GENMASK(8, 7)
0058 #define SP7021_TX_UNIT GENMASK(10, 9)
0059 #define SP7021_TX_EMP_FLAG_MASK BIT(11)
0060 #define SP7021_RX_FULL_FLAG_MASK BIT(14)
0061 #define SP7021_FINISH_FLAG_MASK BIT(15)
0062 #define SP7021_CLEAN_RW_BYTE GENMASK(10, 7)
0063 #define SP7021_CLEAN_FLUG_MASK GENMASK(15, 11)
0064 #define SP7021_CLK_MASK GENMASK(31, 16)
0065
0066 #define SP7021_INT_BYPASS BIT(3)
0067 #define SP7021_CLR_MASTER_INT BIT(6)
0068
0069 #define SP7021_SPI_DATA_SIZE (255)
0070 #define SP7021_FIFO_DATA_LEN (16)
0071
0072 enum {
0073 SP7021_MASTER_MODE = 0,
0074 SP7021_SLAVE_MODE = 1,
0075 };
0076
0077 struct sp7021_spi_ctlr {
0078 struct device *dev;
0079 struct spi_controller *ctlr;
0080 void __iomem *m_base;
0081 void __iomem *s_base;
0082 u32 xfer_conf;
0083 int mode;
0084 int m_irq;
0085 int s_irq;
0086 struct clk *spi_clk;
0087 struct reset_control *rstc;
0088
0089 struct mutex buf_lock;
0090 struct completion isr_done;
0091 struct completion slave_isr;
0092 unsigned int rx_cur_len;
0093 unsigned int tx_cur_len;
0094 unsigned int data_unit;
0095 const u8 *tx_buf;
0096 u8 *rx_buf;
0097 };
0098
0099 static irqreturn_t sp7021_spi_slave_irq(int irq, void *dev)
0100 {
0101 struct sp7021_spi_ctlr *pspim = dev;
0102 unsigned int data_status;
0103
0104 data_status = readl(pspim->s_base + SP7021_DATA_RDY_REG);
0105 data_status |= SP7021_SLAVE_CLR_INT;
0106 writel(data_status , pspim->s_base + SP7021_DATA_RDY_REG);
0107 complete(&pspim->slave_isr);
0108 return IRQ_HANDLED;
0109 }
0110
0111 static int sp7021_spi_slave_abort(struct spi_controller *ctlr)
0112 {
0113 struct sp7021_spi_ctlr *pspim = spi_master_get_devdata(ctlr);
0114
0115 complete(&pspim->slave_isr);
0116 complete(&pspim->isr_done);
0117 return 0;
0118 }
0119
0120 static int sp7021_spi_slave_tx(struct spi_device *spi, struct spi_transfer *xfer)
0121 {
0122 struct sp7021_spi_ctlr *pspim = spi_controller_get_devdata(spi->controller);
0123 u32 value;
0124
0125 reinit_completion(&pspim->slave_isr);
0126 value = SP7021_SLAVE_DMA_EN | SP7021_SLAVE_DMA_RW | FIELD_PREP(SP7021_SLAVE_DMA_CMD, 3);
0127 writel(value, pspim->s_base + SP7021_SLAVE_DMA_CTRL_REG);
0128 writel(xfer->len, pspim->s_base + SP7021_SLAVE_DMA_LENGTH_REG);
0129 writel(xfer->tx_dma, pspim->s_base + SP7021_SLAVE_DMA_ADDR_REG);
0130 value = readl(pspim->s_base + SP7021_DATA_RDY_REG);
0131 value |= SP7021_SLAVE_DATA_RDY;
0132 writel(value, pspim->s_base + SP7021_DATA_RDY_REG);
0133 if (wait_for_completion_interruptible(&pspim->isr_done)) {
0134 dev_err(&spi->dev, "%s() wait_for_completion err\n", __func__);
0135 return -EINTR;
0136 }
0137 return 0;
0138 }
0139
0140 static int sp7021_spi_slave_rx(struct spi_device *spi, struct spi_transfer *xfer)
0141 {
0142 struct sp7021_spi_ctlr *pspim = spi_controller_get_devdata(spi->controller);
0143 u32 value;
0144
0145 reinit_completion(&pspim->isr_done);
0146 value = SP7021_SLAVE_DMA_EN | FIELD_PREP(SP7021_SLAVE_DMA_CMD, 3);
0147 writel(value, pspim->s_base + SP7021_SLAVE_DMA_CTRL_REG);
0148 writel(xfer->len, pspim->s_base + SP7021_SLAVE_DMA_LENGTH_REG);
0149 writel(xfer->rx_dma, pspim->s_base + SP7021_SLAVE_DMA_ADDR_REG);
0150 if (wait_for_completion_interruptible(&pspim->isr_done)) {
0151 dev_err(&spi->dev, "%s() wait_for_completion err\n", __func__);
0152 return -EINTR;
0153 }
0154 writel(SP7021_SLAVE_SW_RST, pspim->s_base + SP7021_SLAVE_DMA_CTRL_REG);
0155 return 0;
0156 }
0157
0158 static void sp7021_spi_master_rb(struct sp7021_spi_ctlr *pspim, unsigned int len)
0159 {
0160 int i;
0161
0162 for (i = 0; i < len; i++) {
0163 pspim->rx_buf[pspim->rx_cur_len] =
0164 readl(pspim->m_base + SP7021_FIFO_REG);
0165 pspim->rx_cur_len++;
0166 }
0167 }
0168
0169 static void sp7021_spi_master_wb(struct sp7021_spi_ctlr *pspim, unsigned int len)
0170 {
0171 int i;
0172
0173 for (i = 0; i < len; i++) {
0174 writel(pspim->tx_buf[pspim->tx_cur_len],
0175 pspim->m_base + SP7021_FIFO_REG);
0176 pspim->tx_cur_len++;
0177 }
0178 }
0179
0180 static irqreturn_t sp7021_spi_master_irq(int irq, void *dev)
0181 {
0182 struct sp7021_spi_ctlr *pspim = dev;
0183 unsigned int tx_cnt, total_len;
0184 unsigned int tx_len, rx_cnt;
0185 unsigned int fd_status;
0186 bool isrdone = false;
0187 u32 value;
0188
0189 fd_status = readl(pspim->m_base + SP7021_SPI_STATUS_REG);
0190 tx_cnt = FIELD_GET(SP7021_TX_CNT_MASK, fd_status);
0191 tx_len = FIELD_GET(SP7021_TX_LEN_MASK, fd_status);
0192 total_len = FIELD_GET(SP7021_GET_LEN_MASK, fd_status);
0193
0194 if ((fd_status & SP7021_TX_EMP_FLAG) && (fd_status & SP7021_RX_EMP_FLAG) && total_len == 0)
0195 return IRQ_NONE;
0196
0197 if (tx_len == 0 && total_len == 0)
0198 return IRQ_NONE;
0199
0200 rx_cnt = FIELD_GET(SP7021_RX_CNT_MASK, fd_status);
0201 if (fd_status & SP7021_RX_FULL_FLAG)
0202 rx_cnt = pspim->data_unit;
0203
0204 tx_cnt = min(tx_len - pspim->tx_cur_len, pspim->data_unit - tx_cnt);
0205 dev_dbg(pspim->dev, "fd_st=0x%x rx_c:%d tx_c:%d tx_l:%d",
0206 fd_status, rx_cnt, tx_cnt, tx_len);
0207
0208 if (rx_cnt > 0)
0209 sp7021_spi_master_rb(pspim, rx_cnt);
0210 if (tx_cnt > 0)
0211 sp7021_spi_master_wb(pspim, tx_cnt);
0212
0213 fd_status = readl(pspim->m_base + SP7021_SPI_STATUS_REG);
0214 tx_len = FIELD_GET(SP7021_TX_LEN_MASK, fd_status);
0215 total_len = FIELD_GET(SP7021_GET_LEN_MASK, fd_status);
0216
0217 if (fd_status & SP7021_FINISH_FLAG || tx_len == pspim->tx_cur_len) {
0218 while (total_len != pspim->rx_cur_len) {
0219 fd_status = readl(pspim->m_base + SP7021_SPI_STATUS_REG);
0220 total_len = FIELD_GET(SP7021_GET_LEN_MASK, fd_status);
0221 if (fd_status & SP7021_RX_FULL_FLAG)
0222 rx_cnt = pspim->data_unit;
0223 else
0224 rx_cnt = FIELD_GET(SP7021_RX_CNT_MASK, fd_status);
0225
0226 if (rx_cnt > 0)
0227 sp7021_spi_master_rb(pspim, rx_cnt);
0228 }
0229 value = readl(pspim->m_base + SP7021_INT_BUSY_REG);
0230 value |= SP7021_CLR_MASTER_INT;
0231 writel(value, pspim->m_base + SP7021_INT_BUSY_REG);
0232 writel(SP7021_FINISH_FLAG, pspim->m_base + SP7021_SPI_STATUS_REG);
0233 isrdone = true;
0234 }
0235
0236 if (isrdone)
0237 complete(&pspim->isr_done);
0238 return IRQ_HANDLED;
0239 }
0240
0241 static void sp7021_prep_transfer(struct spi_controller *ctlr, struct spi_device *spi)
0242 {
0243 struct sp7021_spi_ctlr *pspim = spi_master_get_devdata(ctlr);
0244
0245 pspim->tx_cur_len = 0;
0246 pspim->rx_cur_len = 0;
0247 pspim->data_unit = SP7021_FIFO_DATA_LEN;
0248 }
0249
0250
0251 static int sp7021_spi_controller_prepare_message(struct spi_controller *ctlr,
0252 struct spi_message *msg)
0253 {
0254 struct sp7021_spi_ctlr *pspim = spi_master_get_devdata(ctlr);
0255 struct spi_device *s = msg->spi;
0256 u32 valus, rs = 0;
0257
0258 valus = readl(pspim->m_base + SP7021_SPI_STATUS_REG);
0259 valus |= SP7021_FD_SW_RST;
0260 writel(valus, pspim->m_base + SP7021_SPI_STATUS_REG);
0261 rs |= SP7021_FD_SEL;
0262 if (s->mode & SPI_CPOL)
0263 rs |= SP7021_CPOL_FD;
0264
0265 if (s->mode & SPI_LSB_FIRST)
0266 rs |= SP7021_LSB_SEL;
0267
0268 if (s->mode & SPI_CS_HIGH)
0269 rs |= SP7021_CS_POR;
0270
0271 if (s->mode & SPI_CPHA)
0272 rs |= SP7021_CPHA_R;
0273 else
0274 rs |= SP7021_CPHA_W;
0275
0276 rs |= FIELD_PREP(SP7021_TX_UNIT, 0) | FIELD_PREP(SP7021_RX_UNIT, 0);
0277 pspim->xfer_conf = rs;
0278 if (pspim->xfer_conf & SP7021_CPOL_FD)
0279 writel(pspim->xfer_conf, pspim->m_base + SP7021_SPI_CONFIG_REG);
0280
0281 return 0;
0282 }
0283
0284 static void sp7021_spi_setup_clk(struct spi_controller *ctlr, struct spi_transfer *xfer)
0285 {
0286 struct sp7021_spi_ctlr *pspim = spi_master_get_devdata(ctlr);
0287 u32 clk_rate, clk_sel, div;
0288
0289 clk_rate = clk_get_rate(pspim->spi_clk);
0290 div = max(2U, clk_rate / xfer->speed_hz);
0291
0292 clk_sel = (div / 2) - 1;
0293 pspim->xfer_conf &= ~SP7021_CLK_MASK;
0294 pspim->xfer_conf |= FIELD_PREP(SP7021_CLK_MASK, clk_sel);
0295 writel(pspim->xfer_conf, pspim->m_base + SP7021_SPI_CONFIG_REG);
0296 }
0297
0298 static int sp7021_spi_master_transfer_one(struct spi_controller *ctlr, struct spi_device *spi,
0299 struct spi_transfer *xfer)
0300 {
0301 struct sp7021_spi_ctlr *pspim = spi_master_get_devdata(ctlr);
0302 unsigned long timeout = msecs_to_jiffies(1000);
0303 unsigned int xfer_cnt, xfer_len, last_len;
0304 unsigned int i, len_temp;
0305 u32 reg_temp;
0306
0307 xfer_cnt = xfer->len / SP7021_SPI_DATA_SIZE;
0308 last_len = xfer->len % SP7021_SPI_DATA_SIZE;
0309
0310 for (i = 0; i <= xfer_cnt; i++) {
0311 mutex_lock(&pspim->buf_lock);
0312 sp7021_prep_transfer(ctlr, spi);
0313 sp7021_spi_setup_clk(ctlr, xfer);
0314 reinit_completion(&pspim->isr_done);
0315
0316 if (i == xfer_cnt)
0317 xfer_len = last_len;
0318 else
0319 xfer_len = SP7021_SPI_DATA_SIZE;
0320
0321 pspim->tx_buf = xfer->tx_buf + i * SP7021_SPI_DATA_SIZE;
0322 pspim->rx_buf = xfer->rx_buf + i * SP7021_SPI_DATA_SIZE;
0323
0324 if (pspim->tx_cur_len < xfer_len) {
0325 len_temp = min(pspim->data_unit, xfer_len);
0326 sp7021_spi_master_wb(pspim, len_temp);
0327 }
0328 reg_temp = readl(pspim->m_base + SP7021_SPI_CONFIG_REG);
0329 reg_temp &= ~SP7021_CLEAN_RW_BYTE;
0330 reg_temp &= ~SP7021_CLEAN_FLUG_MASK;
0331 reg_temp |= SP7021_FD_SEL | SP7021_FINISH_FLAG_MASK |
0332 SP7021_TX_EMP_FLAG_MASK | SP7021_RX_FULL_FLAG_MASK |
0333 FIELD_PREP(SP7021_TX_UNIT, 0) | FIELD_PREP(SP7021_RX_UNIT, 0);
0334 writel(reg_temp, pspim->m_base + SP7021_SPI_CONFIG_REG);
0335
0336 reg_temp = FIELD_PREP(SP7021_SET_TX_LEN, xfer_len) |
0337 FIELD_PREP(SP7021_SET_XFER_LEN, xfer_len) |
0338 SP7021_SPI_START_FD;
0339 writel(reg_temp, pspim->m_base + SP7021_SPI_STATUS_REG);
0340
0341 if (!wait_for_completion_interruptible_timeout(&pspim->isr_done, timeout)) {
0342 dev_err(&spi->dev, "wait_for_completion err\n");
0343 mutex_unlock(&pspim->buf_lock);
0344 return -ETIMEDOUT;
0345 }
0346
0347 reg_temp = readl(pspim->m_base + SP7021_SPI_STATUS_REG);
0348 if (reg_temp & SP7021_FINISH_FLAG) {
0349 writel(SP7021_FINISH_FLAG, pspim->m_base + SP7021_SPI_STATUS_REG);
0350 writel(readl(pspim->m_base + SP7021_SPI_CONFIG_REG) &
0351 SP7021_CLEAN_FLUG_MASK, pspim->m_base + SP7021_SPI_CONFIG_REG);
0352 }
0353
0354 if (pspim->xfer_conf & SP7021_CPOL_FD)
0355 writel(pspim->xfer_conf, pspim->m_base + SP7021_SPI_CONFIG_REG);
0356
0357 mutex_unlock(&pspim->buf_lock);
0358 }
0359 return 0;
0360 }
0361
0362 static int sp7021_spi_slave_transfer_one(struct spi_controller *ctlr, struct spi_device *spi,
0363 struct spi_transfer *xfer)
0364 {
0365 struct sp7021_spi_ctlr *pspim = spi_master_get_devdata(ctlr);
0366 struct device *dev = pspim->dev;
0367 int ret;
0368
0369 if (xfer->tx_buf && !xfer->rx_buf) {
0370 xfer->tx_dma = dma_map_single(dev, (void *)xfer->tx_buf,
0371 xfer->len, DMA_TO_DEVICE);
0372 if (dma_mapping_error(dev, xfer->tx_dma))
0373 return -ENOMEM;
0374 ret = sp7021_spi_slave_tx(spi, xfer);
0375 dma_unmap_single(dev, xfer->tx_dma, xfer->len, DMA_TO_DEVICE);
0376 } else if (xfer->rx_buf && !xfer->tx_buf) {
0377 xfer->rx_dma = dma_map_single(dev, xfer->rx_buf, xfer->len,
0378 DMA_FROM_DEVICE);
0379 if (dma_mapping_error(dev, xfer->rx_dma))
0380 return -ENOMEM;
0381 ret = sp7021_spi_slave_rx(spi, xfer);
0382 dma_unmap_single(dev, xfer->rx_dma, xfer->len, DMA_FROM_DEVICE);
0383 } else {
0384 dev_dbg(&ctlr->dev, "%s() wrong command\n", __func__);
0385 return -EINVAL;
0386 }
0387
0388 spi_finalize_current_transfer(ctlr);
0389 return ret;
0390 }
0391
0392 static void sp7021_spi_disable_unprepare(void *data)
0393 {
0394 clk_disable_unprepare(data);
0395 }
0396
0397 static void sp7021_spi_reset_control_assert(void *data)
0398 {
0399 reset_control_assert(data);
0400 }
0401
0402 static int sp7021_spi_controller_probe(struct platform_device *pdev)
0403 {
0404 struct device *dev = &pdev->dev;
0405 struct sp7021_spi_ctlr *pspim;
0406 struct spi_controller *ctlr;
0407 int mode, ret;
0408
0409 pdev->id = of_alias_get_id(pdev->dev.of_node, "sp_spi");
0410
0411 if (device_property_read_bool(dev, "spi-slave"))
0412 mode = SP7021_SLAVE_MODE;
0413 else
0414 mode = SP7021_MASTER_MODE;
0415
0416 if (mode == SP7021_SLAVE_MODE)
0417 ctlr = devm_spi_alloc_slave(dev, sizeof(*pspim));
0418 else
0419 ctlr = devm_spi_alloc_master(dev, sizeof(*pspim));
0420 if (!ctlr)
0421 return -ENOMEM;
0422 device_set_node(&ctlr->dev, dev_fwnode(dev));
0423 ctlr->bus_num = pdev->id;
0424 ctlr->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST;
0425 ctlr->auto_runtime_pm = true;
0426 ctlr->prepare_message = sp7021_spi_controller_prepare_message;
0427 if (mode == SP7021_SLAVE_MODE) {
0428 ctlr->transfer_one = sp7021_spi_slave_transfer_one;
0429 ctlr->slave_abort = sp7021_spi_slave_abort;
0430 ctlr->flags = SPI_CONTROLLER_HALF_DUPLEX;
0431 } else {
0432 ctlr->bits_per_word_mask = SPI_BPW_MASK(8);
0433 ctlr->min_speed_hz = 40000;
0434 ctlr->max_speed_hz = 25000000;
0435 ctlr->use_gpio_descriptors = true;
0436 ctlr->flags = SPI_CONTROLLER_MUST_RX | SPI_CONTROLLER_MUST_TX;
0437 ctlr->transfer_one = sp7021_spi_master_transfer_one;
0438 }
0439 platform_set_drvdata(pdev, ctlr);
0440 pspim = spi_controller_get_devdata(ctlr);
0441 pspim->mode = mode;
0442 pspim->ctlr = ctlr;
0443 pspim->dev = dev;
0444 mutex_init(&pspim->buf_lock);
0445 init_completion(&pspim->isr_done);
0446 init_completion(&pspim->slave_isr);
0447
0448 pspim->m_base = devm_platform_ioremap_resource_byname(pdev, "master");
0449 if (IS_ERR(pspim->m_base))
0450 return dev_err_probe(dev, PTR_ERR(pspim->m_base), "m_base get fail\n");
0451
0452 pspim->s_base = devm_platform_ioremap_resource_byname(pdev, "slave");
0453 if (IS_ERR(pspim->s_base))
0454 return dev_err_probe(dev, PTR_ERR(pspim->s_base), "s_base get fail\n");
0455
0456 pspim->m_irq = platform_get_irq_byname(pdev, "master_risc");
0457 if (pspim->m_irq < 0)
0458 return pspim->m_irq;
0459
0460 pspim->s_irq = platform_get_irq_byname(pdev, "slave_risc");
0461 if (pspim->s_irq < 0)
0462 return pspim->s_irq;
0463
0464 pspim->spi_clk = devm_clk_get(dev, NULL);
0465 if (IS_ERR(pspim->spi_clk))
0466 return dev_err_probe(dev, PTR_ERR(pspim->spi_clk), "clk get fail\n");
0467
0468 pspim->rstc = devm_reset_control_get_exclusive(dev, NULL);
0469 if (IS_ERR(pspim->rstc))
0470 return dev_err_probe(dev, PTR_ERR(pspim->rstc), "rst get fail\n");
0471
0472 ret = clk_prepare_enable(pspim->spi_clk);
0473 if (ret)
0474 return dev_err_probe(dev, ret, "failed to enable clk\n");
0475
0476 ret = devm_add_action_or_reset(dev, sp7021_spi_disable_unprepare, pspim->spi_clk);
0477 if (ret)
0478 return ret;
0479
0480 ret = reset_control_deassert(pspim->rstc);
0481 if (ret)
0482 return dev_err_probe(dev, ret, "failed to deassert reset\n");
0483
0484 ret = devm_add_action_or_reset(dev, sp7021_spi_reset_control_assert, pspim->rstc);
0485 if (ret)
0486 return ret;
0487
0488 ret = devm_request_irq(dev, pspim->m_irq, sp7021_spi_master_irq,
0489 IRQF_TRIGGER_RISING, pdev->name, pspim);
0490 if (ret)
0491 return ret;
0492
0493 ret = devm_request_irq(dev, pspim->s_irq, sp7021_spi_slave_irq,
0494 IRQF_TRIGGER_RISING, pdev->name, pspim);
0495 if (ret)
0496 return ret;
0497
0498 pm_runtime_enable(dev);
0499 ret = spi_register_controller(ctlr);
0500 if (ret) {
0501 pm_runtime_disable(dev);
0502 return dev_err_probe(dev, ret, "spi_register_master fail\n");
0503 }
0504 return 0;
0505 }
0506
0507 static int sp7021_spi_controller_remove(struct platform_device *pdev)
0508 {
0509 struct spi_controller *ctlr = dev_get_drvdata(&pdev->dev);
0510
0511 spi_unregister_controller(ctlr);
0512 pm_runtime_disable(&pdev->dev);
0513 pm_runtime_set_suspended(&pdev->dev);
0514 return 0;
0515 }
0516
0517 static int __maybe_unused sp7021_spi_controller_suspend(struct device *dev)
0518 {
0519 struct spi_controller *ctlr = dev_get_drvdata(dev);
0520 struct sp7021_spi_ctlr *pspim = spi_master_get_devdata(ctlr);
0521
0522 return reset_control_assert(pspim->rstc);
0523 }
0524
0525 static int __maybe_unused sp7021_spi_controller_resume(struct device *dev)
0526 {
0527 struct spi_controller *ctlr = dev_get_drvdata(dev);
0528 struct sp7021_spi_ctlr *pspim = spi_master_get_devdata(ctlr);
0529
0530 reset_control_deassert(pspim->rstc);
0531 return clk_prepare_enable(pspim->spi_clk);
0532 }
0533
0534 #ifdef CONFIG_PM
0535 static int sp7021_spi_runtime_suspend(struct device *dev)
0536 {
0537 struct spi_controller *ctlr = dev_get_drvdata(dev);
0538 struct sp7021_spi_ctlr *pspim = spi_master_get_devdata(ctlr);
0539
0540 return reset_control_assert(pspim->rstc);
0541 }
0542
0543 static int sp7021_spi_runtime_resume(struct device *dev)
0544 {
0545 struct spi_controller *ctlr = dev_get_drvdata(dev);
0546 struct sp7021_spi_ctlr *pspim = spi_master_get_devdata(ctlr);
0547
0548 return reset_control_deassert(pspim->rstc);
0549 }
0550 #endif
0551
0552 static const struct dev_pm_ops sp7021_spi_pm_ops = {
0553 SET_RUNTIME_PM_OPS(sp7021_spi_runtime_suspend,
0554 sp7021_spi_runtime_resume, NULL)
0555 SET_SYSTEM_SLEEP_PM_OPS(sp7021_spi_controller_suspend,
0556 sp7021_spi_controller_resume)
0557 };
0558
0559 static const struct of_device_id sp7021_spi_controller_ids[] = {
0560 { .compatible = "sunplus,sp7021-spi" },
0561 {}
0562 };
0563 MODULE_DEVICE_TABLE(of, sp7021_spi_controller_ids);
0564
0565 static struct platform_driver sp7021_spi_controller_driver = {
0566 .probe = sp7021_spi_controller_probe,
0567 .remove = sp7021_spi_controller_remove,
0568 .driver = {
0569 .name = "sunplus,sp7021-spi-controller",
0570 .of_match_table = sp7021_spi_controller_ids,
0571 .pm = &sp7021_spi_pm_ops,
0572 },
0573 };
0574 module_platform_driver(sp7021_spi_controller_driver);
0575
0576 MODULE_AUTHOR("Li-hao Kuo <lhjeff911@gmail.com>");
0577 MODULE_DESCRIPTION("Sunplus SPI controller driver");
0578 MODULE_LICENSE("GPL");
