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0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Copyright (C) 2012 - 2014 Allwinner Tech
0004  * Pan Nan <pannan@allwinnertech.com>
0005  *
0006  * Copyright (C) 2014 Maxime Ripard
0007  * Maxime Ripard <maxime.ripard@free-electrons.com>
0008  */
0009 
0010 #include <linux/bitfield.h>
0011 #include <linux/clk.h>
0012 #include <linux/delay.h>
0013 #include <linux/device.h>
0014 #include <linux/interrupt.h>
0015 #include <linux/io.h>
0016 #include <linux/module.h>
0017 #include <linux/of_device.h>
0018 #include <linux/platform_device.h>
0019 #include <linux/pm_runtime.h>
0020 #include <linux/reset.h>
0021 #include <linux/dmaengine.h>
0022 
0023 #include <linux/spi/spi.h>
0024 
0025 #define SUN6I_AUTOSUSPEND_TIMEOUT   2000
0026 
0027 #define SUN6I_FIFO_DEPTH        128
0028 #define SUN8I_FIFO_DEPTH        64
0029 
0030 #define SUN6I_GBL_CTL_REG       0x04
0031 #define SUN6I_GBL_CTL_BUS_ENABLE        BIT(0)
0032 #define SUN6I_GBL_CTL_MASTER            BIT(1)
0033 #define SUN6I_GBL_CTL_TP            BIT(7)
0034 #define SUN6I_GBL_CTL_RST           BIT(31)
0035 
0036 #define SUN6I_TFR_CTL_REG       0x08
0037 #define SUN6I_TFR_CTL_CPHA          BIT(0)
0038 #define SUN6I_TFR_CTL_CPOL          BIT(1)
0039 #define SUN6I_TFR_CTL_SPOL          BIT(2)
0040 #define SUN6I_TFR_CTL_CS_MASK           0x30
0041 #define SUN6I_TFR_CTL_CS(cs)            (((cs) << 4) & SUN6I_TFR_CTL_CS_MASK)
0042 #define SUN6I_TFR_CTL_CS_MANUAL         BIT(6)
0043 #define SUN6I_TFR_CTL_CS_LEVEL          BIT(7)
0044 #define SUN6I_TFR_CTL_DHB           BIT(8)
0045 #define SUN6I_TFR_CTL_FBS           BIT(12)
0046 #define SUN6I_TFR_CTL_XCH           BIT(31)
0047 
0048 #define SUN6I_INT_CTL_REG       0x10
0049 #define SUN6I_INT_CTL_RF_RDY            BIT(0)
0050 #define SUN6I_INT_CTL_TF_ERQ            BIT(4)
0051 #define SUN6I_INT_CTL_RF_OVF            BIT(8)
0052 #define SUN6I_INT_CTL_TC            BIT(12)
0053 
0054 #define SUN6I_INT_STA_REG       0x14
0055 
0056 #define SUN6I_FIFO_CTL_REG      0x18
0057 #define SUN6I_FIFO_CTL_RF_RDY_TRIG_LEVEL_MASK   0xff
0058 #define SUN6I_FIFO_CTL_RF_DRQ_EN        BIT(8)
0059 #define SUN6I_FIFO_CTL_RF_RDY_TRIG_LEVEL_BITS   0
0060 #define SUN6I_FIFO_CTL_RF_RST           BIT(15)
0061 #define SUN6I_FIFO_CTL_TF_ERQ_TRIG_LEVEL_MASK   0xff
0062 #define SUN6I_FIFO_CTL_TF_ERQ_TRIG_LEVEL_BITS   16
0063 #define SUN6I_FIFO_CTL_TF_DRQ_EN        BIT(24)
0064 #define SUN6I_FIFO_CTL_TF_RST           BIT(31)
0065 
0066 #define SUN6I_FIFO_STA_REG      0x1c
0067 #define SUN6I_FIFO_STA_RF_CNT_MASK      GENMASK(7, 0)
0068 #define SUN6I_FIFO_STA_TF_CNT_MASK      GENMASK(23, 16)
0069 
0070 #define SUN6I_CLK_CTL_REG       0x24
0071 #define SUN6I_CLK_CTL_CDR2_MASK         0xff
0072 #define SUN6I_CLK_CTL_CDR2(div)         (((div) & SUN6I_CLK_CTL_CDR2_MASK) << 0)
0073 #define SUN6I_CLK_CTL_CDR1_MASK         0xf
0074 #define SUN6I_CLK_CTL_CDR1(div)         (((div) & SUN6I_CLK_CTL_CDR1_MASK) << 8)
0075 #define SUN6I_CLK_CTL_DRS           BIT(12)
0076 
0077 #define SUN6I_MAX_XFER_SIZE     0xffffff
0078 
0079 #define SUN6I_BURST_CNT_REG     0x30
0080 
0081 #define SUN6I_XMIT_CNT_REG      0x34
0082 
0083 #define SUN6I_BURST_CTL_CNT_REG     0x38
0084 
0085 #define SUN6I_TXDATA_REG        0x200
0086 #define SUN6I_RXDATA_REG        0x300
0087 
0088 struct sun6i_spi {
0089     struct spi_master   *master;
0090     void __iomem        *base_addr;
0091     dma_addr_t      dma_addr_rx;
0092     dma_addr_t      dma_addr_tx;
0093     struct clk      *hclk;
0094     struct clk      *mclk;
0095     struct reset_control    *rstc;
0096 
0097     struct completion   done;
0098 
0099     const u8        *tx_buf;
0100     u8          *rx_buf;
0101     int         len;
0102     unsigned long       fifo_depth;
0103 };
0104 
0105 static inline u32 sun6i_spi_read(struct sun6i_spi *sspi, u32 reg)
0106 {
0107     return readl(sspi->base_addr + reg);
0108 }
0109 
0110 static inline void sun6i_spi_write(struct sun6i_spi *sspi, u32 reg, u32 value)
0111 {
0112     writel(value, sspi->base_addr + reg);
0113 }
0114 
0115 static inline u32 sun6i_spi_get_rx_fifo_count(struct sun6i_spi *sspi)
0116 {
0117     u32 reg = sun6i_spi_read(sspi, SUN6I_FIFO_STA_REG);
0118 
0119     return FIELD_GET(SUN6I_FIFO_STA_RF_CNT_MASK, reg);
0120 }
0121 
0122 static inline u32 sun6i_spi_get_tx_fifo_count(struct sun6i_spi *sspi)
0123 {
0124     u32 reg = sun6i_spi_read(sspi, SUN6I_FIFO_STA_REG);
0125 
0126     return FIELD_GET(SUN6I_FIFO_STA_TF_CNT_MASK, reg);
0127 }
0128 
0129 static inline void sun6i_spi_disable_interrupt(struct sun6i_spi *sspi, u32 mask)
0130 {
0131     u32 reg = sun6i_spi_read(sspi, SUN6I_INT_CTL_REG);
0132 
0133     reg &= ~mask;
0134     sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, reg);
0135 }
0136 
0137 static inline void sun6i_spi_drain_fifo(struct sun6i_spi *sspi)
0138 {
0139     u32 len;
0140     u8 byte;
0141 
0142     /* See how much data is available */
0143     len = sun6i_spi_get_rx_fifo_count(sspi);
0144 
0145     while (len--) {
0146         byte = readb(sspi->base_addr + SUN6I_RXDATA_REG);
0147         if (sspi->rx_buf)
0148             *sspi->rx_buf++ = byte;
0149     }
0150 }
0151 
0152 static inline void sun6i_spi_fill_fifo(struct sun6i_spi *sspi)
0153 {
0154     u32 cnt;
0155     int len;
0156     u8 byte;
0157 
0158     /* See how much data we can fit */
0159     cnt = sspi->fifo_depth - sun6i_spi_get_tx_fifo_count(sspi);
0160 
0161     len = min((int)cnt, sspi->len);
0162 
0163     while (len--) {
0164         byte = sspi->tx_buf ? *sspi->tx_buf++ : 0;
0165         writeb(byte, sspi->base_addr + SUN6I_TXDATA_REG);
0166         sspi->len--;
0167     }
0168 }
0169 
0170 static void sun6i_spi_set_cs(struct spi_device *spi, bool enable)
0171 {
0172     struct sun6i_spi *sspi = spi_master_get_devdata(spi->master);
0173     u32 reg;
0174 
0175     reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG);
0176     reg &= ~SUN6I_TFR_CTL_CS_MASK;
0177     reg |= SUN6I_TFR_CTL_CS(spi->chip_select);
0178 
0179     if (enable)
0180         reg |= SUN6I_TFR_CTL_CS_LEVEL;
0181     else
0182         reg &= ~SUN6I_TFR_CTL_CS_LEVEL;
0183 
0184     sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg);
0185 }
0186 
0187 static size_t sun6i_spi_max_transfer_size(struct spi_device *spi)
0188 {
0189     return SUN6I_MAX_XFER_SIZE - 1;
0190 }
0191 
0192 static int sun6i_spi_prepare_dma(struct sun6i_spi *sspi,
0193                  struct spi_transfer *tfr)
0194 {
0195     struct dma_async_tx_descriptor *rxdesc, *txdesc;
0196     struct spi_master *master = sspi->master;
0197 
0198     rxdesc = NULL;
0199     if (tfr->rx_buf) {
0200         struct dma_slave_config rxconf = {
0201             .direction = DMA_DEV_TO_MEM,
0202             .src_addr = sspi->dma_addr_rx,
0203             .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
0204             .src_maxburst = 8,
0205         };
0206 
0207         dmaengine_slave_config(master->dma_rx, &rxconf);
0208 
0209         rxdesc = dmaengine_prep_slave_sg(master->dma_rx,
0210                          tfr->rx_sg.sgl,
0211                          tfr->rx_sg.nents,
0212                          DMA_DEV_TO_MEM,
0213                          DMA_PREP_INTERRUPT);
0214         if (!rxdesc)
0215             return -EINVAL;
0216     }
0217 
0218     txdesc = NULL;
0219     if (tfr->tx_buf) {
0220         struct dma_slave_config txconf = {
0221             .direction = DMA_MEM_TO_DEV,
0222             .dst_addr = sspi->dma_addr_tx,
0223             .dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
0224             .dst_maxburst = 8,
0225         };
0226 
0227         dmaengine_slave_config(master->dma_tx, &txconf);
0228 
0229         txdesc = dmaengine_prep_slave_sg(master->dma_tx,
0230                          tfr->tx_sg.sgl,
0231                          tfr->tx_sg.nents,
0232                          DMA_MEM_TO_DEV,
0233                          DMA_PREP_INTERRUPT);
0234         if (!txdesc) {
0235             if (rxdesc)
0236                 dmaengine_terminate_sync(master->dma_rx);
0237             return -EINVAL;
0238         }
0239     }
0240 
0241     if (tfr->rx_buf) {
0242         dmaengine_submit(rxdesc);
0243         dma_async_issue_pending(master->dma_rx);
0244     }
0245 
0246     if (tfr->tx_buf) {
0247         dmaengine_submit(txdesc);
0248         dma_async_issue_pending(master->dma_tx);
0249     }
0250 
0251     return 0;
0252 }
0253 
0254 static int sun6i_spi_transfer_one(struct spi_master *master,
0255                   struct spi_device *spi,
0256                   struct spi_transfer *tfr)
0257 {
0258     struct sun6i_spi *sspi = spi_master_get_devdata(master);
0259     unsigned int mclk_rate, div, div_cdr1, div_cdr2, timeout;
0260     unsigned int start, end, tx_time;
0261     unsigned int trig_level;
0262     unsigned int tx_len = 0, rx_len = 0;
0263     bool use_dma;
0264     int ret = 0;
0265     u32 reg;
0266 
0267     if (tfr->len > SUN6I_MAX_XFER_SIZE)
0268         return -EINVAL;
0269 
0270     reinit_completion(&sspi->done);
0271     sspi->tx_buf = tfr->tx_buf;
0272     sspi->rx_buf = tfr->rx_buf;
0273     sspi->len = tfr->len;
0274     use_dma = master->can_dma ? master->can_dma(master, spi, tfr) : false;
0275 
0276     /* Clear pending interrupts */
0277     sun6i_spi_write(sspi, SUN6I_INT_STA_REG, ~0);
0278 
0279     /* Reset FIFO */
0280     sun6i_spi_write(sspi, SUN6I_FIFO_CTL_REG,
0281             SUN6I_FIFO_CTL_RF_RST | SUN6I_FIFO_CTL_TF_RST);
0282 
0283     reg = 0;
0284 
0285     if (!use_dma) {
0286         /*
0287          * Setup FIFO interrupt trigger level
0288          * Here we choose 3/4 of the full fifo depth, as it's
0289          * the hardcoded value used in old generation of Allwinner
0290          * SPI controller. (See spi-sun4i.c)
0291          */
0292         trig_level = sspi->fifo_depth / 4 * 3;
0293     } else {
0294         /*
0295          * Setup FIFO DMA request trigger level
0296          * We choose 1/2 of the full fifo depth, that value will
0297          * be used as DMA burst length.
0298          */
0299         trig_level = sspi->fifo_depth / 2;
0300 
0301         if (tfr->tx_buf)
0302             reg |= SUN6I_FIFO_CTL_TF_DRQ_EN;
0303         if (tfr->rx_buf)
0304             reg |= SUN6I_FIFO_CTL_RF_DRQ_EN;
0305     }
0306 
0307     reg |= (trig_level << SUN6I_FIFO_CTL_RF_RDY_TRIG_LEVEL_BITS) |
0308            (trig_level << SUN6I_FIFO_CTL_TF_ERQ_TRIG_LEVEL_BITS);
0309 
0310     sun6i_spi_write(sspi, SUN6I_FIFO_CTL_REG, reg);
0311 
0312     /*
0313      * Setup the transfer control register: Chip Select,
0314      * polarities, etc.
0315      */
0316     reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG);
0317 
0318     if (spi->mode & SPI_CPOL)
0319         reg |= SUN6I_TFR_CTL_CPOL;
0320     else
0321         reg &= ~SUN6I_TFR_CTL_CPOL;
0322 
0323     if (spi->mode & SPI_CPHA)
0324         reg |= SUN6I_TFR_CTL_CPHA;
0325     else
0326         reg &= ~SUN6I_TFR_CTL_CPHA;
0327 
0328     if (spi->mode & SPI_LSB_FIRST)
0329         reg |= SUN6I_TFR_CTL_FBS;
0330     else
0331         reg &= ~SUN6I_TFR_CTL_FBS;
0332 
0333     /*
0334      * If it's a TX only transfer, we don't want to fill the RX
0335      * FIFO with bogus data
0336      */
0337     if (sspi->rx_buf) {
0338         reg &= ~SUN6I_TFR_CTL_DHB;
0339         rx_len = tfr->len;
0340     } else {
0341         reg |= SUN6I_TFR_CTL_DHB;
0342     }
0343 
0344     /* We want to control the chip select manually */
0345     reg |= SUN6I_TFR_CTL_CS_MANUAL;
0346 
0347     sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg);
0348 
0349     /* Ensure that we have a parent clock fast enough */
0350     mclk_rate = clk_get_rate(sspi->mclk);
0351     if (mclk_rate < (2 * tfr->speed_hz)) {
0352         clk_set_rate(sspi->mclk, 2 * tfr->speed_hz);
0353         mclk_rate = clk_get_rate(sspi->mclk);
0354     }
0355 
0356     /*
0357      * Setup clock divider.
0358      *
0359      * We have two choices there. Either we can use the clock
0360      * divide rate 1, which is calculated thanks to this formula:
0361      * SPI_CLK = MOD_CLK / (2 ^ cdr)
0362      * Or we can use CDR2, which is calculated with the formula:
0363      * SPI_CLK = MOD_CLK / (2 * (cdr + 1))
0364      * Wether we use the former or the latter is set through the
0365      * DRS bit.
0366      *
0367      * First try CDR2, and if we can't reach the expected
0368      * frequency, fall back to CDR1.
0369      */
0370     div_cdr1 = DIV_ROUND_UP(mclk_rate, tfr->speed_hz);
0371     div_cdr2 = DIV_ROUND_UP(div_cdr1, 2);
0372     if (div_cdr2 <= (SUN6I_CLK_CTL_CDR2_MASK + 1)) {
0373         reg = SUN6I_CLK_CTL_CDR2(div_cdr2 - 1) | SUN6I_CLK_CTL_DRS;
0374         tfr->effective_speed_hz = mclk_rate / (2 * div_cdr2);
0375     } else {
0376         div = min(SUN6I_CLK_CTL_CDR1_MASK, order_base_2(div_cdr1));
0377         reg = SUN6I_CLK_CTL_CDR1(div);
0378         tfr->effective_speed_hz = mclk_rate / (1 << div);
0379     }
0380 
0381     sun6i_spi_write(sspi, SUN6I_CLK_CTL_REG, reg);
0382     /* Finally enable the bus - doing so before might raise SCK to HIGH */
0383     reg = sun6i_spi_read(sspi, SUN6I_GBL_CTL_REG);
0384     reg |= SUN6I_GBL_CTL_BUS_ENABLE;
0385     sun6i_spi_write(sspi, SUN6I_GBL_CTL_REG, reg);
0386 
0387     /* Setup the transfer now... */
0388     if (sspi->tx_buf)
0389         tx_len = tfr->len;
0390 
0391     /* Setup the counters */
0392     sun6i_spi_write(sspi, SUN6I_BURST_CNT_REG, tfr->len);
0393     sun6i_spi_write(sspi, SUN6I_XMIT_CNT_REG, tx_len);
0394     sun6i_spi_write(sspi, SUN6I_BURST_CTL_CNT_REG, tx_len);
0395 
0396     if (!use_dma) {
0397         /* Fill the TX FIFO */
0398         sun6i_spi_fill_fifo(sspi);
0399     } else {
0400         ret = sun6i_spi_prepare_dma(sspi, tfr);
0401         if (ret) {
0402             dev_warn(&master->dev,
0403                  "%s: prepare DMA failed, ret=%d",
0404                  dev_name(&spi->dev), ret);
0405             return ret;
0406         }
0407     }
0408 
0409     /* Enable the interrupts */
0410     reg = SUN6I_INT_CTL_TC;
0411 
0412     if (!use_dma) {
0413         if (rx_len > sspi->fifo_depth)
0414             reg |= SUN6I_INT_CTL_RF_RDY;
0415         if (tx_len > sspi->fifo_depth)
0416             reg |= SUN6I_INT_CTL_TF_ERQ;
0417     }
0418 
0419     sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, reg);
0420 
0421     /* Start the transfer */
0422     reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG);
0423     sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg | SUN6I_TFR_CTL_XCH);
0424 
0425     tx_time = max(tfr->len * 8 * 2 / (tfr->speed_hz / 1000), 100U);
0426     start = jiffies;
0427     timeout = wait_for_completion_timeout(&sspi->done,
0428                           msecs_to_jiffies(tx_time));
0429     end = jiffies;
0430     if (!timeout) {
0431         dev_warn(&master->dev,
0432              "%s: timeout transferring %u bytes@%iHz for %i(%i)ms",
0433              dev_name(&spi->dev), tfr->len, tfr->speed_hz,
0434              jiffies_to_msecs(end - start), tx_time);
0435         ret = -ETIMEDOUT;
0436     }
0437 
0438     sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, 0);
0439 
0440     if (ret && use_dma) {
0441         dmaengine_terminate_sync(master->dma_rx);
0442         dmaengine_terminate_sync(master->dma_tx);
0443     }
0444 
0445     return ret;
0446 }
0447 
0448 static irqreturn_t sun6i_spi_handler(int irq, void *dev_id)
0449 {
0450     struct sun6i_spi *sspi = dev_id;
0451     u32 status = sun6i_spi_read(sspi, SUN6I_INT_STA_REG);
0452 
0453     /* Transfer complete */
0454     if (status & SUN6I_INT_CTL_TC) {
0455         sun6i_spi_write(sspi, SUN6I_INT_STA_REG, SUN6I_INT_CTL_TC);
0456         sun6i_spi_drain_fifo(sspi);
0457         complete(&sspi->done);
0458         return IRQ_HANDLED;
0459     }
0460 
0461     /* Receive FIFO 3/4 full */
0462     if (status & SUN6I_INT_CTL_RF_RDY) {
0463         sun6i_spi_drain_fifo(sspi);
0464         /* Only clear the interrupt _after_ draining the FIFO */
0465         sun6i_spi_write(sspi, SUN6I_INT_STA_REG, SUN6I_INT_CTL_RF_RDY);
0466         return IRQ_HANDLED;
0467     }
0468 
0469     /* Transmit FIFO 3/4 empty */
0470     if (status & SUN6I_INT_CTL_TF_ERQ) {
0471         sun6i_spi_fill_fifo(sspi);
0472 
0473         if (!sspi->len)
0474             /* nothing left to transmit */
0475             sun6i_spi_disable_interrupt(sspi, SUN6I_INT_CTL_TF_ERQ);
0476 
0477         /* Only clear the interrupt _after_ re-seeding the FIFO */
0478         sun6i_spi_write(sspi, SUN6I_INT_STA_REG, SUN6I_INT_CTL_TF_ERQ);
0479 
0480         return IRQ_HANDLED;
0481     }
0482 
0483     return IRQ_NONE;
0484 }
0485 
0486 static int sun6i_spi_runtime_resume(struct device *dev)
0487 {
0488     struct spi_master *master = dev_get_drvdata(dev);
0489     struct sun6i_spi *sspi = spi_master_get_devdata(master);
0490     int ret;
0491 
0492     ret = clk_prepare_enable(sspi->hclk);
0493     if (ret) {
0494         dev_err(dev, "Couldn't enable AHB clock\n");
0495         goto out;
0496     }
0497 
0498     ret = clk_prepare_enable(sspi->mclk);
0499     if (ret) {
0500         dev_err(dev, "Couldn't enable module clock\n");
0501         goto err;
0502     }
0503 
0504     ret = reset_control_deassert(sspi->rstc);
0505     if (ret) {
0506         dev_err(dev, "Couldn't deassert the device from reset\n");
0507         goto err2;
0508     }
0509 
0510     sun6i_spi_write(sspi, SUN6I_GBL_CTL_REG,
0511             SUN6I_GBL_CTL_MASTER | SUN6I_GBL_CTL_TP);
0512 
0513     return 0;
0514 
0515 err2:
0516     clk_disable_unprepare(sspi->mclk);
0517 err:
0518     clk_disable_unprepare(sspi->hclk);
0519 out:
0520     return ret;
0521 }
0522 
0523 static int sun6i_spi_runtime_suspend(struct device *dev)
0524 {
0525     struct spi_master *master = dev_get_drvdata(dev);
0526     struct sun6i_spi *sspi = spi_master_get_devdata(master);
0527 
0528     reset_control_assert(sspi->rstc);
0529     clk_disable_unprepare(sspi->mclk);
0530     clk_disable_unprepare(sspi->hclk);
0531 
0532     return 0;
0533 }
0534 
0535 static bool sun6i_spi_can_dma(struct spi_master *master,
0536                   struct spi_device *spi,
0537                   struct spi_transfer *xfer)
0538 {
0539     struct sun6i_spi *sspi = spi_master_get_devdata(master);
0540 
0541     /*
0542      * If the number of spi words to transfer is less or equal than
0543      * the fifo length we can just fill the fifo and wait for a single
0544      * irq, so don't bother setting up dma
0545      */
0546     return xfer->len > sspi->fifo_depth;
0547 }
0548 
0549 static int sun6i_spi_probe(struct platform_device *pdev)
0550 {
0551     struct spi_master *master;
0552     struct sun6i_spi *sspi;
0553     struct resource *mem;
0554     int ret = 0, irq;
0555 
0556     master = spi_alloc_master(&pdev->dev, sizeof(struct sun6i_spi));
0557     if (!master) {
0558         dev_err(&pdev->dev, "Unable to allocate SPI Master\n");
0559         return -ENOMEM;
0560     }
0561 
0562     platform_set_drvdata(pdev, master);
0563     sspi = spi_master_get_devdata(master);
0564 
0565     sspi->base_addr = devm_platform_get_and_ioremap_resource(pdev, 0, &mem);
0566     if (IS_ERR(sspi->base_addr)) {
0567         ret = PTR_ERR(sspi->base_addr);
0568         goto err_free_master;
0569     }
0570 
0571     irq = platform_get_irq(pdev, 0);
0572     if (irq < 0) {
0573         ret = -ENXIO;
0574         goto err_free_master;
0575     }
0576 
0577     ret = devm_request_irq(&pdev->dev, irq, sun6i_spi_handler,
0578                    0, "sun6i-spi", sspi);
0579     if (ret) {
0580         dev_err(&pdev->dev, "Cannot request IRQ\n");
0581         goto err_free_master;
0582     }
0583 
0584     sspi->master = master;
0585     sspi->fifo_depth = (unsigned long)of_device_get_match_data(&pdev->dev);
0586 
0587     master->max_speed_hz = 100 * 1000 * 1000;
0588     master->min_speed_hz = 3 * 1000;
0589     master->use_gpio_descriptors = true;
0590     master->set_cs = sun6i_spi_set_cs;
0591     master->transfer_one = sun6i_spi_transfer_one;
0592     master->num_chipselect = 4;
0593     master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST;
0594     master->bits_per_word_mask = SPI_BPW_MASK(8);
0595     master->dev.of_node = pdev->dev.of_node;
0596     master->auto_runtime_pm = true;
0597     master->max_transfer_size = sun6i_spi_max_transfer_size;
0598 
0599     sspi->hclk = devm_clk_get(&pdev->dev, "ahb");
0600     if (IS_ERR(sspi->hclk)) {
0601         dev_err(&pdev->dev, "Unable to acquire AHB clock\n");
0602         ret = PTR_ERR(sspi->hclk);
0603         goto err_free_master;
0604     }
0605 
0606     sspi->mclk = devm_clk_get(&pdev->dev, "mod");
0607     if (IS_ERR(sspi->mclk)) {
0608         dev_err(&pdev->dev, "Unable to acquire module clock\n");
0609         ret = PTR_ERR(sspi->mclk);
0610         goto err_free_master;
0611     }
0612 
0613     init_completion(&sspi->done);
0614 
0615     sspi->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL);
0616     if (IS_ERR(sspi->rstc)) {
0617         dev_err(&pdev->dev, "Couldn't get reset controller\n");
0618         ret = PTR_ERR(sspi->rstc);
0619         goto err_free_master;
0620     }
0621 
0622     master->dma_tx = dma_request_chan(&pdev->dev, "tx");
0623     if (IS_ERR(master->dma_tx)) {
0624         /* Check tx to see if we need defer probing driver */
0625         if (PTR_ERR(master->dma_tx) == -EPROBE_DEFER) {
0626             ret = -EPROBE_DEFER;
0627             goto err_free_master;
0628         }
0629         dev_warn(&pdev->dev, "Failed to request TX DMA channel\n");
0630         master->dma_tx = NULL;
0631     }
0632 
0633     master->dma_rx = dma_request_chan(&pdev->dev, "rx");
0634     if (IS_ERR(master->dma_rx)) {
0635         if (PTR_ERR(master->dma_rx) == -EPROBE_DEFER) {
0636             ret = -EPROBE_DEFER;
0637             goto err_free_dma_tx;
0638         }
0639         dev_warn(&pdev->dev, "Failed to request RX DMA channel\n");
0640         master->dma_rx = NULL;
0641     }
0642 
0643     if (master->dma_tx && master->dma_rx) {
0644         sspi->dma_addr_tx = mem->start + SUN6I_TXDATA_REG;
0645         sspi->dma_addr_rx = mem->start + SUN6I_RXDATA_REG;
0646         master->can_dma = sun6i_spi_can_dma;
0647     }
0648 
0649     /*
0650      * This wake-up/shutdown pattern is to be able to have the
0651      * device woken up, even if runtime_pm is disabled
0652      */
0653     ret = sun6i_spi_runtime_resume(&pdev->dev);
0654     if (ret) {
0655         dev_err(&pdev->dev, "Couldn't resume the device\n");
0656         goto err_free_dma_rx;
0657     }
0658 
0659     pm_runtime_set_autosuspend_delay(&pdev->dev, SUN6I_AUTOSUSPEND_TIMEOUT);
0660     pm_runtime_use_autosuspend(&pdev->dev);
0661     pm_runtime_set_active(&pdev->dev);
0662     pm_runtime_enable(&pdev->dev);
0663 
0664     ret = devm_spi_register_master(&pdev->dev, master);
0665     if (ret) {
0666         dev_err(&pdev->dev, "cannot register SPI master\n");
0667         goto err_pm_disable;
0668     }
0669 
0670     return 0;
0671 
0672 err_pm_disable:
0673     pm_runtime_disable(&pdev->dev);
0674     sun6i_spi_runtime_suspend(&pdev->dev);
0675 err_free_dma_rx:
0676     if (master->dma_rx)
0677         dma_release_channel(master->dma_rx);
0678 err_free_dma_tx:
0679     if (master->dma_tx)
0680         dma_release_channel(master->dma_tx);
0681 err_free_master:
0682     spi_master_put(master);
0683     return ret;
0684 }
0685 
0686 static int sun6i_spi_remove(struct platform_device *pdev)
0687 {
0688     struct spi_master *master = platform_get_drvdata(pdev);
0689 
0690     pm_runtime_force_suspend(&pdev->dev);
0691 
0692     if (master->dma_tx)
0693         dma_release_channel(master->dma_tx);
0694     if (master->dma_rx)
0695         dma_release_channel(master->dma_rx);
0696     return 0;
0697 }
0698 
0699 static const struct of_device_id sun6i_spi_match[] = {
0700     { .compatible = "allwinner,sun6i-a31-spi", .data = (void *)SUN6I_FIFO_DEPTH },
0701     { .compatible = "allwinner,sun8i-h3-spi",  .data = (void *)SUN8I_FIFO_DEPTH },
0702     {}
0703 };
0704 MODULE_DEVICE_TABLE(of, sun6i_spi_match);
0705 
0706 static const struct dev_pm_ops sun6i_spi_pm_ops = {
0707     .runtime_resume     = sun6i_spi_runtime_resume,
0708     .runtime_suspend    = sun6i_spi_runtime_suspend,
0709 };
0710 
0711 static struct platform_driver sun6i_spi_driver = {
0712     .probe  = sun6i_spi_probe,
0713     .remove = sun6i_spi_remove,
0714     .driver = {
0715         .name       = "sun6i-spi",
0716         .of_match_table = sun6i_spi_match,
0717         .pm     = &sun6i_spi_pm_ops,
0718     },
0719 };
0720 module_platform_driver(sun6i_spi_driver);
0721 
0722 MODULE_AUTHOR("Pan Nan <pannan@allwinnertech.com>");
0723 MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
0724 MODULE_DESCRIPTION("Allwinner A31 SPI controller driver");
0725 MODULE_LICENSE("GPL");
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