drivers/spi/spi-sun4i.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Copyright (C) 2012 - 2014 Allwinner Tech
0004  * Pan Nan <pannan@allwinnertech.com>
0005  *
0006  * Copyright (C) 2014 Maxime Ripard
0007  * Maxime Ripard <maxime.ripard@free-electrons.com>
0008  */
0009
0010 #include <linux/clk.h>
0011 #include <linux/delay.h>
0012 #include <linux/device.h>
0013 #include <linux/interrupt.h>
0014 #include <linux/io.h>
0015 #include <linux/module.h>
0016 #include <linux/platform_device.h>
0017 #include <linux/pm_runtime.h>
0018
0019 #include <linux/spi/spi.h>
0020
0021 #define SUN4I_FIFO_DEPTH        64
0022
0023 #define SUN4I_RXDATA_REG        0x00
0024
0025 #define SUN4I_TXDATA_REG        0x04
0026
0027 #define SUN4I_CTL_REG           0x08
0028 #define SUN4I_CTL_ENABLE            BIT(0)
0029 #define SUN4I_CTL_MASTER            BIT(1)
0030 #define SUN4I_CTL_CPHA              BIT(2)
0031 #define SUN4I_CTL_CPOL              BIT(3)
0032 #define SUN4I_CTL_CS_ACTIVE_LOW         BIT(4)
0033 #define SUN4I_CTL_LMTF              BIT(6)
0034 #define SUN4I_CTL_TF_RST            BIT(8)
0035 #define SUN4I_CTL_RF_RST            BIT(9)
0036 #define SUN4I_CTL_XCH               BIT(10)
0037 #define SUN4I_CTL_CS_MASK           0x3000
0038 #define SUN4I_CTL_CS(cs)            (((cs) << 12) & SUN4I_CTL_CS_MASK)
0039 #define SUN4I_CTL_DHB               BIT(15)
0040 #define SUN4I_CTL_CS_MANUAL         BIT(16)
0041 #define SUN4I_CTL_CS_LEVEL          BIT(17)
0042 #define SUN4I_CTL_TP                BIT(18)
0043
0044 #define SUN4I_INT_CTL_REG       0x0c
0045 #define SUN4I_INT_CTL_RF_F34            BIT(4)
0046 #define SUN4I_INT_CTL_TF_E34            BIT(12)
0047 #define SUN4I_INT_CTL_TC            BIT(16)
0048
0049 #define SUN4I_INT_STA_REG       0x10
0050
0051 #define SUN4I_DMA_CTL_REG       0x14
0052
0053 #define SUN4I_WAIT_REG          0x18
0054
0055 #define SUN4I_CLK_CTL_REG       0x1c
0056 #define SUN4I_CLK_CTL_CDR2_MASK         0xff
0057 #define SUN4I_CLK_CTL_CDR2(div)         ((div) & SUN4I_CLK_CTL_CDR2_MASK)
0058 #define SUN4I_CLK_CTL_CDR1_MASK         0xf
0059 #define SUN4I_CLK_CTL_CDR1(div)         (((div) & SUN4I_CLK_CTL_CDR1_MASK) << 8)
0060 #define SUN4I_CLK_CTL_DRS           BIT(12)
0061
0062 #define SUN4I_MAX_XFER_SIZE         0xffffff
0063
0064 #define SUN4I_BURST_CNT_REG     0x20
0065 #define SUN4I_BURST_CNT(cnt)            ((cnt) & SUN4I_MAX_XFER_SIZE)
0066
0067 #define SUN4I_XMIT_CNT_REG      0x24
0068 #define SUN4I_XMIT_CNT(cnt)         ((cnt) & SUN4I_MAX_XFER_SIZE)
0069
0070
0071 #define SUN4I_FIFO_STA_REG      0x28
0072 #define SUN4I_FIFO_STA_RF_CNT_MASK      0x7f
0073 #define SUN4I_FIFO_STA_RF_CNT_BITS      0
0074 #define SUN4I_FIFO_STA_TF_CNT_MASK      0x7f
0075 #define SUN4I_FIFO_STA_TF_CNT_BITS      16
0076
0077 struct sun4i_spi {
0078     struct spi_master   *master;
0079     void __iomem        *base_addr;
0080     struct clk      *hclk;
0081     struct clk      *mclk;
0082
0083     struct completion   done;
0084
0085     const u8        *tx_buf;
0086     u8          *rx_buf;
0087     int         len;
0088 };
0089
0090 static inline u32 sun4i_spi_read(struct sun4i_spi *sspi, u32 reg)
0091 {
0092     return readl(sspi->base_addr + reg);
0093 }
0094
0095 static inline void sun4i_spi_write(struct sun4i_spi *sspi, u32 reg, u32 value)
0096 {
0097     writel(value, sspi->base_addr + reg);
0098 }
0099
0100 static inline u32 sun4i_spi_get_tx_fifo_count(struct sun4i_spi *sspi)
0101 {
0102     u32 reg = sun4i_spi_read(sspi, SUN4I_FIFO_STA_REG);
0103
0104     reg >>= SUN4I_FIFO_STA_TF_CNT_BITS;
0105
0106     return reg & SUN4I_FIFO_STA_TF_CNT_MASK;
0107 }
0108
0109 static inline void sun4i_spi_enable_interrupt(struct sun4i_spi *sspi, u32 mask)
0110 {
0111     u32 reg = sun4i_spi_read(sspi, SUN4I_INT_CTL_REG);
0112
0113     reg |= mask;
0114     sun4i_spi_write(sspi, SUN4I_INT_CTL_REG, reg);
0115 }
0116
0117 static inline void sun4i_spi_disable_interrupt(struct sun4i_spi *sspi, u32 mask)
0118 {
0119     u32 reg = sun4i_spi_read(sspi, SUN4I_INT_CTL_REG);
0120
0121     reg &= ~mask;
0122     sun4i_spi_write(sspi, SUN4I_INT_CTL_REG, reg);
0123 }
0124
0125 static inline void sun4i_spi_drain_fifo(struct sun4i_spi *sspi, int len)
0126 {
0127     u32 reg, cnt;
0128     u8 byte;
0129
0130     /* See how much data is available */
0131     reg = sun4i_spi_read(sspi, SUN4I_FIFO_STA_REG);
0132     reg &= SUN4I_FIFO_STA_RF_CNT_MASK;
0133     cnt = reg >> SUN4I_FIFO_STA_RF_CNT_BITS;
0134
0135     if (len > cnt)
0136         len = cnt;
0137
0138     while (len--) {
0139         byte = readb(sspi->base_addr + SUN4I_RXDATA_REG);
0140         if (sspi->rx_buf)
0141             *sspi->rx_buf++ = byte;
0142     }
0143 }
0144
0145 static inline void sun4i_spi_fill_fifo(struct sun4i_spi *sspi, int len)
0146 {
0147     u32 cnt;
0148     u8 byte;
0149
0150     /* See how much data we can fit */
0151     cnt = SUN4I_FIFO_DEPTH - sun4i_spi_get_tx_fifo_count(sspi);
0152
0153     len = min3(len, (int)cnt, sspi->len);
0154
0155     while (len--) {
0156         byte = sspi->tx_buf ? *sspi->tx_buf++ : 0;
0157         writeb(byte, sspi->base_addr + SUN4I_TXDATA_REG);
0158         sspi->len--;
0159     }
0160 }
0161
0162 static void sun4i_spi_set_cs(struct spi_device *spi, bool enable)
0163 {
0164     struct sun4i_spi *sspi = spi_master_get_devdata(spi->master);
0165     u32 reg;
0166
0167     reg = sun4i_spi_read(sspi, SUN4I_CTL_REG);
0168
0169     reg &= ~SUN4I_CTL_CS_MASK;
0170     reg |= SUN4I_CTL_CS(spi->chip_select);
0171
0172     /* We want to control the chip select manually */
0173     reg |= SUN4I_CTL_CS_MANUAL;
0174
0175     if (enable)
0176         reg |= SUN4I_CTL_CS_LEVEL;
0177     else
0178         reg &= ~SUN4I_CTL_CS_LEVEL;
0179
0180     /*
0181      * Even though this looks irrelevant since we are supposed to
0182      * be controlling the chip select manually, this bit also
0183      * controls the levels of the chip select for inactive
0184      * devices.
0185      *
0186      * If we don't set it, the chip select level will go low by
0187      * default when the device is idle, which is not really
0188      * expected in the common case where the chip select is active
0189      * low.
0190      */
0191     if (spi->mode & SPI_CS_HIGH)
0192         reg &= ~SUN4I_CTL_CS_ACTIVE_LOW;
0193     else
0194         reg |= SUN4I_CTL_CS_ACTIVE_LOW;
0195
0196     sun4i_spi_write(sspi, SUN4I_CTL_REG, reg);
0197 }
0198
0199 static size_t sun4i_spi_max_transfer_size(struct spi_device *spi)
0200 {
0201     return SUN4I_MAX_XFER_SIZE - 1;
0202 }
0203
0204 static int sun4i_spi_transfer_one(struct spi_master *master,
0205                   struct spi_device *spi,
0206                   struct spi_transfer *tfr)
0207 {
0208     struct sun4i_spi *sspi = spi_master_get_devdata(master);
0209     unsigned int mclk_rate, div, timeout;
0210     unsigned int start, end, tx_time;
0211     unsigned int tx_len = 0;
0212     int ret = 0;
0213     u32 reg;
0214
0215     /* We don't support transfer larger than the FIFO */
0216     if (tfr->len > SUN4I_MAX_XFER_SIZE)
0217         return -EMSGSIZE;
0218
0219     if (tfr->tx_buf && tfr->len >= SUN4I_MAX_XFER_SIZE)
0220         return -EMSGSIZE;
0221
0222     reinit_completion(&sspi->done);
0223     sspi->tx_buf = tfr->tx_buf;
0224     sspi->rx_buf = tfr->rx_buf;
0225     sspi->len = tfr->len;
0226
0227     /* Clear pending interrupts */
0228     sun4i_spi_write(sspi, SUN4I_INT_STA_REG, ~0);
0229
0230
0231     reg = sun4i_spi_read(sspi, SUN4I_CTL_REG);
0232
0233     /* Reset FIFOs */
0234     sun4i_spi_write(sspi, SUN4I_CTL_REG,
0235             reg | SUN4I_CTL_RF_RST | SUN4I_CTL_TF_RST);
0236
0237     /*
0238      * Setup the transfer control register: Chip Select,
0239      * polarities, etc.
0240      */
0241     if (spi->mode & SPI_CPOL)
0242         reg |= SUN4I_CTL_CPOL;
0243     else
0244         reg &= ~SUN4I_CTL_CPOL;
0245
0246     if (spi->mode & SPI_CPHA)
0247         reg |= SUN4I_CTL_CPHA;
0248     else
0249         reg &= ~SUN4I_CTL_CPHA;
0250
0251     if (spi->mode & SPI_LSB_FIRST)
0252         reg |= SUN4I_CTL_LMTF;
0253     else
0254         reg &= ~SUN4I_CTL_LMTF;
0255
0256
0257     /*
0258      * If it's a TX only transfer, we don't want to fill the RX
0259      * FIFO with bogus data
0260      */
0261     if (sspi->rx_buf)
0262         reg &= ~SUN4I_CTL_DHB;
0263     else
0264         reg |= SUN4I_CTL_DHB;
0265
0266     sun4i_spi_write(sspi, SUN4I_CTL_REG, reg);
0267
0268     /* Ensure that we have a parent clock fast enough */
0269     mclk_rate = clk_get_rate(sspi->mclk);
0270     if (mclk_rate < (2 * tfr->speed_hz)) {
0271         clk_set_rate(sspi->mclk, 2 * tfr->speed_hz);
0272         mclk_rate = clk_get_rate(sspi->mclk);
0273     }
0274
0275     /*
0276      * Setup clock divider.
0277      *
0278      * We have two choices there. Either we can use the clock
0279      * divide rate 1, which is calculated thanks to this formula:
0280      * SPI_CLK = MOD_CLK / (2 ^ (cdr + 1))
0281      * Or we can use CDR2, which is calculated with the formula:
0282      * SPI_CLK = MOD_CLK / (2 * (cdr + 1))
0283      * Whether we use the former or the latter is set through the
0284      * DRS bit.
0285      *
0286      * First try CDR2, and if we can't reach the expected
0287      * frequency, fall back to CDR1.
0288      */
0289     div = mclk_rate / (2 * tfr->speed_hz);
0290     if (div <= (SUN4I_CLK_CTL_CDR2_MASK + 1)) {
0291         if (div > 0)
0292             div--;
0293
0294         reg = SUN4I_CLK_CTL_CDR2(div) | SUN4I_CLK_CTL_DRS;
0295     } else {
0296         div = ilog2(mclk_rate) - ilog2(tfr->speed_hz);
0297         reg = SUN4I_CLK_CTL_CDR1(div);
0298     }
0299
0300     sun4i_spi_write(sspi, SUN4I_CLK_CTL_REG, reg);
0301
0302     /* Setup the transfer now... */
0303     if (sspi->tx_buf)
0304         tx_len = tfr->len;
0305
0306     /* Setup the counters */
0307     sun4i_spi_write(sspi, SUN4I_BURST_CNT_REG, SUN4I_BURST_CNT(tfr->len));
0308     sun4i_spi_write(sspi, SUN4I_XMIT_CNT_REG, SUN4I_XMIT_CNT(tx_len));
0309
0310     /*
0311      * Fill the TX FIFO
0312      * Filling the FIFO fully causes timeout for some reason
0313      * at least on spi2 on A10s
0314      */
0315     sun4i_spi_fill_fifo(sspi, SUN4I_FIFO_DEPTH - 1);
0316
0317     /* Enable the interrupts */
0318     sun4i_spi_enable_interrupt(sspi, SUN4I_INT_CTL_TC |
0319                      SUN4I_INT_CTL_RF_F34);
0320     /* Only enable Tx FIFO interrupt if we really need it */
0321     if (tx_len > SUN4I_FIFO_DEPTH)
0322         sun4i_spi_enable_interrupt(sspi, SUN4I_INT_CTL_TF_E34);
0323
0324     /* Start the transfer */
0325     reg = sun4i_spi_read(sspi, SUN4I_CTL_REG);
0326     sun4i_spi_write(sspi, SUN4I_CTL_REG, reg | SUN4I_CTL_XCH);
0327
0328     tx_time = max(tfr->len * 8 * 2 / (tfr->speed_hz / 1000), 100U);
0329     start = jiffies;
0330     timeout = wait_for_completion_timeout(&sspi->done,
0331                           msecs_to_jiffies(tx_time));
0332     end = jiffies;
0333     if (!timeout) {
0334         dev_warn(&master->dev,
0335              "%s: timeout transferring %u bytes@%iHz for %i(%i)ms",
0336              dev_name(&spi->dev), tfr->len, tfr->speed_hz,
0337              jiffies_to_msecs(end - start), tx_time);
0338         ret = -ETIMEDOUT;
0339         goto out;
0340     }
0341
0342
0343 out:
0344     sun4i_spi_write(sspi, SUN4I_INT_CTL_REG, 0);
0345
0346     return ret;
0347 }
0348
0349 static irqreturn_t sun4i_spi_handler(int irq, void *dev_id)
0350 {
0351     struct sun4i_spi *sspi = dev_id;
0352     u32 status = sun4i_spi_read(sspi, SUN4I_INT_STA_REG);
0353
0354     /* Transfer complete */
0355     if (status & SUN4I_INT_CTL_TC) {
0356         sun4i_spi_write(sspi, SUN4I_INT_STA_REG, SUN4I_INT_CTL_TC);
0357         sun4i_spi_drain_fifo(sspi, SUN4I_FIFO_DEPTH);
0358         complete(&sspi->done);
0359         return IRQ_HANDLED;
0360     }
0361
0362     /* Receive FIFO 3/4 full */
0363     if (status & SUN4I_INT_CTL_RF_F34) {
0364         sun4i_spi_drain_fifo(sspi, SUN4I_FIFO_DEPTH);
0365         /* Only clear the interrupt _after_ draining the FIFO */
0366         sun4i_spi_write(sspi, SUN4I_INT_STA_REG, SUN4I_INT_CTL_RF_F34);
0367         return IRQ_HANDLED;
0368     }
0369
0370     /* Transmit FIFO 3/4 empty */
0371     if (status & SUN4I_INT_CTL_TF_E34) {
0372         sun4i_spi_fill_fifo(sspi, SUN4I_FIFO_DEPTH);
0373
0374         if (!sspi->len)
0375             /* nothing left to transmit */
0376             sun4i_spi_disable_interrupt(sspi, SUN4I_INT_CTL_TF_E34);
0377
0378         /* Only clear the interrupt _after_ re-seeding the FIFO */
0379         sun4i_spi_write(sspi, SUN4I_INT_STA_REG, SUN4I_INT_CTL_TF_E34);
0380
0381         return IRQ_HANDLED;
0382     }
0383
0384     return IRQ_NONE;
0385 }
0386
0387 static int sun4i_spi_runtime_resume(struct device *dev)
0388 {
0389     struct spi_master *master = dev_get_drvdata(dev);
0390     struct sun4i_spi *sspi = spi_master_get_devdata(master);
0391     int ret;
0392
0393     ret = clk_prepare_enable(sspi->hclk);
0394     if (ret) {
0395         dev_err(dev, "Couldn't enable AHB clock\n");
0396         goto out;
0397     }
0398
0399     ret = clk_prepare_enable(sspi->mclk);
0400     if (ret) {
0401         dev_err(dev, "Couldn't enable module clock\n");
0402         goto err;
0403     }
0404
0405     sun4i_spi_write(sspi, SUN4I_CTL_REG,
0406             SUN4I_CTL_ENABLE | SUN4I_CTL_MASTER | SUN4I_CTL_TP);
0407
0408     return 0;
0409
0410 err:
0411     clk_disable_unprepare(sspi->hclk);
0412 out:
0413     return ret;
0414 }
0415
0416 static int sun4i_spi_runtime_suspend(struct device *dev)
0417 {
0418     struct spi_master *master = dev_get_drvdata(dev);
0419     struct sun4i_spi *sspi = spi_master_get_devdata(master);
0420
0421     clk_disable_unprepare(sspi->mclk);
0422     clk_disable_unprepare(sspi->hclk);
0423
0424     return 0;
0425 }
0426
0427 static int sun4i_spi_probe(struct platform_device *pdev)
0428 {
0429     struct spi_master *master;
0430     struct sun4i_spi *sspi;
0431     int ret = 0, irq;
0432
0433     master = spi_alloc_master(&pdev->dev, sizeof(struct sun4i_spi));
0434     if (!master) {
0435         dev_err(&pdev->dev, "Unable to allocate SPI Master\n");
0436         return -ENOMEM;
0437     }
0438
0439     platform_set_drvdata(pdev, master);
0440     sspi = spi_master_get_devdata(master);
0441
0442     sspi->base_addr = devm_platform_ioremap_resource(pdev, 0);
0443     if (IS_ERR(sspi->base_addr)) {
0444         ret = PTR_ERR(sspi->base_addr);
0445         goto err_free_master;
0446     }
0447
0448     irq = platform_get_irq(pdev, 0);
0449     if (irq < 0) {
0450         ret = -ENXIO;
0451         goto err_free_master;
0452     }
0453
0454     ret = devm_request_irq(&pdev->dev, irq, sun4i_spi_handler,
0455                    0, "sun4i-spi", sspi);
0456     if (ret) {
0457         dev_err(&pdev->dev, "Cannot request IRQ\n");
0458         goto err_free_master;
0459     }
0460
0461     sspi->master = master;
0462     master->max_speed_hz = 100 * 1000 * 1000;
0463     master->min_speed_hz = 3 * 1000;
0464     master->set_cs = sun4i_spi_set_cs;
0465     master->transfer_one = sun4i_spi_transfer_one;
0466     master->num_chipselect = 4;
0467     master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST;
0468     master->bits_per_word_mask = SPI_BPW_MASK(8);
0469     master->dev.of_node = pdev->dev.of_node;
0470     master->auto_runtime_pm = true;
0471     master->max_transfer_size = sun4i_spi_max_transfer_size;
0472
0473     sspi->hclk = devm_clk_get(&pdev->dev, "ahb");
0474     if (IS_ERR(sspi->hclk)) {
0475         dev_err(&pdev->dev, "Unable to acquire AHB clock\n");
0476         ret = PTR_ERR(sspi->hclk);
0477         goto err_free_master;
0478     }
0479
0480     sspi->mclk = devm_clk_get(&pdev->dev, "mod");
0481     if (IS_ERR(sspi->mclk)) {
0482         dev_err(&pdev->dev, "Unable to acquire module clock\n");
0483         ret = PTR_ERR(sspi->mclk);
0484         goto err_free_master;
0485     }
0486
0487     init_completion(&sspi->done);
0488
0489     /*
0490      * This wake-up/shutdown pattern is to be able to have the
0491      * device woken up, even if runtime_pm is disabled
0492      */
0493     ret = sun4i_spi_runtime_resume(&pdev->dev);
0494     if (ret) {
0495         dev_err(&pdev->dev, "Couldn't resume the device\n");
0496         goto err_free_master;
0497     }
0498
0499     pm_runtime_set_active(&pdev->dev);
0500     pm_runtime_enable(&pdev->dev);
0501     pm_runtime_idle(&pdev->dev);
0502
0503     ret = devm_spi_register_master(&pdev->dev, master);
0504     if (ret) {
0505         dev_err(&pdev->dev, "cannot register SPI master\n");
0506         goto err_pm_disable;
0507     }
0508
0509     return 0;
0510
0511 err_pm_disable:
0512     pm_runtime_disable(&pdev->dev);
0513     sun4i_spi_runtime_suspend(&pdev->dev);
0514 err_free_master:
0515     spi_master_put(master);
0516     return ret;
0517 }
0518
0519 static int sun4i_spi_remove(struct platform_device *pdev)
0520 {
0521     pm_runtime_force_suspend(&pdev->dev);
0522
0523     return 0;
0524 }
0525
0526 static const struct of_device_id sun4i_spi_match[] = {
0527     { .compatible = "allwinner,sun4i-a10-spi", },
0528     {}
0529 };
0530 MODULE_DEVICE_TABLE(of, sun4i_spi_match);
0531
0532 static const struct dev_pm_ops sun4i_spi_pm_ops = {
0533     .runtime_resume     = sun4i_spi_runtime_resume,
0534     .runtime_suspend    = sun4i_spi_runtime_suspend,
0535 };
0536
0537 static struct platform_driver sun4i_spi_driver = {
0538     .probe  = sun4i_spi_probe,
0539     .remove = sun4i_spi_remove,
0540     .driver = {
0541         .name       = "sun4i-spi",
0542         .of_match_table = sun4i_spi_match,
0543         .pm     = &sun4i_spi_pm_ops,
0544     },
0545 };
0546 module_platform_driver(sun4i_spi_driver);
0547
0548 MODULE_AUTHOR("Pan Nan <pannan@allwinnertech.com>");
0549 MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
0550 MODULE_DESCRIPTION("Allwinner A1X/A20 SPI controller driver");
0551 MODULE_LICENSE("GPL");