drivers/spi/spi-st-ssc4.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  *  Copyright (c) 2008-2014 STMicroelectronics Limited
0004  *
0005  *  Author: Angus Clark <Angus.Clark@st.com>
0006  *          Patrice Chotard <patrice.chotard@st.com>
0007  *          Lee Jones <lee.jones@linaro.org>
0008  *
0009  *  SPI master mode controller driver, used in STMicroelectronics devices.
0010  */
0011
0012 #include <linux/clk.h>
0013 #include <linux/delay.h>
0014 #include <linux/interrupt.h>
0015 #include <linux/io.h>
0016 #include <linux/module.h>
0017 #include <linux/pinctrl/consumer.h>
0018 #include <linux/platform_device.h>
0019 #include <linux/of.h>
0020 #include <linux/of_irq.h>
0021 #include <linux/pm_runtime.h>
0022 #include <linux/spi/spi.h>
0023 #include <linux/spi/spi_bitbang.h>
0024
0025 /* SSC registers */
0026 #define SSC_BRG             0x000
0027 #define SSC_TBUF            0x004
0028 #define SSC_RBUF            0x008
0029 #define SSC_CTL             0x00C
0030 #define SSC_IEN             0x010
0031 #define SSC_I2C             0x018
0032
0033 /* SSC Control */
0034 #define SSC_CTL_DATA_WIDTH_9        0x8
0035 #define SSC_CTL_DATA_WIDTH_MSK      0xf
0036 #define SSC_CTL_BM          0xf
0037 #define SSC_CTL_HB          BIT(4)
0038 #define SSC_CTL_PH          BIT(5)
0039 #define SSC_CTL_PO          BIT(6)
0040 #define SSC_CTL_SR          BIT(7)
0041 #define SSC_CTL_MS          BIT(8)
0042 #define SSC_CTL_EN          BIT(9)
0043 #define SSC_CTL_LPB         BIT(10)
0044 #define SSC_CTL_EN_TX_FIFO      BIT(11)
0045 #define SSC_CTL_EN_RX_FIFO      BIT(12)
0046 #define SSC_CTL_EN_CLST_RX      BIT(13)
0047
0048 /* SSC Interrupt Enable */
0049 #define SSC_IEN_TEEN            BIT(2)
0050
0051 #define FIFO_SIZE           8
0052
0053 struct spi_st {
0054     /* SSC SPI Controller */
0055     void __iomem        *base;
0056     struct clk      *clk;
0057     struct device       *dev;
0058
0059     /* SSC SPI current transaction */
0060     const u8        *tx_ptr;
0061     u8          *rx_ptr;
0062     u16         bytes_per_word;
0063     unsigned int        words_remaining;
0064     unsigned int        baud;
0065     struct completion   done;
0066 };
0067
0068 /* Load the TX FIFO */
0069 static void ssc_write_tx_fifo(struct spi_st *spi_st)
0070 {
0071     unsigned int count, i;
0072     uint32_t word = 0;
0073
0074     if (spi_st->words_remaining > FIFO_SIZE)
0075         count = FIFO_SIZE;
0076     else
0077         count = spi_st->words_remaining;
0078
0079     for (i = 0; i < count; i++) {
0080         if (spi_st->tx_ptr) {
0081             if (spi_st->bytes_per_word == 1) {
0082                 word = *spi_st->tx_ptr++;
0083             } else {
0084                 word = *spi_st->tx_ptr++;
0085                 word = *spi_st->tx_ptr++ | (word << 8);
0086             }
0087         }
0088         writel_relaxed(word, spi_st->base + SSC_TBUF);
0089     }
0090 }
0091
0092 /* Read the RX FIFO */
0093 static void ssc_read_rx_fifo(struct spi_st *spi_st)
0094 {
0095     unsigned int count, i;
0096     uint32_t word = 0;
0097
0098     if (spi_st->words_remaining > FIFO_SIZE)
0099         count = FIFO_SIZE;
0100     else
0101         count = spi_st->words_remaining;
0102
0103     for (i = 0; i < count; i++) {
0104         word = readl_relaxed(spi_st->base + SSC_RBUF);
0105
0106         if (spi_st->rx_ptr) {
0107             if (spi_st->bytes_per_word == 1) {
0108                 *spi_st->rx_ptr++ = (uint8_t)word;
0109             } else {
0110                 *spi_st->rx_ptr++ = (word >> 8);
0111                 *spi_st->rx_ptr++ = word & 0xff;
0112             }
0113         }
0114     }
0115     spi_st->words_remaining -= count;
0116 }
0117
0118 static int spi_st_transfer_one(struct spi_master *master,
0119                    struct spi_device *spi, struct spi_transfer *t)
0120 {
0121     struct spi_st *spi_st = spi_master_get_devdata(master);
0122     uint32_t ctl = 0;
0123
0124     /* Setup transfer */
0125     spi_st->tx_ptr = t->tx_buf;
0126     spi_st->rx_ptr = t->rx_buf;
0127
0128     if (spi->bits_per_word > 8) {
0129         /*
0130          * Anything greater than 8 bits-per-word requires 2
0131          * bytes-per-word in the RX/TX buffers
0132          */
0133         spi_st->bytes_per_word = 2;
0134         spi_st->words_remaining = t->len / 2;
0135
0136     } else if (spi->bits_per_word == 8 && !(t->len & 0x1)) {
0137         /*
0138          * If transfer is even-length, and 8 bits-per-word, then
0139          * implement as half-length 16 bits-per-word transfer
0140          */
0141         spi_st->bytes_per_word = 2;
0142         spi_st->words_remaining = t->len / 2;
0143
0144         /* Set SSC_CTL to 16 bits-per-word */
0145         ctl = readl_relaxed(spi_st->base + SSC_CTL);
0146         writel_relaxed((ctl | 0xf), spi_st->base + SSC_CTL);
0147
0148         readl_relaxed(spi_st->base + SSC_RBUF);
0149
0150     } else {
0151         spi_st->bytes_per_word = 1;
0152         spi_st->words_remaining = t->len;
0153     }
0154
0155     reinit_completion(&spi_st->done);
0156
0157     /* Start transfer by writing to the TX FIFO */
0158     ssc_write_tx_fifo(spi_st);
0159     writel_relaxed(SSC_IEN_TEEN, spi_st->base + SSC_IEN);
0160
0161     /* Wait for transfer to complete */
0162     wait_for_completion(&spi_st->done);
0163
0164     /* Restore SSC_CTL if necessary */
0165     if (ctl)
0166         writel_relaxed(ctl, spi_st->base + SSC_CTL);
0167
0168     spi_finalize_current_transfer(spi->master);
0169
0170     return t->len;
0171 }
0172
0173 /* the spi->mode bits understood by this driver: */
0174 #define MODEBITS  (SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST | SPI_LOOP | SPI_CS_HIGH)
0175 static int spi_st_setup(struct spi_device *spi)
0176 {
0177     struct spi_st *spi_st = spi_master_get_devdata(spi->master);
0178     u32 spi_st_clk, sscbrg, var;
0179     u32 hz = spi->max_speed_hz;
0180
0181     if (!hz)  {
0182         dev_err(&spi->dev, "max_speed_hz unspecified\n");
0183         return -EINVAL;
0184     }
0185
0186     if (!spi->cs_gpiod) {
0187         dev_err(&spi->dev, "no valid gpio assigned\n");
0188         return -EINVAL;
0189     }
0190
0191     spi_st_clk = clk_get_rate(spi_st->clk);
0192
0193     /* Set SSC_BRF */
0194     sscbrg = spi_st_clk / (2 * hz);
0195     if (sscbrg < 0x07 || sscbrg > BIT(16)) {
0196         dev_err(&spi->dev,
0197             "baudrate %d outside valid range %d\n", sscbrg, hz);
0198         return -EINVAL;
0199     }
0200
0201     spi_st->baud = spi_st_clk / (2 * sscbrg);
0202     if (sscbrg == BIT(16)) /* 16-bit counter wraps */
0203         sscbrg = 0x0;
0204
0205     writel_relaxed(sscbrg, spi_st->base + SSC_BRG);
0206
0207     dev_dbg(&spi->dev,
0208         "setting baudrate:target= %u hz, actual= %u hz, sscbrg= %u\n",
0209         hz, spi_st->baud, sscbrg);
0210
0211     /* Set SSC_CTL and enable SSC */
0212     var = readl_relaxed(spi_st->base + SSC_CTL);
0213     var |= SSC_CTL_MS;
0214
0215     if (spi->mode & SPI_CPOL)
0216         var |= SSC_CTL_PO;
0217     else
0218         var &= ~SSC_CTL_PO;
0219
0220     if (spi->mode & SPI_CPHA)
0221         var |= SSC_CTL_PH;
0222     else
0223         var &= ~SSC_CTL_PH;
0224
0225     if ((spi->mode & SPI_LSB_FIRST) == 0)
0226         var |= SSC_CTL_HB;
0227     else
0228         var &= ~SSC_CTL_HB;
0229
0230     if (spi->mode & SPI_LOOP)
0231         var |= SSC_CTL_LPB;
0232     else
0233         var &= ~SSC_CTL_LPB;
0234
0235     var &= ~SSC_CTL_DATA_WIDTH_MSK;
0236     var |= (spi->bits_per_word - 1);
0237
0238     var |= SSC_CTL_EN_TX_FIFO | SSC_CTL_EN_RX_FIFO;
0239     var |= SSC_CTL_EN;
0240
0241     writel_relaxed(var, spi_st->base + SSC_CTL);
0242
0243     /* Clear the status register */
0244     readl_relaxed(spi_st->base + SSC_RBUF);
0245
0246     return 0;
0247 }
0248
0249 /* Interrupt fired when TX shift register becomes empty */
0250 static irqreturn_t spi_st_irq(int irq, void *dev_id)
0251 {
0252     struct spi_st *spi_st = (struct spi_st *)dev_id;
0253
0254     /* Read RX FIFO */
0255     ssc_read_rx_fifo(spi_st);
0256
0257     /* Fill TX FIFO */
0258     if (spi_st->words_remaining) {
0259         ssc_write_tx_fifo(spi_st);
0260     } else {
0261         /* TX/RX complete */
0262         writel_relaxed(0x0, spi_st->base + SSC_IEN);
0263         /*
0264          * read SSC_IEN to ensure that this bit is set
0265          * before re-enabling interrupt
0266          */
0267         readl(spi_st->base + SSC_IEN);
0268         complete(&spi_st->done);
0269     }
0270
0271     return IRQ_HANDLED;
0272 }
0273
0274 static int spi_st_probe(struct platform_device *pdev)
0275 {
0276     struct device_node *np = pdev->dev.of_node;
0277     struct spi_master *master;
0278     struct spi_st *spi_st;
0279     int irq, ret = 0;
0280     u32 var;
0281
0282     master = spi_alloc_master(&pdev->dev, sizeof(*spi_st));
0283     if (!master)
0284         return -ENOMEM;
0285
0286     master->dev.of_node     = np;
0287     master->mode_bits       = MODEBITS;
0288     master->setup           = spi_st_setup;
0289     master->transfer_one        = spi_st_transfer_one;
0290     master->bits_per_word_mask  = SPI_BPW_MASK(8) | SPI_BPW_MASK(16);
0291     master->auto_runtime_pm     = true;
0292     master->bus_num         = pdev->id;
0293     master->use_gpio_descriptors    = true;
0294     spi_st              = spi_master_get_devdata(master);
0295
0296     spi_st->clk = devm_clk_get(&pdev->dev, "ssc");
0297     if (IS_ERR(spi_st->clk)) {
0298         dev_err(&pdev->dev, "Unable to request clock\n");
0299         ret = PTR_ERR(spi_st->clk);
0300         goto put_master;
0301     }
0302
0303     ret = clk_prepare_enable(spi_st->clk);
0304     if (ret)
0305         goto put_master;
0306
0307     init_completion(&spi_st->done);
0308
0309     /* Get resources */
0310     spi_st->base = devm_platform_ioremap_resource(pdev, 0);
0311     if (IS_ERR(spi_st->base)) {
0312         ret = PTR_ERR(spi_st->base);
0313         goto clk_disable;
0314     }
0315
0316     /* Disable I2C and Reset SSC */
0317     writel_relaxed(0x0, spi_st->base + SSC_I2C);
0318     var = readw_relaxed(spi_st->base + SSC_CTL);
0319     var |= SSC_CTL_SR;
0320     writel_relaxed(var, spi_st->base + SSC_CTL);
0321
0322     udelay(1);
0323     var = readl_relaxed(spi_st->base + SSC_CTL);
0324     var &= ~SSC_CTL_SR;
0325     writel_relaxed(var, spi_st->base + SSC_CTL);
0326
0327     /* Set SSC into slave mode before reconfiguring PIO pins */
0328     var = readl_relaxed(spi_st->base + SSC_CTL);
0329     var &= ~SSC_CTL_MS;
0330     writel_relaxed(var, spi_st->base + SSC_CTL);
0331
0332     irq = irq_of_parse_and_map(np, 0);
0333     if (!irq) {
0334         dev_err(&pdev->dev, "IRQ missing or invalid\n");
0335         ret = -EINVAL;
0336         goto clk_disable;
0337     }
0338
0339     ret = devm_request_irq(&pdev->dev, irq, spi_st_irq, 0,
0340                    pdev->name, spi_st);
0341     if (ret) {
0342         dev_err(&pdev->dev, "Failed to request irq %d\n", irq);
0343         goto clk_disable;
0344     }
0345
0346     /* by default the device is on */
0347     pm_runtime_set_active(&pdev->dev);
0348     pm_runtime_enable(&pdev->dev);
0349
0350     platform_set_drvdata(pdev, master);
0351
0352     ret = devm_spi_register_master(&pdev->dev, master);
0353     if (ret) {
0354         dev_err(&pdev->dev, "Failed to register master\n");
0355         goto rpm_disable;
0356     }
0357
0358     return 0;
0359
0360 rpm_disable:
0361     pm_runtime_disable(&pdev->dev);
0362 clk_disable:
0363     clk_disable_unprepare(spi_st->clk);
0364 put_master:
0365     spi_master_put(master);
0366     return ret;
0367 }
0368
0369 static int spi_st_remove(struct platform_device *pdev)
0370 {
0371     struct spi_master *master = platform_get_drvdata(pdev);
0372     struct spi_st *spi_st = spi_master_get_devdata(master);
0373
0374     pm_runtime_disable(&pdev->dev);
0375
0376     clk_disable_unprepare(spi_st->clk);
0377
0378     pinctrl_pm_select_sleep_state(&pdev->dev);
0379
0380     return 0;
0381 }
0382
0383 #ifdef CONFIG_PM
0384 static int spi_st_runtime_suspend(struct device *dev)
0385 {
0386     struct spi_master *master = dev_get_drvdata(dev);
0387     struct spi_st *spi_st = spi_master_get_devdata(master);
0388
0389     writel_relaxed(0, spi_st->base + SSC_IEN);
0390     pinctrl_pm_select_sleep_state(dev);
0391
0392     clk_disable_unprepare(spi_st->clk);
0393
0394     return 0;
0395 }
0396
0397 static int spi_st_runtime_resume(struct device *dev)
0398 {
0399     struct spi_master *master = dev_get_drvdata(dev);
0400     struct spi_st *spi_st = spi_master_get_devdata(master);
0401     int ret;
0402
0403     ret = clk_prepare_enable(spi_st->clk);
0404     pinctrl_pm_select_default_state(dev);
0405
0406     return ret;
0407 }
0408 #endif
0409
0410 #ifdef CONFIG_PM_SLEEP
0411 static int spi_st_suspend(struct device *dev)
0412 {
0413     struct spi_master *master = dev_get_drvdata(dev);
0414     int ret;
0415
0416     ret = spi_master_suspend(master);
0417     if (ret)
0418         return ret;
0419
0420     return pm_runtime_force_suspend(dev);
0421 }
0422
0423 static int spi_st_resume(struct device *dev)
0424 {
0425     struct spi_master *master = dev_get_drvdata(dev);
0426     int ret;
0427
0428     ret = spi_master_resume(master);
0429     if (ret)
0430         return ret;
0431
0432     return pm_runtime_force_resume(dev);
0433 }
0434 #endif
0435
0436 static const struct dev_pm_ops spi_st_pm = {
0437     SET_SYSTEM_SLEEP_PM_OPS(spi_st_suspend, spi_st_resume)
0438     SET_RUNTIME_PM_OPS(spi_st_runtime_suspend, spi_st_runtime_resume, NULL)
0439 };
0440
0441 static const struct of_device_id stm_spi_match[] = {
0442     { .compatible = "st,comms-ssc4-spi", },
0443     {},
0444 };
0445 MODULE_DEVICE_TABLE(of, stm_spi_match);
0446
0447 static struct platform_driver spi_st_driver = {
0448     .driver = {
0449         .name = "spi-st",
0450         .pm = &spi_st_pm,
0451         .of_match_table = of_match_ptr(stm_spi_match),
0452     },
0453     .probe = spi_st_probe,
0454     .remove = spi_st_remove,
0455 };
0456 module_platform_driver(spi_st_driver);
0457
0458 MODULE_AUTHOR("Patrice Chotard <patrice.chotard@st.com>");
0459 MODULE_DESCRIPTION("STM SSC SPI driver");
0460 MODULE_LICENSE("GPL v2");