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OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0
0002 // Copyright (C) 2018 Spreadtrum Communications Inc.
0003 
0004 #include <linux/clk.h>
0005 #include <linux/dmaengine.h>
0006 #include <linux/dma-mapping.h>
0007 #include <linux/dma/sprd-dma.h>
0008 #include <linux/interrupt.h>
0009 #include <linux/io.h>
0010 #include <linux/iopoll.h>
0011 #include <linux/kernel.h>
0012 #include <linux/module.h>
0013 #include <linux/of.h>
0014 #include <linux/of_device.h>
0015 #include <linux/of_dma.h>
0016 #include <linux/platform_device.h>
0017 #include <linux/pm_runtime.h>
0018 #include <linux/spi/spi.h>
0019 
0020 #define SPRD_SPI_TXD            0x0
0021 #define SPRD_SPI_CLKD           0x4
0022 #define SPRD_SPI_CTL0           0x8
0023 #define SPRD_SPI_CTL1           0xc
0024 #define SPRD_SPI_CTL2           0x10
0025 #define SPRD_SPI_CTL3           0x14
0026 #define SPRD_SPI_CTL4           0x18
0027 #define SPRD_SPI_CTL5           0x1c
0028 #define SPRD_SPI_INT_EN         0x20
0029 #define SPRD_SPI_INT_CLR        0x24
0030 #define SPRD_SPI_INT_RAW_STS        0x28
0031 #define SPRD_SPI_INT_MASK_STS       0x2c
0032 #define SPRD_SPI_STS1           0x30
0033 #define SPRD_SPI_STS2           0x34
0034 #define SPRD_SPI_DSP_WAIT       0x38
0035 #define SPRD_SPI_STS3           0x3c
0036 #define SPRD_SPI_CTL6           0x40
0037 #define SPRD_SPI_STS4           0x44
0038 #define SPRD_SPI_FIFO_RST       0x48
0039 #define SPRD_SPI_CTL7           0x4c
0040 #define SPRD_SPI_STS5           0x50
0041 #define SPRD_SPI_CTL8           0x54
0042 #define SPRD_SPI_CTL9           0x58
0043 #define SPRD_SPI_CTL10          0x5c
0044 #define SPRD_SPI_CTL11          0x60
0045 #define SPRD_SPI_CTL12          0x64
0046 #define SPRD_SPI_STS6           0x68
0047 #define SPRD_SPI_STS7           0x6c
0048 #define SPRD_SPI_STS8           0x70
0049 #define SPRD_SPI_STS9           0x74
0050 
0051 /* Bits & mask definition for register CTL0 */
0052 #define SPRD_SPI_SCK_REV        BIT(13)
0053 #define SPRD_SPI_NG_TX          BIT(1)
0054 #define SPRD_SPI_NG_RX          BIT(0)
0055 #define SPRD_SPI_CHNL_LEN_MASK      GENMASK(4, 0)
0056 #define SPRD_SPI_CSN_MASK       GENMASK(11, 8)
0057 #define SPRD_SPI_CS0_VALID      BIT(8)
0058 
0059 /* Bits & mask definition for register SPI_INT_EN */
0060 #define SPRD_SPI_TX_END_INT_EN      BIT(8)
0061 #define SPRD_SPI_RX_END_INT_EN      BIT(9)
0062 
0063 /* Bits & mask definition for register SPI_INT_RAW_STS */
0064 #define SPRD_SPI_TX_END_RAW     BIT(8)
0065 #define SPRD_SPI_RX_END_RAW     BIT(9)
0066 
0067 /* Bits & mask definition for register SPI_INT_CLR */
0068 #define SPRD_SPI_TX_END_CLR     BIT(8)
0069 #define SPRD_SPI_RX_END_CLR     BIT(9)
0070 
0071 /* Bits & mask definition for register INT_MASK_STS */
0072 #define SPRD_SPI_MASK_RX_END        BIT(9)
0073 #define SPRD_SPI_MASK_TX_END        BIT(8)
0074 
0075 /* Bits & mask definition for register STS2 */
0076 #define SPRD_SPI_TX_BUSY        BIT(8)
0077 
0078 /* Bits & mask definition for register CTL1 */
0079 #define SPRD_SPI_RX_MODE        BIT(12)
0080 #define SPRD_SPI_TX_MODE        BIT(13)
0081 #define SPRD_SPI_RTX_MD_MASK        GENMASK(13, 12)
0082 
0083 /* Bits & mask definition for register CTL2 */
0084 #define SPRD_SPI_DMA_EN         BIT(6)
0085 
0086 /* Bits & mask definition for register CTL4 */
0087 #define SPRD_SPI_START_RX       BIT(9)
0088 #define SPRD_SPI_ONLY_RECV_MASK     GENMASK(8, 0)
0089 
0090 /* Bits & mask definition for register SPI_INT_CLR */
0091 #define SPRD_SPI_RX_END_INT_CLR     BIT(9)
0092 #define SPRD_SPI_TX_END_INT_CLR     BIT(8)
0093 
0094 /* Bits & mask definition for register SPI_INT_RAW */
0095 #define SPRD_SPI_RX_END_IRQ     BIT(9)
0096 #define SPRD_SPI_TX_END_IRQ     BIT(8)
0097 
0098 /* Bits & mask definition for register CTL12 */
0099 #define SPRD_SPI_SW_RX_REQ      BIT(0)
0100 #define SPRD_SPI_SW_TX_REQ      BIT(1)
0101 
0102 /* Bits & mask definition for register CTL7 */
0103 #define SPRD_SPI_DATA_LINE2_EN      BIT(15)
0104 #define SPRD_SPI_MODE_MASK      GENMASK(5, 3)
0105 #define SPRD_SPI_MODE_OFFSET        3
0106 #define SPRD_SPI_3WIRE_MODE     4
0107 #define SPRD_SPI_4WIRE_MODE     0
0108 
0109 /* Bits & mask definition for register CTL8 */
0110 #define SPRD_SPI_TX_MAX_LEN_MASK    GENMASK(19, 0)
0111 #define SPRD_SPI_TX_LEN_H_MASK      GENMASK(3, 0)
0112 #define SPRD_SPI_TX_LEN_H_OFFSET    16
0113 
0114 /* Bits & mask definition for register CTL9 */
0115 #define SPRD_SPI_TX_LEN_L_MASK      GENMASK(15, 0)
0116 
0117 /* Bits & mask definition for register CTL10 */
0118 #define SPRD_SPI_RX_MAX_LEN_MASK    GENMASK(19, 0)
0119 #define SPRD_SPI_RX_LEN_H_MASK      GENMASK(3, 0)
0120 #define SPRD_SPI_RX_LEN_H_OFFSET    16
0121 
0122 /* Bits & mask definition for register CTL11 */
0123 #define SPRD_SPI_RX_LEN_L_MASK      GENMASK(15, 0)
0124 
0125 /* Default & maximum word delay cycles */
0126 #define SPRD_SPI_MIN_DELAY_CYCLE    14
0127 #define SPRD_SPI_MAX_DELAY_CYCLE    130
0128 
0129 #define SPRD_SPI_FIFO_SIZE      32
0130 #define SPRD_SPI_CHIP_CS_NUM        0x4
0131 #define SPRD_SPI_CHNL_LEN       2
0132 #define SPRD_SPI_DEFAULT_SOURCE     26000000
0133 #define SPRD_SPI_MAX_SPEED_HZ       48000000
0134 #define SPRD_SPI_AUTOSUSPEND_DELAY  100
0135 #define SPRD_SPI_DMA_STEP       8
0136 
0137 enum sprd_spi_dma_channel {
0138     SPRD_SPI_RX,
0139     SPRD_SPI_TX,
0140     SPRD_SPI_MAX,
0141 };
0142 
0143 struct sprd_spi_dma {
0144     bool enable;
0145     struct dma_chan *dma_chan[SPRD_SPI_MAX];
0146     enum dma_slave_buswidth width;
0147     u32 fragmens_len;
0148     u32 rx_len;
0149 };
0150 
0151 struct sprd_spi {
0152     void __iomem *base;
0153     phys_addr_t phy_base;
0154     struct device *dev;
0155     struct clk *clk;
0156     int irq;
0157     u32 src_clk;
0158     u32 hw_mode;
0159     u32 trans_len;
0160     u32 trans_mode;
0161     u32 word_delay;
0162     u32 hw_speed_hz;
0163     u32 len;
0164     int status;
0165     struct sprd_spi_dma dma;
0166     struct completion xfer_completion;
0167     const void *tx_buf;
0168     void *rx_buf;
0169     int (*read_bufs)(struct sprd_spi *ss, u32 len);
0170     int (*write_bufs)(struct sprd_spi *ss, u32 len);
0171 };
0172 
0173 static u32 sprd_spi_transfer_max_timeout(struct sprd_spi *ss,
0174                      struct spi_transfer *t)
0175 {
0176     /*
0177      * The time spent on transmission of the full FIFO data is the maximum
0178      * SPI transmission time.
0179      */
0180     u32 size = t->bits_per_word * SPRD_SPI_FIFO_SIZE;
0181     u32 bit_time_us = DIV_ROUND_UP(USEC_PER_SEC, ss->hw_speed_hz);
0182     u32 total_time_us = size * bit_time_us;
0183     /*
0184      * There is an interval between data and the data in our SPI hardware,
0185      * so the total transmission time need add the interval time.
0186      */
0187     u32 interval_cycle = SPRD_SPI_FIFO_SIZE * ss->word_delay;
0188     u32 interval_time_us = DIV_ROUND_UP(interval_cycle * USEC_PER_SEC,
0189                         ss->src_clk);
0190 
0191     return total_time_us + interval_time_us;
0192 }
0193 
0194 static int sprd_spi_wait_for_tx_end(struct sprd_spi *ss, struct spi_transfer *t)
0195 {
0196     u32 val, us;
0197     int ret;
0198 
0199     us = sprd_spi_transfer_max_timeout(ss, t);
0200     ret = readl_relaxed_poll_timeout(ss->base + SPRD_SPI_INT_RAW_STS, val,
0201                      val & SPRD_SPI_TX_END_IRQ, 0, us);
0202     if (ret) {
0203         dev_err(ss->dev, "SPI error, spi send timeout!\n");
0204         return ret;
0205     }
0206 
0207     ret = readl_relaxed_poll_timeout(ss->base + SPRD_SPI_STS2, val,
0208                      !(val & SPRD_SPI_TX_BUSY), 0, us);
0209     if (ret) {
0210         dev_err(ss->dev, "SPI error, spi busy timeout!\n");
0211         return ret;
0212     }
0213 
0214     writel_relaxed(SPRD_SPI_TX_END_INT_CLR, ss->base + SPRD_SPI_INT_CLR);
0215 
0216     return 0;
0217 }
0218 
0219 static int sprd_spi_wait_for_rx_end(struct sprd_spi *ss, struct spi_transfer *t)
0220 {
0221     u32 val, us;
0222     int ret;
0223 
0224     us = sprd_spi_transfer_max_timeout(ss, t);
0225     ret = readl_relaxed_poll_timeout(ss->base + SPRD_SPI_INT_RAW_STS, val,
0226                      val & SPRD_SPI_RX_END_IRQ, 0, us);
0227     if (ret) {
0228         dev_err(ss->dev, "SPI error, spi rx timeout!\n");
0229         return ret;
0230     }
0231 
0232     writel_relaxed(SPRD_SPI_RX_END_INT_CLR, ss->base + SPRD_SPI_INT_CLR);
0233 
0234     return 0;
0235 }
0236 
0237 static void sprd_spi_tx_req(struct sprd_spi *ss)
0238 {
0239     writel_relaxed(SPRD_SPI_SW_TX_REQ, ss->base + SPRD_SPI_CTL12);
0240 }
0241 
0242 static void sprd_spi_rx_req(struct sprd_spi *ss)
0243 {
0244     writel_relaxed(SPRD_SPI_SW_RX_REQ, ss->base + SPRD_SPI_CTL12);
0245 }
0246 
0247 static void sprd_spi_enter_idle(struct sprd_spi *ss)
0248 {
0249     u32 val = readl_relaxed(ss->base + SPRD_SPI_CTL1);
0250 
0251     val &= ~SPRD_SPI_RTX_MD_MASK;
0252     writel_relaxed(val, ss->base + SPRD_SPI_CTL1);
0253 }
0254 
0255 static void sprd_spi_set_transfer_bits(struct sprd_spi *ss, u32 bits)
0256 {
0257     u32 val = readl_relaxed(ss->base + SPRD_SPI_CTL0);
0258 
0259     /* Set the valid bits for every transaction */
0260     val &= ~(SPRD_SPI_CHNL_LEN_MASK << SPRD_SPI_CHNL_LEN);
0261     val |= bits << SPRD_SPI_CHNL_LEN;
0262     writel_relaxed(val, ss->base + SPRD_SPI_CTL0);
0263 }
0264 
0265 static void sprd_spi_set_tx_length(struct sprd_spi *ss, u32 length)
0266 {
0267     u32 val = readl_relaxed(ss->base + SPRD_SPI_CTL8);
0268 
0269     length &= SPRD_SPI_TX_MAX_LEN_MASK;
0270     val &= ~SPRD_SPI_TX_LEN_H_MASK;
0271     val |= length >> SPRD_SPI_TX_LEN_H_OFFSET;
0272     writel_relaxed(val, ss->base + SPRD_SPI_CTL8);
0273 
0274     val = length & SPRD_SPI_TX_LEN_L_MASK;
0275     writel_relaxed(val, ss->base + SPRD_SPI_CTL9);
0276 }
0277 
0278 static void sprd_spi_set_rx_length(struct sprd_spi *ss, u32 length)
0279 {
0280     u32 val = readl_relaxed(ss->base + SPRD_SPI_CTL10);
0281 
0282     length &= SPRD_SPI_RX_MAX_LEN_MASK;
0283     val &= ~SPRD_SPI_RX_LEN_H_MASK;
0284     val |= length >> SPRD_SPI_RX_LEN_H_OFFSET;
0285     writel_relaxed(val, ss->base + SPRD_SPI_CTL10);
0286 
0287     val = length & SPRD_SPI_RX_LEN_L_MASK;
0288     writel_relaxed(val, ss->base + SPRD_SPI_CTL11);
0289 }
0290 
0291 static void sprd_spi_chipselect(struct spi_device *sdev, bool cs)
0292 {
0293     struct spi_controller *sctlr = sdev->controller;
0294     struct sprd_spi *ss = spi_controller_get_devdata(sctlr);
0295     u32 val;
0296 
0297     val = readl_relaxed(ss->base + SPRD_SPI_CTL0);
0298     /*  The SPI controller will pull down CS pin if cs is 0 */
0299     if (!cs) {
0300         val &= ~SPRD_SPI_CS0_VALID;
0301         writel_relaxed(val, ss->base + SPRD_SPI_CTL0);
0302     } else {
0303         val |= SPRD_SPI_CSN_MASK;
0304         writel_relaxed(val, ss->base + SPRD_SPI_CTL0);
0305     }
0306 }
0307 
0308 static int sprd_spi_write_only_receive(struct sprd_spi *ss, u32 len)
0309 {
0310     u32 val;
0311 
0312     /* Clear the start receive bit and reset receive data number */
0313     val = readl_relaxed(ss->base + SPRD_SPI_CTL4);
0314     val &= ~(SPRD_SPI_START_RX | SPRD_SPI_ONLY_RECV_MASK);
0315     writel_relaxed(val, ss->base + SPRD_SPI_CTL4);
0316 
0317     /* Set the receive data length */
0318     val = readl_relaxed(ss->base + SPRD_SPI_CTL4);
0319     val |= len & SPRD_SPI_ONLY_RECV_MASK;
0320     writel_relaxed(val, ss->base + SPRD_SPI_CTL4);
0321 
0322     /* Trigger to receive data */
0323     val = readl_relaxed(ss->base + SPRD_SPI_CTL4);
0324     val |= SPRD_SPI_START_RX;
0325     writel_relaxed(val, ss->base + SPRD_SPI_CTL4);
0326 
0327     return len;
0328 }
0329 
0330 static int sprd_spi_write_bufs_u8(struct sprd_spi *ss, u32 len)
0331 {
0332     u8 *tx_p = (u8 *)ss->tx_buf;
0333     int i;
0334 
0335     for (i = 0; i < len; i++)
0336         writeb_relaxed(tx_p[i], ss->base + SPRD_SPI_TXD);
0337 
0338     ss->tx_buf += i;
0339     return i;
0340 }
0341 
0342 static int sprd_spi_write_bufs_u16(struct sprd_spi *ss, u32 len)
0343 {
0344     u16 *tx_p = (u16 *)ss->tx_buf;
0345     int i;
0346 
0347     for (i = 0; i < len; i++)
0348         writew_relaxed(tx_p[i], ss->base + SPRD_SPI_TXD);
0349 
0350     ss->tx_buf += i << 1;
0351     return i << 1;
0352 }
0353 
0354 static int sprd_spi_write_bufs_u32(struct sprd_spi *ss, u32 len)
0355 {
0356     u32 *tx_p = (u32 *)ss->tx_buf;
0357     int i;
0358 
0359     for (i = 0; i < len; i++)
0360         writel_relaxed(tx_p[i], ss->base + SPRD_SPI_TXD);
0361 
0362     ss->tx_buf += i << 2;
0363     return i << 2;
0364 }
0365 
0366 static int sprd_spi_read_bufs_u8(struct sprd_spi *ss, u32 len)
0367 {
0368     u8 *rx_p = (u8 *)ss->rx_buf;
0369     int i;
0370 
0371     for (i = 0; i < len; i++)
0372         rx_p[i] = readb_relaxed(ss->base + SPRD_SPI_TXD);
0373 
0374     ss->rx_buf += i;
0375     return i;
0376 }
0377 
0378 static int sprd_spi_read_bufs_u16(struct sprd_spi *ss, u32 len)
0379 {
0380     u16 *rx_p = (u16 *)ss->rx_buf;
0381     int i;
0382 
0383     for (i = 0; i < len; i++)
0384         rx_p[i] = readw_relaxed(ss->base + SPRD_SPI_TXD);
0385 
0386     ss->rx_buf += i << 1;
0387     return i << 1;
0388 }
0389 
0390 static int sprd_spi_read_bufs_u32(struct sprd_spi *ss, u32 len)
0391 {
0392     u32 *rx_p = (u32 *)ss->rx_buf;
0393     int i;
0394 
0395     for (i = 0; i < len; i++)
0396         rx_p[i] = readl_relaxed(ss->base + SPRD_SPI_TXD);
0397 
0398     ss->rx_buf += i << 2;
0399     return i << 2;
0400 }
0401 
0402 static int sprd_spi_txrx_bufs(struct spi_device *sdev, struct spi_transfer *t)
0403 {
0404     struct sprd_spi *ss = spi_controller_get_devdata(sdev->controller);
0405     u32 trans_len = ss->trans_len, len;
0406     int ret, write_size = 0, read_size = 0;
0407 
0408     while (trans_len) {
0409         len = trans_len > SPRD_SPI_FIFO_SIZE ? SPRD_SPI_FIFO_SIZE :
0410             trans_len;
0411         if (ss->trans_mode & SPRD_SPI_TX_MODE) {
0412             sprd_spi_set_tx_length(ss, len);
0413             write_size += ss->write_bufs(ss, len);
0414 
0415             /*
0416              * For our 3 wires mode or dual TX line mode, we need
0417              * to request the controller to transfer.
0418              */
0419             if (ss->hw_mode & SPI_3WIRE || ss->hw_mode & SPI_TX_DUAL)
0420                 sprd_spi_tx_req(ss);
0421 
0422             ret = sprd_spi_wait_for_tx_end(ss, t);
0423         } else {
0424             sprd_spi_set_rx_length(ss, len);
0425 
0426             /*
0427              * For our 3 wires mode or dual TX line mode, we need
0428              * to request the controller to read.
0429              */
0430             if (ss->hw_mode & SPI_3WIRE || ss->hw_mode & SPI_TX_DUAL)
0431                 sprd_spi_rx_req(ss);
0432             else
0433                 write_size += ss->write_bufs(ss, len);
0434 
0435             ret = sprd_spi_wait_for_rx_end(ss, t);
0436         }
0437 
0438         if (ret)
0439             goto complete;
0440 
0441         if (ss->trans_mode & SPRD_SPI_RX_MODE)
0442             read_size += ss->read_bufs(ss, len);
0443 
0444         trans_len -= len;
0445     }
0446 
0447     if (ss->trans_mode & SPRD_SPI_TX_MODE)
0448         ret = write_size;
0449     else
0450         ret = read_size;
0451 complete:
0452     sprd_spi_enter_idle(ss);
0453 
0454     return ret;
0455 }
0456 
0457 static void sprd_spi_irq_enable(struct sprd_spi *ss)
0458 {
0459     u32 val;
0460 
0461     /* Clear interrupt status before enabling interrupt. */
0462     writel_relaxed(SPRD_SPI_TX_END_CLR | SPRD_SPI_RX_END_CLR,
0463         ss->base + SPRD_SPI_INT_CLR);
0464     /* Enable SPI interrupt only in DMA mode. */
0465     val = readl_relaxed(ss->base + SPRD_SPI_INT_EN);
0466     writel_relaxed(val | SPRD_SPI_TX_END_INT_EN |
0467                SPRD_SPI_RX_END_INT_EN,
0468                ss->base + SPRD_SPI_INT_EN);
0469 }
0470 
0471 static void sprd_spi_irq_disable(struct sprd_spi *ss)
0472 {
0473     writel_relaxed(0, ss->base + SPRD_SPI_INT_EN);
0474 }
0475 
0476 static void sprd_spi_dma_enable(struct sprd_spi *ss, bool enable)
0477 {
0478     u32 val = readl_relaxed(ss->base + SPRD_SPI_CTL2);
0479 
0480     if (enable)
0481         val |= SPRD_SPI_DMA_EN;
0482     else
0483         val &= ~SPRD_SPI_DMA_EN;
0484 
0485     writel_relaxed(val, ss->base + SPRD_SPI_CTL2);
0486 }
0487 
0488 static int sprd_spi_dma_submit(struct dma_chan *dma_chan,
0489                    struct dma_slave_config *c,
0490                    struct sg_table *sg,
0491                    enum dma_transfer_direction dir)
0492 {
0493     struct dma_async_tx_descriptor *desc;
0494     dma_cookie_t cookie;
0495     unsigned long flags;
0496     int ret;
0497 
0498     ret = dmaengine_slave_config(dma_chan, c);
0499     if (ret < 0)
0500         return ret;
0501 
0502     flags = SPRD_DMA_FLAGS(SPRD_DMA_CHN_MODE_NONE, SPRD_DMA_NO_TRG,
0503                    SPRD_DMA_FRAG_REQ, SPRD_DMA_TRANS_INT);
0504     desc = dmaengine_prep_slave_sg(dma_chan, sg->sgl, sg->nents, dir, flags);
0505     if (!desc)
0506         return  -ENODEV;
0507 
0508     cookie = dmaengine_submit(desc);
0509     if (dma_submit_error(cookie))
0510         return dma_submit_error(cookie);
0511 
0512     dma_async_issue_pending(dma_chan);
0513 
0514     return 0;
0515 }
0516 
0517 static int sprd_spi_dma_rx_config(struct sprd_spi *ss, struct spi_transfer *t)
0518 {
0519     struct dma_chan *dma_chan = ss->dma.dma_chan[SPRD_SPI_RX];
0520     struct dma_slave_config config = {
0521         .src_addr = ss->phy_base,
0522         .src_addr_width = ss->dma.width,
0523         .dst_addr_width = ss->dma.width,
0524         .dst_maxburst = ss->dma.fragmens_len,
0525     };
0526     int ret;
0527 
0528     ret = sprd_spi_dma_submit(dma_chan, &config, &t->rx_sg, DMA_DEV_TO_MEM);
0529     if (ret)
0530         return ret;
0531 
0532     return ss->dma.rx_len;
0533 }
0534 
0535 static int sprd_spi_dma_tx_config(struct sprd_spi *ss, struct spi_transfer *t)
0536 {
0537     struct dma_chan *dma_chan = ss->dma.dma_chan[SPRD_SPI_TX];
0538     struct dma_slave_config config = {
0539         .dst_addr = ss->phy_base,
0540         .src_addr_width = ss->dma.width,
0541         .dst_addr_width = ss->dma.width,
0542         .src_maxburst = ss->dma.fragmens_len,
0543     };
0544     int ret;
0545 
0546     ret = sprd_spi_dma_submit(dma_chan, &config, &t->tx_sg, DMA_MEM_TO_DEV);
0547     if (ret)
0548         return ret;
0549 
0550     return t->len;
0551 }
0552 
0553 static int sprd_spi_dma_request(struct sprd_spi *ss)
0554 {
0555     ss->dma.dma_chan[SPRD_SPI_RX] = dma_request_chan(ss->dev, "rx_chn");
0556     if (IS_ERR_OR_NULL(ss->dma.dma_chan[SPRD_SPI_RX]))
0557         return dev_err_probe(ss->dev, PTR_ERR(ss->dma.dma_chan[SPRD_SPI_RX]),
0558                      "request RX DMA channel failed!\n");
0559 
0560     ss->dma.dma_chan[SPRD_SPI_TX]  = dma_request_chan(ss->dev, "tx_chn");
0561     if (IS_ERR_OR_NULL(ss->dma.dma_chan[SPRD_SPI_TX])) {
0562         dma_release_channel(ss->dma.dma_chan[SPRD_SPI_RX]);
0563         return dev_err_probe(ss->dev, PTR_ERR(ss->dma.dma_chan[SPRD_SPI_TX]),
0564                      "request TX DMA channel failed!\n");
0565     }
0566 
0567     return 0;
0568 }
0569 
0570 static void sprd_spi_dma_release(struct sprd_spi *ss)
0571 {
0572     if (ss->dma.dma_chan[SPRD_SPI_RX])
0573         dma_release_channel(ss->dma.dma_chan[SPRD_SPI_RX]);
0574 
0575     if (ss->dma.dma_chan[SPRD_SPI_TX])
0576         dma_release_channel(ss->dma.dma_chan[SPRD_SPI_TX]);
0577 }
0578 
0579 static int sprd_spi_dma_txrx_bufs(struct spi_device *sdev,
0580                   struct spi_transfer *t)
0581 {
0582     struct sprd_spi *ss = spi_master_get_devdata(sdev->master);
0583     u32 trans_len = ss->trans_len;
0584     int ret, write_size = 0;
0585 
0586     reinit_completion(&ss->xfer_completion);
0587     sprd_spi_irq_enable(ss);
0588     if (ss->trans_mode & SPRD_SPI_TX_MODE) {
0589         write_size = sprd_spi_dma_tx_config(ss, t);
0590         sprd_spi_set_tx_length(ss, trans_len);
0591 
0592         /*
0593          * For our 3 wires mode or dual TX line mode, we need
0594          * to request the controller to transfer.
0595          */
0596         if (ss->hw_mode & SPI_3WIRE || ss->hw_mode & SPI_TX_DUAL)
0597             sprd_spi_tx_req(ss);
0598     } else {
0599         sprd_spi_set_rx_length(ss, trans_len);
0600 
0601         /*
0602          * For our 3 wires mode or dual TX line mode, we need
0603          * to request the controller to read.
0604          */
0605         if (ss->hw_mode & SPI_3WIRE || ss->hw_mode & SPI_TX_DUAL)
0606             sprd_spi_rx_req(ss);
0607         else
0608             write_size = ss->write_bufs(ss, trans_len);
0609     }
0610 
0611     if (write_size < 0) {
0612         ret = write_size;
0613         dev_err(ss->dev, "failed to write, ret = %d\n", ret);
0614         goto trans_complete;
0615     }
0616 
0617     if (ss->trans_mode & SPRD_SPI_RX_MODE) {
0618         /*
0619          * Set up the DMA receive data length, which must be an
0620          * integral multiple of fragment length. But when the length
0621          * of received data is less than fragment length, DMA can be
0622          * configured to receive data according to the actual length
0623          * of received data.
0624          */
0625         ss->dma.rx_len = t->len > ss->dma.fragmens_len ?
0626             (t->len - t->len % ss->dma.fragmens_len) :
0627              t->len;
0628         ret = sprd_spi_dma_rx_config(ss, t);
0629         if (ret < 0) {
0630             dev_err(&sdev->dev,
0631                 "failed to configure rx DMA, ret = %d\n", ret);
0632             goto trans_complete;
0633         }
0634     }
0635 
0636     sprd_spi_dma_enable(ss, true);
0637     wait_for_completion(&(ss->xfer_completion));
0638 
0639     if (ss->trans_mode & SPRD_SPI_TX_MODE)
0640         ret = write_size;
0641     else
0642         ret = ss->dma.rx_len;
0643 
0644 trans_complete:
0645     sprd_spi_dma_enable(ss, false);
0646     sprd_spi_enter_idle(ss);
0647     sprd_spi_irq_disable(ss);
0648 
0649     return ret;
0650 }
0651 
0652 static void sprd_spi_set_speed(struct sprd_spi *ss, u32 speed_hz)
0653 {
0654     /*
0655      * From SPI datasheet, the prescale calculation formula:
0656      * prescale = SPI source clock / (2 * SPI_freq) - 1;
0657      */
0658     u32 clk_div = DIV_ROUND_UP(ss->src_clk, speed_hz << 1) - 1;
0659 
0660     /* Save the real hardware speed */
0661     ss->hw_speed_hz = (ss->src_clk >> 1) / (clk_div + 1);
0662     writel_relaxed(clk_div, ss->base + SPRD_SPI_CLKD);
0663 }
0664 
0665 static int sprd_spi_init_hw(struct sprd_spi *ss, struct spi_transfer *t)
0666 {
0667     struct spi_delay *d = &t->word_delay;
0668     u16 word_delay, interval;
0669     u32 val;
0670 
0671     if (d->unit != SPI_DELAY_UNIT_SCK)
0672         return -EINVAL;
0673 
0674     val = readl_relaxed(ss->base + SPRD_SPI_CTL0);
0675     val &= ~(SPRD_SPI_SCK_REV | SPRD_SPI_NG_TX | SPRD_SPI_NG_RX);
0676     /* Set default chip selection, clock phase and clock polarity */
0677     val |= ss->hw_mode & SPI_CPHA ? SPRD_SPI_NG_RX : SPRD_SPI_NG_TX;
0678     val |= ss->hw_mode & SPI_CPOL ? SPRD_SPI_SCK_REV : 0;
0679     writel_relaxed(val, ss->base + SPRD_SPI_CTL0);
0680 
0681     /*
0682      * Set the intervals of two SPI frames, and the inteval calculation
0683      * formula as below per datasheet:
0684      * interval time (source clock cycles) = interval * 4 + 10.
0685      */
0686     word_delay = clamp_t(u16, d->value, SPRD_SPI_MIN_DELAY_CYCLE,
0687                  SPRD_SPI_MAX_DELAY_CYCLE);
0688     interval = DIV_ROUND_UP(word_delay - 10, 4);
0689     ss->word_delay = interval * 4 + 10;
0690     writel_relaxed(interval, ss->base + SPRD_SPI_CTL5);
0691 
0692     /* Reset SPI fifo */
0693     writel_relaxed(1, ss->base + SPRD_SPI_FIFO_RST);
0694     writel_relaxed(0, ss->base + SPRD_SPI_FIFO_RST);
0695 
0696     /* Set SPI work mode */
0697     val = readl_relaxed(ss->base + SPRD_SPI_CTL7);
0698     val &= ~SPRD_SPI_MODE_MASK;
0699 
0700     if (ss->hw_mode & SPI_3WIRE)
0701         val |= SPRD_SPI_3WIRE_MODE << SPRD_SPI_MODE_OFFSET;
0702     else
0703         val |= SPRD_SPI_4WIRE_MODE << SPRD_SPI_MODE_OFFSET;
0704 
0705     if (ss->hw_mode & SPI_TX_DUAL)
0706         val |= SPRD_SPI_DATA_LINE2_EN;
0707     else
0708         val &= ~SPRD_SPI_DATA_LINE2_EN;
0709 
0710     writel_relaxed(val, ss->base + SPRD_SPI_CTL7);
0711 
0712     return 0;
0713 }
0714 
0715 static int sprd_spi_setup_transfer(struct spi_device *sdev,
0716                    struct spi_transfer *t)
0717 {
0718     struct sprd_spi *ss = spi_controller_get_devdata(sdev->controller);
0719     u8 bits_per_word = t->bits_per_word;
0720     u32 val, mode = 0;
0721     int ret;
0722 
0723     ss->len = t->len;
0724     ss->tx_buf = t->tx_buf;
0725     ss->rx_buf = t->rx_buf;
0726 
0727     ss->hw_mode = sdev->mode;
0728     ret = sprd_spi_init_hw(ss, t);
0729     if (ret)
0730         return ret;
0731 
0732     /* Set tansfer speed and valid bits */
0733     sprd_spi_set_speed(ss, t->speed_hz);
0734     sprd_spi_set_transfer_bits(ss, bits_per_word);
0735 
0736     if (bits_per_word > 16)
0737         bits_per_word = round_up(bits_per_word, 16);
0738     else
0739         bits_per_word = round_up(bits_per_word, 8);
0740 
0741     switch (bits_per_word) {
0742     case 8:
0743         ss->trans_len = t->len;
0744         ss->read_bufs = sprd_spi_read_bufs_u8;
0745         ss->write_bufs = sprd_spi_write_bufs_u8;
0746         ss->dma.width = DMA_SLAVE_BUSWIDTH_1_BYTE;
0747         ss->dma.fragmens_len = SPRD_SPI_DMA_STEP;
0748         break;
0749     case 16:
0750         ss->trans_len = t->len >> 1;
0751         ss->read_bufs = sprd_spi_read_bufs_u16;
0752         ss->write_bufs = sprd_spi_write_bufs_u16;
0753         ss->dma.width = DMA_SLAVE_BUSWIDTH_2_BYTES;
0754         ss->dma.fragmens_len = SPRD_SPI_DMA_STEP << 1;
0755         break;
0756     case 32:
0757         ss->trans_len = t->len >> 2;
0758         ss->read_bufs = sprd_spi_read_bufs_u32;
0759         ss->write_bufs = sprd_spi_write_bufs_u32;
0760         ss->dma.width = DMA_SLAVE_BUSWIDTH_4_BYTES;
0761         ss->dma.fragmens_len = SPRD_SPI_DMA_STEP << 2;
0762         break;
0763     default:
0764         return -EINVAL;
0765     }
0766 
0767     /* Set transfer read or write mode */
0768     val = readl_relaxed(ss->base + SPRD_SPI_CTL1);
0769     val &= ~SPRD_SPI_RTX_MD_MASK;
0770     if (t->tx_buf)
0771         mode |= SPRD_SPI_TX_MODE;
0772     if (t->rx_buf)
0773         mode |= SPRD_SPI_RX_MODE;
0774 
0775     writel_relaxed(val | mode, ss->base + SPRD_SPI_CTL1);
0776 
0777     ss->trans_mode = mode;
0778 
0779     /*
0780      * If in only receive mode, we need to trigger the SPI controller to
0781      * receive data automatically.
0782      */
0783     if (ss->trans_mode == SPRD_SPI_RX_MODE)
0784         ss->write_bufs = sprd_spi_write_only_receive;
0785 
0786     return 0;
0787 }
0788 
0789 static int sprd_spi_transfer_one(struct spi_controller *sctlr,
0790                  struct spi_device *sdev,
0791                  struct spi_transfer *t)
0792 {
0793     int ret;
0794 
0795     ret = sprd_spi_setup_transfer(sdev, t);
0796     if (ret)
0797         goto setup_err;
0798 
0799     if (sctlr->can_dma(sctlr, sdev, t))
0800         ret = sprd_spi_dma_txrx_bufs(sdev, t);
0801     else
0802         ret = sprd_spi_txrx_bufs(sdev, t);
0803 
0804     if (ret == t->len)
0805         ret = 0;
0806     else if (ret >= 0)
0807         ret = -EREMOTEIO;
0808 
0809 setup_err:
0810     spi_finalize_current_transfer(sctlr);
0811 
0812     return ret;
0813 }
0814 
0815 static irqreturn_t sprd_spi_handle_irq(int irq, void *data)
0816 {
0817     struct sprd_spi *ss = (struct sprd_spi *)data;
0818     u32 val = readl_relaxed(ss->base + SPRD_SPI_INT_MASK_STS);
0819 
0820     if (val & SPRD_SPI_MASK_TX_END) {
0821         writel_relaxed(SPRD_SPI_TX_END_CLR, ss->base + SPRD_SPI_INT_CLR);
0822         if (!(ss->trans_mode & SPRD_SPI_RX_MODE))
0823             complete(&ss->xfer_completion);
0824 
0825         return IRQ_HANDLED;
0826     }
0827 
0828     if (val & SPRD_SPI_MASK_RX_END) {
0829         writel_relaxed(SPRD_SPI_RX_END_CLR, ss->base + SPRD_SPI_INT_CLR);
0830         if (ss->dma.rx_len < ss->len) {
0831             ss->rx_buf += ss->dma.rx_len;
0832             ss->dma.rx_len +=
0833                 ss->read_bufs(ss, ss->len - ss->dma.rx_len);
0834         }
0835         complete(&ss->xfer_completion);
0836 
0837         return IRQ_HANDLED;
0838     }
0839 
0840     return IRQ_NONE;
0841 }
0842 
0843 static int sprd_spi_irq_init(struct platform_device *pdev, struct sprd_spi *ss)
0844 {
0845     int ret;
0846 
0847     ss->irq = platform_get_irq(pdev, 0);
0848     if (ss->irq < 0)
0849         return ss->irq;
0850 
0851     ret = devm_request_irq(&pdev->dev, ss->irq, sprd_spi_handle_irq,
0852                 0, pdev->name, ss);
0853     if (ret)
0854         dev_err(&pdev->dev, "failed to request spi irq %d, ret = %d\n",
0855             ss->irq, ret);
0856 
0857     return ret;
0858 }
0859 
0860 static int sprd_spi_clk_init(struct platform_device *pdev, struct sprd_spi *ss)
0861 {
0862     struct clk *clk_spi, *clk_parent;
0863 
0864     clk_spi = devm_clk_get(&pdev->dev, "spi");
0865     if (IS_ERR(clk_spi)) {
0866         dev_warn(&pdev->dev, "can't get the spi clock\n");
0867         clk_spi = NULL;
0868     }
0869 
0870     clk_parent = devm_clk_get(&pdev->dev, "source");
0871     if (IS_ERR(clk_parent)) {
0872         dev_warn(&pdev->dev, "can't get the source clock\n");
0873         clk_parent = NULL;
0874     }
0875 
0876     ss->clk = devm_clk_get(&pdev->dev, "enable");
0877     if (IS_ERR(ss->clk)) {
0878         dev_err(&pdev->dev, "can't get the enable clock\n");
0879         return PTR_ERR(ss->clk);
0880     }
0881 
0882     if (!clk_set_parent(clk_spi, clk_parent))
0883         ss->src_clk = clk_get_rate(clk_spi);
0884     else
0885         ss->src_clk = SPRD_SPI_DEFAULT_SOURCE;
0886 
0887     return 0;
0888 }
0889 
0890 static bool sprd_spi_can_dma(struct spi_controller *sctlr,
0891                  struct spi_device *spi, struct spi_transfer *t)
0892 {
0893     struct sprd_spi *ss = spi_controller_get_devdata(sctlr);
0894 
0895     return ss->dma.enable && (t->len > SPRD_SPI_FIFO_SIZE);
0896 }
0897 
0898 static int sprd_spi_dma_init(struct platform_device *pdev, struct sprd_spi *ss)
0899 {
0900     int ret;
0901 
0902     ret = sprd_spi_dma_request(ss);
0903     if (ret) {
0904         if (ret == -EPROBE_DEFER)
0905             return ret;
0906 
0907         dev_warn(&pdev->dev,
0908              "failed to request dma, enter no dma mode, ret = %d\n",
0909              ret);
0910 
0911         return 0;
0912     }
0913 
0914     ss->dma.enable = true;
0915 
0916     return 0;
0917 }
0918 
0919 static int sprd_spi_probe(struct platform_device *pdev)
0920 {
0921     struct spi_controller *sctlr;
0922     struct resource *res;
0923     struct sprd_spi *ss;
0924     int ret;
0925 
0926     pdev->id = of_alias_get_id(pdev->dev.of_node, "spi");
0927     sctlr = spi_alloc_master(&pdev->dev, sizeof(*ss));
0928     if (!sctlr)
0929         return -ENOMEM;
0930 
0931     ss = spi_controller_get_devdata(sctlr);
0932     res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
0933     ss->base = devm_ioremap_resource(&pdev->dev, res);
0934     if (IS_ERR(ss->base)) {
0935         ret = PTR_ERR(ss->base);
0936         goto free_controller;
0937     }
0938 
0939     ss->phy_base = res->start;
0940     ss->dev = &pdev->dev;
0941     sctlr->dev.of_node = pdev->dev.of_node;
0942     sctlr->mode_bits = SPI_CPOL | SPI_CPHA | SPI_3WIRE | SPI_TX_DUAL;
0943     sctlr->bus_num = pdev->id;
0944     sctlr->set_cs = sprd_spi_chipselect;
0945     sctlr->transfer_one = sprd_spi_transfer_one;
0946     sctlr->can_dma = sprd_spi_can_dma;
0947     sctlr->auto_runtime_pm = true;
0948     sctlr->max_speed_hz = min_t(u32, ss->src_clk >> 1,
0949                     SPRD_SPI_MAX_SPEED_HZ);
0950 
0951     init_completion(&ss->xfer_completion);
0952     platform_set_drvdata(pdev, sctlr);
0953     ret = sprd_spi_clk_init(pdev, ss);
0954     if (ret)
0955         goto free_controller;
0956 
0957     ret = sprd_spi_irq_init(pdev, ss);
0958     if (ret)
0959         goto free_controller;
0960 
0961     ret = sprd_spi_dma_init(pdev, ss);
0962     if (ret)
0963         goto free_controller;
0964 
0965     ret = clk_prepare_enable(ss->clk);
0966     if (ret)
0967         goto release_dma;
0968 
0969     ret = pm_runtime_set_active(&pdev->dev);
0970     if (ret < 0)
0971         goto disable_clk;
0972 
0973     pm_runtime_set_autosuspend_delay(&pdev->dev,
0974                      SPRD_SPI_AUTOSUSPEND_DELAY);
0975     pm_runtime_use_autosuspend(&pdev->dev);
0976     pm_runtime_enable(&pdev->dev);
0977     ret = pm_runtime_get_sync(&pdev->dev);
0978     if (ret < 0) {
0979         dev_err(&pdev->dev, "failed to resume SPI controller\n");
0980         goto err_rpm_put;
0981     }
0982 
0983     ret = devm_spi_register_controller(&pdev->dev, sctlr);
0984     if (ret)
0985         goto err_rpm_put;
0986 
0987     pm_runtime_mark_last_busy(&pdev->dev);
0988     pm_runtime_put_autosuspend(&pdev->dev);
0989 
0990     return 0;
0991 
0992 err_rpm_put:
0993     pm_runtime_put_noidle(&pdev->dev);
0994     pm_runtime_disable(&pdev->dev);
0995 disable_clk:
0996     clk_disable_unprepare(ss->clk);
0997 release_dma:
0998     sprd_spi_dma_release(ss);
0999 free_controller:
1000     spi_controller_put(sctlr);
1001 
1002     return ret;
1003 }
1004 
1005 static int sprd_spi_remove(struct platform_device *pdev)
1006 {
1007     struct spi_controller *sctlr = platform_get_drvdata(pdev);
1008     struct sprd_spi *ss = spi_controller_get_devdata(sctlr);
1009     int ret;
1010 
1011     ret = pm_runtime_resume_and_get(ss->dev);
1012     if (ret < 0) {
1013         dev_err(ss->dev, "failed to resume SPI controller\n");
1014         return ret;
1015     }
1016 
1017     spi_controller_suspend(sctlr);
1018 
1019     if (ss->dma.enable)
1020         sprd_spi_dma_release(ss);
1021     clk_disable_unprepare(ss->clk);
1022     pm_runtime_put_noidle(&pdev->dev);
1023     pm_runtime_disable(&pdev->dev);
1024 
1025     return 0;
1026 }
1027 
1028 static int __maybe_unused sprd_spi_runtime_suspend(struct device *dev)
1029 {
1030     struct spi_controller *sctlr = dev_get_drvdata(dev);
1031     struct sprd_spi *ss = spi_controller_get_devdata(sctlr);
1032 
1033     if (ss->dma.enable)
1034         sprd_spi_dma_release(ss);
1035 
1036     clk_disable_unprepare(ss->clk);
1037 
1038     return 0;
1039 }
1040 
1041 static int __maybe_unused sprd_spi_runtime_resume(struct device *dev)
1042 {
1043     struct spi_controller *sctlr = dev_get_drvdata(dev);
1044     struct sprd_spi *ss = spi_controller_get_devdata(sctlr);
1045     int ret;
1046 
1047     ret = clk_prepare_enable(ss->clk);
1048     if (ret)
1049         return ret;
1050 
1051     if (!ss->dma.enable)
1052         return 0;
1053 
1054     ret = sprd_spi_dma_request(ss);
1055     if (ret)
1056         clk_disable_unprepare(ss->clk);
1057 
1058     return ret;
1059 }
1060 
1061 static const struct dev_pm_ops sprd_spi_pm_ops = {
1062     SET_RUNTIME_PM_OPS(sprd_spi_runtime_suspend,
1063                sprd_spi_runtime_resume, NULL)
1064 };
1065 
1066 static const struct of_device_id sprd_spi_of_match[] = {
1067     { .compatible = "sprd,sc9860-spi", },
1068     { /* sentinel */ }
1069 };
1070 MODULE_DEVICE_TABLE(of, sprd_spi_of_match);
1071 
1072 static struct platform_driver sprd_spi_driver = {
1073     .driver = {
1074         .name = "sprd-spi",
1075         .of_match_table = sprd_spi_of_match,
1076         .pm = &sprd_spi_pm_ops,
1077     },
1078     .probe = sprd_spi_probe,
1079     .remove  = sprd_spi_remove,
1080 };
1081 
1082 module_platform_driver(sprd_spi_driver);
1083 
1084 MODULE_DESCRIPTION("Spreadtrum SPI Controller driver");
1085 MODULE_AUTHOR("Lanqing Liu <lanqing.liu@spreadtrum.com>");
1086 MODULE_LICENSE("GPL v2");
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