drivers/spi/spi-sprd-adi.c

0001 /*
0002  * Copyright (C) 2017 Spreadtrum Communications Inc.
0003  *
0004  * SPDX-License-Identifier: GPL-2.0
0005  */
0006
0007 #include <linux/delay.h>
0008 #include <linux/hwspinlock.h>
0009 #include <linux/init.h>
0010 #include <linux/io.h>
0011 #include <linux/kernel.h>
0012 #include <linux/module.h>
0013 #include <linux/of.h>
0014 #include <linux/of_device.h>
0015 #include <linux/platform_device.h>
0016 #include <linux/reboot.h>
0017 #include <linux/spi/spi.h>
0018 #include <linux/sizes.h>
0019
0020 /* Registers definitions for ADI controller */
0021 #define REG_ADI_CTRL0           0x4
0022 #define REG_ADI_CHN_PRIL        0x8
0023 #define REG_ADI_CHN_PRIH        0xc
0024 #define REG_ADI_INT_EN          0x10
0025 #define REG_ADI_INT_RAW         0x14
0026 #define REG_ADI_INT_MASK        0x18
0027 #define REG_ADI_INT_CLR         0x1c
0028 #define REG_ADI_GSSI_CFG0       0x20
0029 #define REG_ADI_GSSI_CFG1       0x24
0030 #define REG_ADI_RD_CMD          0x28
0031 #define REG_ADI_RD_DATA         0x2c
0032 #define REG_ADI_ARM_FIFO_STS        0x30
0033 #define REG_ADI_STS         0x34
0034 #define REG_ADI_EVT_FIFO_STS        0x38
0035 #define REG_ADI_ARM_CMD_STS     0x3c
0036 #define REG_ADI_CHN_EN          0x40
0037 #define REG_ADI_CHN_ADDR(id)        (0x44 + (id - 2) * 4)
0038 #define REG_ADI_CHN_EN1         0x20c
0039
0040 /* Bits definitions for register REG_ADI_GSSI_CFG0 */
0041 #define BIT_CLK_ALL_ON          BIT(30)
0042
0043 /* Bits definitions for register REG_ADI_RD_DATA */
0044 #define BIT_RD_CMD_BUSY         BIT(31)
0045 #define RD_ADDR_SHIFT           16
0046 #define RD_VALUE_MASK           GENMASK(15, 0)
0047 #define RD_ADDR_MASK            GENMASK(30, 16)
0048
0049 /* Bits definitions for register REG_ADI_ARM_FIFO_STS */
0050 #define BIT_FIFO_FULL           BIT(11)
0051 #define BIT_FIFO_EMPTY          BIT(10)
0052
0053 /*
0054  * ADI slave devices include RTC, ADC, regulator, charger, thermal and so on.
0055  * ADI supports 12/14bit address for r2p0, and additional 17bit for r3p0 or
0056  * later versions. Since bit[1:0] are zero, so the spec describe them as
0057  * 10/12/15bit address mode.
0058  * The 10bit mode supports sigle slave, 12/15bit mode supports 3 slave, the
0059  * high two bits is slave_id.
0060  * The slave devices address offset is 0x8000 for 10/12bit address mode,
0061  * and 0x20000 for 15bit mode.
0062  */
0063 #define ADI_10BIT_SLAVE_ADDR_SIZE   SZ_4K
0064 #define ADI_10BIT_SLAVE_OFFSET      0x8000
0065 #define ADI_12BIT_SLAVE_ADDR_SIZE   SZ_16K
0066 #define ADI_12BIT_SLAVE_OFFSET      0x8000
0067 #define ADI_15BIT_SLAVE_ADDR_SIZE   SZ_128K
0068 #define ADI_15BIT_SLAVE_OFFSET      0x20000
0069
0070 /* Timeout (ms) for the trylock of hardware spinlocks */
0071 #define ADI_HWSPINLOCK_TIMEOUT      5000
0072 /*
0073  * ADI controller has 50 channels including 2 software channels
0074  * and 48 hardware channels.
0075  */
0076 #define ADI_HW_CHNS         50
0077
0078 #define ADI_FIFO_DRAIN_TIMEOUT      1000
0079 #define ADI_READ_TIMEOUT        2000
0080
0081 /*
0082  * Read back address from REG_ADI_RD_DATA bit[30:16] which maps to:
0083  * REG_ADI_RD_CMD bit[14:0] for r2p0
0084  * REG_ADI_RD_CMD bit[16:2] for r3p0
0085  */
0086 #define RDBACK_ADDR_MASK_R2     GENMASK(14, 0)
0087 #define RDBACK_ADDR_MASK_R3     GENMASK(16, 2)
0088 #define RDBACK_ADDR_SHIFT_R3        2
0089
0090 /* Registers definitions for PMIC watchdog controller */
0091 #define REG_WDG_LOAD_LOW        0x0
0092 #define REG_WDG_LOAD_HIGH       0x4
0093 #define REG_WDG_CTRL            0x8
0094 #define REG_WDG_LOCK            0x20
0095
0096 /* Bits definitions for register REG_WDG_CTRL */
0097 #define BIT_WDG_RUN         BIT(1)
0098 #define BIT_WDG_NEW         BIT(2)
0099 #define BIT_WDG_RST         BIT(3)
0100
0101 /* Bits definitions for register REG_MODULE_EN */
0102 #define BIT_WDG_EN          BIT(2)
0103
0104 /* Registers definitions for PMIC */
0105 #define PMIC_RST_STATUS         0xee8
0106 #define PMIC_MODULE_EN          0xc08
0107 #define PMIC_CLK_EN         0xc18
0108 #define PMIC_WDG_BASE           0x80
0109
0110 /* Definition of PMIC reset status register */
0111 #define HWRST_STATUS_SECURITY       0x02
0112 #define HWRST_STATUS_RECOVERY       0x20
0113 #define HWRST_STATUS_NORMAL     0x40
0114 #define HWRST_STATUS_ALARM      0x50
0115 #define HWRST_STATUS_SLEEP      0x60
0116 #define HWRST_STATUS_FASTBOOT       0x30
0117 #define HWRST_STATUS_SPECIAL        0x70
0118 #define HWRST_STATUS_PANIC      0x80
0119 #define HWRST_STATUS_CFTREBOOT      0x90
0120 #define HWRST_STATUS_AUTODLOADER    0xa0
0121 #define HWRST_STATUS_IQMODE     0xb0
0122 #define HWRST_STATUS_SPRDISK        0xc0
0123 #define HWRST_STATUS_FACTORYTEST    0xe0
0124 #define HWRST_STATUS_WATCHDOG       0xf0
0125
0126 /* Use default timeout 50 ms that converts to watchdog values */
0127 #define WDG_LOAD_VAL            ((50 * 32768) / 1000)
0128 #define WDG_LOAD_MASK           GENMASK(15, 0)
0129 #define WDG_UNLOCK_KEY          0xe551
0130
0131 struct sprd_adi_wdg {
0132     u32 base;
0133     u32 rst_sts;
0134     u32 wdg_en;
0135     u32 wdg_clk;
0136 };
0137
0138 struct sprd_adi_data {
0139     u32 slave_offset;
0140     u32 slave_addr_size;
0141     int (*read_check)(u32 val, u32 reg);
0142     int (*restart)(struct notifier_block *this,
0143                unsigned long mode, void *cmd);
0144     void (*wdg_rst)(void *p);
0145 };
0146
0147 struct sprd_adi {
0148     struct spi_controller   *ctlr;
0149     struct device       *dev;
0150     void __iomem        *base;
0151     struct hwspinlock   *hwlock;
0152     unsigned long       slave_vbase;
0153     unsigned long       slave_pbase;
0154     struct notifier_block   restart_handler;
0155     const struct sprd_adi_data *data;
0156 };
0157
0158 static int sprd_adi_check_addr(struct sprd_adi *sadi, u32 reg)
0159 {
0160     if (reg >= sadi->data->slave_addr_size) {
0161         dev_err(sadi->dev,
0162             "slave address offset is incorrect, reg = 0x%x\n",
0163             reg);
0164         return -EINVAL;
0165     }
0166
0167     return 0;
0168 }
0169
0170 static int sprd_adi_drain_fifo(struct sprd_adi *sadi)
0171 {
0172     u32 timeout = ADI_FIFO_DRAIN_TIMEOUT;
0173     u32 sts;
0174
0175     do {
0176         sts = readl_relaxed(sadi->base + REG_ADI_ARM_FIFO_STS);
0177         if (sts & BIT_FIFO_EMPTY)
0178             break;
0179
0180         cpu_relax();
0181     } while (--timeout);
0182
0183     if (timeout == 0) {
0184         dev_err(sadi->dev, "drain write fifo timeout\n");
0185         return -EBUSY;
0186     }
0187
0188     return 0;
0189 }
0190
0191 static int sprd_adi_fifo_is_full(struct sprd_adi *sadi)
0192 {
0193     return readl_relaxed(sadi->base + REG_ADI_ARM_FIFO_STS) & BIT_FIFO_FULL;
0194 }
0195
0196 static int sprd_adi_read_check(u32 val, u32 addr)
0197 {
0198     u32 rd_addr;
0199
0200     rd_addr = (val & RD_ADDR_MASK) >> RD_ADDR_SHIFT;
0201
0202     if (rd_addr != addr) {
0203         pr_err("ADI read error, addr = 0x%x, val = 0x%x\n", addr, val);
0204         return -EIO;
0205     }
0206
0207     return 0;
0208 }
0209
0210 static int sprd_adi_read_check_r2(u32 val, u32 reg)
0211 {
0212     return sprd_adi_read_check(val, reg & RDBACK_ADDR_MASK_R2);
0213 }
0214
0215 static int sprd_adi_read_check_r3(u32 val, u32 reg)
0216 {
0217     return sprd_adi_read_check(val, (reg & RDBACK_ADDR_MASK_R3) >> RDBACK_ADDR_SHIFT_R3);
0218 }
0219
0220 static int sprd_adi_read(struct sprd_adi *sadi, u32 reg, u32 *read_val)
0221 {
0222     int read_timeout = ADI_READ_TIMEOUT;
0223     unsigned long flags;
0224     u32 val;
0225     int ret = 0;
0226
0227     if (sadi->hwlock) {
0228         ret = hwspin_lock_timeout_irqsave(sadi->hwlock,
0229                           ADI_HWSPINLOCK_TIMEOUT,
0230                           &flags);
0231         if (ret) {
0232             dev_err(sadi->dev, "get the hw lock failed\n");
0233             return ret;
0234         }
0235     }
0236
0237     ret = sprd_adi_check_addr(sadi, reg);
0238     if (ret)
0239         goto out;
0240
0241     /*
0242      * Set the slave address offset need to read into RD_CMD register,
0243      * then ADI controller will start to transfer automatically.
0244      */
0245     writel_relaxed(reg, sadi->base + REG_ADI_RD_CMD);
0246
0247     /*
0248      * Wait read operation complete, the BIT_RD_CMD_BUSY will be set
0249      * simultaneously when writing read command to register, and the
0250      * BIT_RD_CMD_BUSY will be cleared after the read operation is
0251      * completed.
0252      */
0253     do {
0254         val = readl_relaxed(sadi->base + REG_ADI_RD_DATA);
0255         if (!(val & BIT_RD_CMD_BUSY))
0256             break;
0257
0258         cpu_relax();
0259     } while (--read_timeout);
0260
0261     if (read_timeout == 0) {
0262         dev_err(sadi->dev, "ADI read timeout\n");
0263         ret = -EBUSY;
0264         goto out;
0265     }
0266
0267     /*
0268      * The return value before adi r5p0 includes data and read register
0269      * address, from bit 0to bit 15 are data, and from bit 16 to bit 30
0270      * are read register address. Then we can check the returned register
0271      * address to validate data.
0272      */
0273     if (sadi->data->read_check) {
0274         ret = sadi->data->read_check(val, reg);
0275         if (ret < 0)
0276             goto out;
0277     }
0278
0279     *read_val = val & RD_VALUE_MASK;
0280
0281 out:
0282     if (sadi->hwlock)
0283         hwspin_unlock_irqrestore(sadi->hwlock, &flags);
0284     return ret;
0285 }
0286
0287 static int sprd_adi_write(struct sprd_adi *sadi, u32 reg, u32 val)
0288 {
0289     u32 timeout = ADI_FIFO_DRAIN_TIMEOUT;
0290     unsigned long flags;
0291     int ret;
0292
0293     if (sadi->hwlock) {
0294         ret = hwspin_lock_timeout_irqsave(sadi->hwlock,
0295                           ADI_HWSPINLOCK_TIMEOUT,
0296                           &flags);
0297         if (ret) {
0298             dev_err(sadi->dev, "get the hw lock failed\n");
0299             return ret;
0300         }
0301     }
0302
0303     ret = sprd_adi_check_addr(sadi, reg);
0304     if (ret)
0305         goto out;
0306
0307     ret = sprd_adi_drain_fifo(sadi);
0308     if (ret < 0)
0309         goto out;
0310
0311     /*
0312      * we should wait for write fifo is empty before writing data to PMIC
0313      * registers.
0314      */
0315     do {
0316         if (!sprd_adi_fifo_is_full(sadi)) {
0317             /* we need virtual register address to write. */
0318             writel_relaxed(val, (void __iomem *)(sadi->slave_vbase + reg));
0319             break;
0320         }
0321
0322         cpu_relax();
0323     } while (--timeout);
0324
0325     if (timeout == 0) {
0326         dev_err(sadi->dev, "write fifo is full\n");
0327         ret = -EBUSY;
0328     }
0329
0330 out:
0331     if (sadi->hwlock)
0332         hwspin_unlock_irqrestore(sadi->hwlock, &flags);
0333     return ret;
0334 }
0335
0336 static int sprd_adi_transfer_one(struct spi_controller *ctlr,
0337                  struct spi_device *spi_dev,
0338                  struct spi_transfer *t)
0339 {
0340     struct sprd_adi *sadi = spi_controller_get_devdata(ctlr);
0341     u32 reg, val;
0342     int ret;
0343
0344     if (t->rx_buf) {
0345         reg = *(u32 *)t->rx_buf;
0346         ret = sprd_adi_read(sadi, reg, &val);
0347         *(u32 *)t->rx_buf = val;
0348     } else if (t->tx_buf) {
0349         u32 *p = (u32 *)t->tx_buf;
0350         reg = *p++;
0351         val = *p;
0352         ret = sprd_adi_write(sadi, reg, val);
0353     } else {
0354         dev_err(sadi->dev, "no buffer for transfer\n");
0355         ret = -EINVAL;
0356     }
0357
0358     return ret;
0359 }
0360
0361 static void sprd_adi_set_wdt_rst_mode(void *p)
0362 {
0363 #if IS_ENABLED(CONFIG_SPRD_WATCHDOG)
0364     u32 val;
0365     struct sprd_adi *sadi = (struct sprd_adi *)p;
0366
0367     /* Init watchdog reset mode */
0368     sprd_adi_read(sadi, PMIC_RST_STATUS, &val);
0369     val |= HWRST_STATUS_WATCHDOG;
0370     sprd_adi_write(sadi, PMIC_RST_STATUS, val);
0371 #endif
0372 }
0373
0374 static int sprd_adi_restart(struct notifier_block *this, unsigned long mode,
0375                   void *cmd, struct sprd_adi_wdg *wdg)
0376 {
0377     struct sprd_adi *sadi = container_of(this, struct sprd_adi,
0378                          restart_handler);
0379     u32 val, reboot_mode = 0;
0380
0381     if (!cmd)
0382         reboot_mode = HWRST_STATUS_NORMAL;
0383     else if (!strncmp(cmd, "recovery", 8))
0384         reboot_mode = HWRST_STATUS_RECOVERY;
0385     else if (!strncmp(cmd, "alarm", 5))
0386         reboot_mode = HWRST_STATUS_ALARM;
0387     else if (!strncmp(cmd, "fastsleep", 9))
0388         reboot_mode = HWRST_STATUS_SLEEP;
0389     else if (!strncmp(cmd, "bootloader", 10))
0390         reboot_mode = HWRST_STATUS_FASTBOOT;
0391     else if (!strncmp(cmd, "panic", 5))
0392         reboot_mode = HWRST_STATUS_PANIC;
0393     else if (!strncmp(cmd, "special", 7))
0394         reboot_mode = HWRST_STATUS_SPECIAL;
0395     else if (!strncmp(cmd, "cftreboot", 9))
0396         reboot_mode = HWRST_STATUS_CFTREBOOT;
0397     else if (!strncmp(cmd, "autodloader", 11))
0398         reboot_mode = HWRST_STATUS_AUTODLOADER;
0399     else if (!strncmp(cmd, "iqmode", 6))
0400         reboot_mode = HWRST_STATUS_IQMODE;
0401     else if (!strncmp(cmd, "sprdisk", 7))
0402         reboot_mode = HWRST_STATUS_SPRDISK;
0403     else if (!strncmp(cmd, "tospanic", 8))
0404         reboot_mode = HWRST_STATUS_SECURITY;
0405     else if (!strncmp(cmd, "factorytest", 11))
0406         reboot_mode = HWRST_STATUS_FACTORYTEST;
0407     else
0408         reboot_mode = HWRST_STATUS_NORMAL;
0409
0410     /* Record the reboot mode */
0411     sprd_adi_read(sadi, wdg->rst_sts, &val);
0412     val &= ~HWRST_STATUS_WATCHDOG;
0413     val |= reboot_mode;
0414     sprd_adi_write(sadi, wdg->rst_sts, val);
0415
0416     /* Enable the interface clock of the watchdog */
0417     sprd_adi_read(sadi, wdg->wdg_en, &val);
0418     val |= BIT_WDG_EN;
0419     sprd_adi_write(sadi, wdg->wdg_en, val);
0420
0421     /* Enable the work clock of the watchdog */
0422     sprd_adi_read(sadi, wdg->wdg_clk, &val);
0423     val |= BIT_WDG_EN;
0424     sprd_adi_write(sadi, wdg->wdg_clk, val);
0425
0426     /* Unlock the watchdog */
0427     sprd_adi_write(sadi, wdg->base + REG_WDG_LOCK, WDG_UNLOCK_KEY);
0428
0429     sprd_adi_read(sadi, wdg->base + REG_WDG_CTRL, &val);
0430     val |= BIT_WDG_NEW;
0431     sprd_adi_write(sadi, wdg->base + REG_WDG_CTRL, val);
0432
0433     /* Load the watchdog timeout value, 50ms is always enough. */
0434     sprd_adi_write(sadi, wdg->base + REG_WDG_LOAD_HIGH, 0);
0435     sprd_adi_write(sadi, wdg->base + REG_WDG_LOAD_LOW,
0436                WDG_LOAD_VAL & WDG_LOAD_MASK);
0437
0438     /* Start the watchdog to reset system */
0439     sprd_adi_read(sadi, wdg->base + REG_WDG_CTRL, &val);
0440     val |= BIT_WDG_RUN | BIT_WDG_RST;
0441     sprd_adi_write(sadi, wdg->base + REG_WDG_CTRL, val);
0442
0443     /* Lock the watchdog */
0444     sprd_adi_write(sadi, wdg->base + REG_WDG_LOCK, ~WDG_UNLOCK_KEY);
0445
0446     mdelay(1000);
0447
0448     dev_emerg(sadi->dev, "Unable to restart system\n");
0449     return NOTIFY_DONE;
0450 }
0451
0452 static int sprd_adi_restart_sc9860(struct notifier_block *this,
0453                        unsigned long mode, void *cmd)
0454 {
0455     struct sprd_adi_wdg wdg = {
0456         .base = PMIC_WDG_BASE,
0457         .rst_sts = PMIC_RST_STATUS,
0458         .wdg_en = PMIC_MODULE_EN,
0459         .wdg_clk = PMIC_CLK_EN,
0460     };
0461
0462     return sprd_adi_restart(this, mode, cmd, &wdg);
0463 }
0464
0465 static void sprd_adi_hw_init(struct sprd_adi *sadi)
0466 {
0467     struct device_node *np = sadi->dev->of_node;
0468     int i, size, chn_cnt;
0469     const __be32 *list;
0470     u32 tmp;
0471
0472     /* Set all channels as default priority */
0473     writel_relaxed(0, sadi->base + REG_ADI_CHN_PRIL);
0474     writel_relaxed(0, sadi->base + REG_ADI_CHN_PRIH);
0475
0476     /* Set clock auto gate mode */
0477     tmp = readl_relaxed(sadi->base + REG_ADI_GSSI_CFG0);
0478     tmp &= ~BIT_CLK_ALL_ON;
0479     writel_relaxed(tmp, sadi->base + REG_ADI_GSSI_CFG0);
0480
0481     /* Set hardware channels setting */
0482     list = of_get_property(np, "sprd,hw-channels", &size);
0483     if (!list || !size) {
0484         dev_info(sadi->dev, "no hw channels setting in node\n");
0485         return;
0486     }
0487
0488     chn_cnt = size / 8;
0489     for (i = 0; i < chn_cnt; i++) {
0490         u32 value;
0491         u32 chn_id = be32_to_cpu(*list++);
0492         u32 chn_config = be32_to_cpu(*list++);
0493
0494         /* Channel 0 and 1 are software channels */
0495         if (chn_id < 2)
0496             continue;
0497
0498         writel_relaxed(chn_config, sadi->base +
0499                    REG_ADI_CHN_ADDR(chn_id));
0500
0501         if (chn_id < 32) {
0502             value = readl_relaxed(sadi->base + REG_ADI_CHN_EN);
0503             value |= BIT(chn_id);
0504             writel_relaxed(value, sadi->base + REG_ADI_CHN_EN);
0505         } else if (chn_id < ADI_HW_CHNS) {
0506             value = readl_relaxed(sadi->base + REG_ADI_CHN_EN1);
0507             value |= BIT(chn_id - 32);
0508             writel_relaxed(value, sadi->base + REG_ADI_CHN_EN1);
0509         }
0510     }
0511 }
0512
0513 static int sprd_adi_probe(struct platform_device *pdev)
0514 {
0515     struct device_node *np = pdev->dev.of_node;
0516     const struct sprd_adi_data *data;
0517     struct spi_controller *ctlr;
0518     struct sprd_adi *sadi;
0519     struct resource *res;
0520     u16 num_chipselect;
0521     int ret;
0522
0523     if (!np) {
0524         dev_err(&pdev->dev, "can not find the adi bus node\n");
0525         return -ENODEV;
0526     }
0527
0528     data = of_device_get_match_data(&pdev->dev);
0529     if (!data) {
0530         dev_err(&pdev->dev, "no matching driver data found\n");
0531         return -EINVAL;
0532     }
0533
0534     pdev->id = of_alias_get_id(np, "spi");
0535     num_chipselect = of_get_child_count(np);
0536
0537     ctlr = spi_alloc_master(&pdev->dev, sizeof(struct sprd_adi));
0538     if (!ctlr)
0539         return -ENOMEM;
0540
0541     dev_set_drvdata(&pdev->dev, ctlr);
0542     sadi = spi_controller_get_devdata(ctlr);
0543
0544     res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
0545     sadi->base = devm_ioremap_resource(&pdev->dev, res);
0546     if (IS_ERR(sadi->base)) {
0547         ret = PTR_ERR(sadi->base);
0548         goto put_ctlr;
0549     }
0550
0551     sadi->slave_vbase = (unsigned long)sadi->base +
0552                 data->slave_offset;
0553     sadi->slave_pbase = res->start + data->slave_offset;
0554     sadi->ctlr = ctlr;
0555     sadi->dev = &pdev->dev;
0556     sadi->data = data;
0557     ret = of_hwspin_lock_get_id(np, 0);
0558     if (ret > 0 || (IS_ENABLED(CONFIG_HWSPINLOCK) && ret == 0)) {
0559         sadi->hwlock =
0560             devm_hwspin_lock_request_specific(&pdev->dev, ret);
0561         if (!sadi->hwlock) {
0562             ret = -ENXIO;
0563             goto put_ctlr;
0564         }
0565     } else {
0566         switch (ret) {
0567         case -ENOENT:
0568             dev_info(&pdev->dev, "no hardware spinlock supplied\n");
0569             break;
0570         default:
0571             dev_err_probe(&pdev->dev, ret, "failed to find hwlock id\n");
0572             goto put_ctlr;
0573         }
0574     }
0575
0576     sprd_adi_hw_init(sadi);
0577
0578     if (sadi->data->wdg_rst)
0579         sadi->data->wdg_rst(sadi);
0580
0581     ctlr->dev.of_node = pdev->dev.of_node;
0582     ctlr->bus_num = pdev->id;
0583     ctlr->num_chipselect = num_chipselect;
0584     ctlr->flags = SPI_MASTER_HALF_DUPLEX;
0585     ctlr->bits_per_word_mask = 0;
0586     ctlr->transfer_one = sprd_adi_transfer_one;
0587
0588     ret = devm_spi_register_controller(&pdev->dev, ctlr);
0589     if (ret) {
0590         dev_err(&pdev->dev, "failed to register SPI controller\n");
0591         goto put_ctlr;
0592     }
0593
0594     if (sadi->data->restart) {
0595         sadi->restart_handler.notifier_call = sadi->data->restart;
0596         sadi->restart_handler.priority = 128;
0597         ret = register_restart_handler(&sadi->restart_handler);
0598         if (ret) {
0599             dev_err(&pdev->dev, "can not register restart handler\n");
0600             goto put_ctlr;
0601         }
0602     }
0603
0604     return 0;
0605
0606 put_ctlr:
0607     spi_controller_put(ctlr);
0608     return ret;
0609 }
0610
0611 static int sprd_adi_remove(struct platform_device *pdev)
0612 {
0613     struct spi_controller *ctlr = dev_get_drvdata(&pdev->dev);
0614     struct sprd_adi *sadi = spi_controller_get_devdata(ctlr);
0615
0616     unregister_restart_handler(&sadi->restart_handler);
0617     return 0;
0618 }
0619
0620 static struct sprd_adi_data sc9860_data = {
0621     .slave_offset = ADI_10BIT_SLAVE_OFFSET,
0622     .slave_addr_size = ADI_10BIT_SLAVE_ADDR_SIZE,
0623     .read_check = sprd_adi_read_check_r2,
0624     .restart = sprd_adi_restart_sc9860,
0625     .wdg_rst = sprd_adi_set_wdt_rst_mode,
0626 };
0627
0628 static struct sprd_adi_data sc9863_data = {
0629     .slave_offset = ADI_12BIT_SLAVE_OFFSET,
0630     .slave_addr_size = ADI_12BIT_SLAVE_ADDR_SIZE,
0631     .read_check = sprd_adi_read_check_r3,
0632 };
0633
0634 static struct sprd_adi_data ums512_data = {
0635     .slave_offset = ADI_15BIT_SLAVE_OFFSET,
0636     .slave_addr_size = ADI_15BIT_SLAVE_ADDR_SIZE,
0637     .read_check = sprd_adi_read_check_r3,
0638 };
0639
0640 static const struct of_device_id sprd_adi_of_match[] = {
0641     {
0642         .compatible = "sprd,sc9860-adi",
0643         .data = &sc9860_data,
0644     },
0645     {
0646         .compatible = "sprd,sc9863-adi",
0647         .data = &sc9863_data,
0648     },
0649     {
0650         .compatible = "sprd,ums512-adi",
0651         .data = &ums512_data,
0652     },
0653     { },
0654 };
0655 MODULE_DEVICE_TABLE(of, sprd_adi_of_match);
0656
0657 static struct platform_driver sprd_adi_driver = {
0658     .driver = {
0659         .name = "sprd-adi",
0660         .of_match_table = sprd_adi_of_match,
0661     },
0662     .probe = sprd_adi_probe,
0663     .remove = sprd_adi_remove,
0664 };
0665 module_platform_driver(sprd_adi_driver);
0666
0667 MODULE_DESCRIPTION("Spreadtrum ADI Controller Driver");
0668 MODULE_AUTHOR("Baolin Wang <Baolin.Wang@spreadtrum.com>");
0669 MODULE_LICENSE("GPL v2");