drivers/spi/spi-slave-mt27xx.c

0001 // SPDX-License-Identifier: GPL-2.0+
0002 // Copyright (c) 2018 MediaTek Inc.
0003
0004 #include <linux/clk.h>
0005 #include <linux/device.h>
0006 #include <linux/dma-mapping.h>
0007 #include <linux/err.h>
0008 #include <linux/interrupt.h>
0009 #include <linux/module.h>
0010 #include <linux/platform_device.h>
0011 #include <linux/pm_runtime.h>
0012 #include <linux/spi/spi.h>
0013 #include <linux/of.h>
0014
0015
0016 #define SPIS_IRQ_EN_REG     0x0
0017 #define SPIS_IRQ_CLR_REG    0x4
0018 #define SPIS_IRQ_ST_REG     0x8
0019 #define SPIS_IRQ_MASK_REG   0xc
0020 #define SPIS_CFG_REG        0x10
0021 #define SPIS_RX_DATA_REG    0x14
0022 #define SPIS_TX_DATA_REG    0x18
0023 #define SPIS_RX_DST_REG     0x1c
0024 #define SPIS_TX_SRC_REG     0x20
0025 #define SPIS_DMA_CFG_REG    0x30
0026 #define SPIS_SOFT_RST_REG   0x40
0027
0028 /* SPIS_IRQ_EN_REG */
0029 #define DMA_DONE_EN     BIT(7)
0030 #define DATA_DONE_EN        BIT(2)
0031 #define RSTA_DONE_EN        BIT(1)
0032 #define CMD_INVALID_EN      BIT(0)
0033
0034 /* SPIS_IRQ_ST_REG */
0035 #define DMA_DONE_ST     BIT(7)
0036 #define DATA_DONE_ST        BIT(2)
0037 #define RSTA_DONE_ST        BIT(1)
0038 #define CMD_INVALID_ST      BIT(0)
0039
0040 /* SPIS_IRQ_MASK_REG */
0041 #define DMA_DONE_MASK       BIT(7)
0042 #define DATA_DONE_MASK      BIT(2)
0043 #define RSTA_DONE_MASK      BIT(1)
0044 #define CMD_INVALID_MASK    BIT(0)
0045
0046 /* SPIS_CFG_REG */
0047 #define SPIS_TX_ENDIAN      BIT(7)
0048 #define SPIS_RX_ENDIAN      BIT(6)
0049 #define SPIS_TXMSBF     BIT(5)
0050 #define SPIS_RXMSBF     BIT(4)
0051 #define SPIS_CPHA       BIT(3)
0052 #define SPIS_CPOL       BIT(2)
0053 #define SPIS_TX_EN      BIT(1)
0054 #define SPIS_RX_EN      BIT(0)
0055
0056 /* SPIS_DMA_CFG_REG */
0057 #define TX_DMA_TRIG_EN      BIT(31)
0058 #define TX_DMA_EN       BIT(30)
0059 #define RX_DMA_EN       BIT(29)
0060 #define TX_DMA_LEN      0xfffff
0061
0062 /* SPIS_SOFT_RST_REG */
0063 #define SPIS_DMA_ADDR_EN    BIT(1)
0064 #define SPIS_SOFT_RST       BIT(0)
0065
0066 struct mtk_spi_slave {
0067     struct device *dev;
0068     void __iomem *base;
0069     struct clk *spi_clk;
0070     struct completion xfer_done;
0071     struct spi_transfer *cur_transfer;
0072     bool slave_aborted;
0073     const struct mtk_spi_compatible *dev_comp;
0074 };
0075
0076 struct mtk_spi_compatible {
0077     const u32 max_fifo_size;
0078     bool must_rx;
0079 };
0080
0081 static const struct mtk_spi_compatible mt2712_compat = {
0082     .max_fifo_size = 512,
0083 };
0084 static const struct mtk_spi_compatible mt8195_compat = {
0085     .max_fifo_size = 128,
0086     .must_rx = true,
0087 };
0088
0089 static const struct of_device_id mtk_spi_slave_of_match[] = {
0090     { .compatible = "mediatek,mt2712-spi-slave",
0091       .data = (void *)&mt2712_compat,},
0092     { .compatible = "mediatek,mt8195-spi-slave",
0093       .data = (void *)&mt8195_compat,},
0094     {}
0095 };
0096 MODULE_DEVICE_TABLE(of, mtk_spi_slave_of_match);
0097
0098 static void mtk_spi_slave_disable_dma(struct mtk_spi_slave *mdata)
0099 {
0100     u32 reg_val;
0101
0102     reg_val = readl(mdata->base + SPIS_DMA_CFG_REG);
0103     reg_val &= ~RX_DMA_EN;
0104     reg_val &= ~TX_DMA_EN;
0105     writel(reg_val, mdata->base + SPIS_DMA_CFG_REG);
0106 }
0107
0108 static void mtk_spi_slave_disable_xfer(struct mtk_spi_slave *mdata)
0109 {
0110     u32 reg_val;
0111
0112     reg_val = readl(mdata->base + SPIS_CFG_REG);
0113     reg_val &= ~SPIS_TX_EN;
0114     reg_val &= ~SPIS_RX_EN;
0115     writel(reg_val, mdata->base + SPIS_CFG_REG);
0116 }
0117
0118 static int mtk_spi_slave_wait_for_completion(struct mtk_spi_slave *mdata)
0119 {
0120     if (wait_for_completion_interruptible(&mdata->xfer_done) ||
0121         mdata->slave_aborted) {
0122         dev_err(mdata->dev, "interrupted\n");
0123         return -EINTR;
0124     }
0125
0126     return 0;
0127 }
0128
0129 static int mtk_spi_slave_prepare_message(struct spi_controller *ctlr,
0130                      struct spi_message *msg)
0131 {
0132     struct mtk_spi_slave *mdata = spi_controller_get_devdata(ctlr);
0133     struct spi_device *spi = msg->spi;
0134     bool cpha, cpol;
0135     u32 reg_val;
0136
0137     cpha = spi->mode & SPI_CPHA ? 1 : 0;
0138     cpol = spi->mode & SPI_CPOL ? 1 : 0;
0139
0140     reg_val = readl(mdata->base + SPIS_CFG_REG);
0141     if (cpha)
0142         reg_val |= SPIS_CPHA;
0143     else
0144         reg_val &= ~SPIS_CPHA;
0145     if (cpol)
0146         reg_val |= SPIS_CPOL;
0147     else
0148         reg_val &= ~SPIS_CPOL;
0149
0150     if (spi->mode & SPI_LSB_FIRST)
0151         reg_val &= ~(SPIS_TXMSBF | SPIS_RXMSBF);
0152     else
0153         reg_val |= SPIS_TXMSBF | SPIS_RXMSBF;
0154
0155     reg_val &= ~SPIS_TX_ENDIAN;
0156     reg_val &= ~SPIS_RX_ENDIAN;
0157     writel(reg_val, mdata->base + SPIS_CFG_REG);
0158
0159     return 0;
0160 }
0161
0162 static int mtk_spi_slave_fifo_transfer(struct spi_controller *ctlr,
0163                        struct spi_device *spi,
0164                        struct spi_transfer *xfer)
0165 {
0166     struct mtk_spi_slave *mdata = spi_controller_get_devdata(ctlr);
0167     int reg_val, cnt, remainder, ret;
0168
0169     writel(SPIS_SOFT_RST, mdata->base + SPIS_SOFT_RST_REG);
0170
0171     reg_val = readl(mdata->base + SPIS_CFG_REG);
0172     if (xfer->rx_buf)
0173         reg_val |= SPIS_RX_EN;
0174     if (xfer->tx_buf)
0175         reg_val |= SPIS_TX_EN;
0176     writel(reg_val, mdata->base + SPIS_CFG_REG);
0177
0178     cnt = xfer->len / 4;
0179     if (xfer->tx_buf)
0180         iowrite32_rep(mdata->base + SPIS_TX_DATA_REG,
0181                   xfer->tx_buf, cnt);
0182
0183     remainder = xfer->len % 4;
0184     if (xfer->tx_buf && remainder > 0) {
0185         reg_val = 0;
0186         memcpy(&reg_val, xfer->tx_buf + cnt * 4, remainder);
0187         writel(reg_val, mdata->base + SPIS_TX_DATA_REG);
0188     }
0189
0190     ret = mtk_spi_slave_wait_for_completion(mdata);
0191     if (ret) {
0192         mtk_spi_slave_disable_xfer(mdata);
0193         writel(SPIS_SOFT_RST, mdata->base + SPIS_SOFT_RST_REG);
0194     }
0195
0196     return ret;
0197 }
0198
0199 static int mtk_spi_slave_dma_transfer(struct spi_controller *ctlr,
0200                       struct spi_device *spi,
0201                       struct spi_transfer *xfer)
0202 {
0203     struct mtk_spi_slave *mdata = spi_controller_get_devdata(ctlr);
0204     struct device *dev = mdata->dev;
0205     int reg_val, ret;
0206
0207     writel(SPIS_SOFT_RST, mdata->base + SPIS_SOFT_RST_REG);
0208
0209     if (xfer->tx_buf) {
0210         /* tx_buf is a const void* where we need a void * for
0211          * the dma mapping
0212          */
0213         void *nonconst_tx = (void *)xfer->tx_buf;
0214
0215         xfer->tx_dma = dma_map_single(dev, nonconst_tx,
0216                           xfer->len, DMA_TO_DEVICE);
0217         if (dma_mapping_error(dev, xfer->tx_dma)) {
0218             ret = -ENOMEM;
0219             goto disable_transfer;
0220         }
0221     }
0222
0223     if (xfer->rx_buf) {
0224         xfer->rx_dma = dma_map_single(dev, xfer->rx_buf,
0225                           xfer->len, DMA_FROM_DEVICE);
0226         if (dma_mapping_error(dev, xfer->rx_dma)) {
0227             ret = -ENOMEM;
0228             goto unmap_txdma;
0229         }
0230     }
0231
0232     writel(xfer->tx_dma, mdata->base + SPIS_TX_SRC_REG);
0233     writel(xfer->rx_dma, mdata->base + SPIS_RX_DST_REG);
0234
0235     writel(SPIS_DMA_ADDR_EN, mdata->base + SPIS_SOFT_RST_REG);
0236
0237     /* enable config reg tx rx_enable */
0238     reg_val = readl(mdata->base + SPIS_CFG_REG);
0239     if (xfer->tx_buf)
0240         reg_val |= SPIS_TX_EN;
0241     if (xfer->rx_buf)
0242         reg_val |= SPIS_RX_EN;
0243     writel(reg_val, mdata->base + SPIS_CFG_REG);
0244
0245     /* config dma */
0246     reg_val = 0;
0247     reg_val |= (xfer->len - 1) & TX_DMA_LEN;
0248     writel(reg_val, mdata->base + SPIS_DMA_CFG_REG);
0249
0250     reg_val = readl(mdata->base + SPIS_DMA_CFG_REG);
0251     if (xfer->tx_buf)
0252         reg_val |= TX_DMA_EN;
0253     if (xfer->rx_buf)
0254         reg_val |= RX_DMA_EN;
0255     reg_val |= TX_DMA_TRIG_EN;
0256     writel(reg_val, mdata->base + SPIS_DMA_CFG_REG);
0257
0258     ret = mtk_spi_slave_wait_for_completion(mdata);
0259     if (ret)
0260         goto unmap_rxdma;
0261
0262     return 0;
0263
0264 unmap_rxdma:
0265     if (xfer->rx_buf)
0266         dma_unmap_single(dev, xfer->rx_dma,
0267                  xfer->len, DMA_FROM_DEVICE);
0268
0269 unmap_txdma:
0270     if (xfer->tx_buf)
0271         dma_unmap_single(dev, xfer->tx_dma,
0272                  xfer->len, DMA_TO_DEVICE);
0273
0274 disable_transfer:
0275     mtk_spi_slave_disable_dma(mdata);
0276     mtk_spi_slave_disable_xfer(mdata);
0277     writel(SPIS_SOFT_RST, mdata->base + SPIS_SOFT_RST_REG);
0278
0279     return ret;
0280 }
0281
0282 static int mtk_spi_slave_transfer_one(struct spi_controller *ctlr,
0283                       struct spi_device *spi,
0284                       struct spi_transfer *xfer)
0285 {
0286     struct mtk_spi_slave *mdata = spi_controller_get_devdata(ctlr);
0287
0288     reinit_completion(&mdata->xfer_done);
0289     mdata->slave_aborted = false;
0290     mdata->cur_transfer = xfer;
0291
0292     if (xfer->len > mdata->dev_comp->max_fifo_size)
0293         return mtk_spi_slave_dma_transfer(ctlr, spi, xfer);
0294     else
0295         return mtk_spi_slave_fifo_transfer(ctlr, spi, xfer);
0296 }
0297
0298 static int mtk_spi_slave_setup(struct spi_device *spi)
0299 {
0300     struct mtk_spi_slave *mdata = spi_controller_get_devdata(spi->master);
0301     u32 reg_val;
0302
0303     reg_val = DMA_DONE_EN | DATA_DONE_EN |
0304           RSTA_DONE_EN | CMD_INVALID_EN;
0305     writel(reg_val, mdata->base + SPIS_IRQ_EN_REG);
0306
0307     reg_val = DMA_DONE_MASK | DATA_DONE_MASK |
0308           RSTA_DONE_MASK | CMD_INVALID_MASK;
0309     writel(reg_val, mdata->base + SPIS_IRQ_MASK_REG);
0310
0311     mtk_spi_slave_disable_dma(mdata);
0312     mtk_spi_slave_disable_xfer(mdata);
0313
0314     return 0;
0315 }
0316
0317 static int mtk_slave_abort(struct spi_controller *ctlr)
0318 {
0319     struct mtk_spi_slave *mdata = spi_controller_get_devdata(ctlr);
0320
0321     mdata->slave_aborted = true;
0322     complete(&mdata->xfer_done);
0323
0324     return 0;
0325 }
0326
0327 static irqreturn_t mtk_spi_slave_interrupt(int irq, void *dev_id)
0328 {
0329     struct spi_controller *ctlr = dev_id;
0330     struct mtk_spi_slave *mdata = spi_controller_get_devdata(ctlr);
0331     struct spi_transfer *trans = mdata->cur_transfer;
0332     u32 int_status, reg_val, cnt, remainder;
0333
0334     int_status = readl(mdata->base + SPIS_IRQ_ST_REG);
0335     writel(int_status, mdata->base + SPIS_IRQ_CLR_REG);
0336
0337     if (!trans)
0338         return IRQ_NONE;
0339
0340     if ((int_status & DMA_DONE_ST) &&
0341         ((int_status & DATA_DONE_ST) ||
0342         (int_status & RSTA_DONE_ST))) {
0343         writel(SPIS_SOFT_RST, mdata->base + SPIS_SOFT_RST_REG);
0344
0345         if (trans->tx_buf)
0346             dma_unmap_single(mdata->dev, trans->tx_dma,
0347                      trans->len, DMA_TO_DEVICE);
0348         if (trans->rx_buf)
0349             dma_unmap_single(mdata->dev, trans->rx_dma,
0350                      trans->len, DMA_FROM_DEVICE);
0351
0352         mtk_spi_slave_disable_dma(mdata);
0353         mtk_spi_slave_disable_xfer(mdata);
0354     }
0355
0356     if ((!(int_status & DMA_DONE_ST)) &&
0357         ((int_status & DATA_DONE_ST) ||
0358         (int_status & RSTA_DONE_ST))) {
0359         cnt = trans->len / 4;
0360         if (trans->rx_buf)
0361             ioread32_rep(mdata->base + SPIS_RX_DATA_REG,
0362                      trans->rx_buf, cnt);
0363         remainder = trans->len % 4;
0364         if (trans->rx_buf && remainder > 0) {
0365             reg_val = readl(mdata->base + SPIS_RX_DATA_REG);
0366             memcpy(trans->rx_buf + (cnt * 4),
0367                    &reg_val, remainder);
0368         }
0369
0370         mtk_spi_slave_disable_xfer(mdata);
0371     }
0372
0373     if (int_status & CMD_INVALID_ST) {
0374         dev_warn(&ctlr->dev, "cmd invalid\n");
0375         return IRQ_NONE;
0376     }
0377
0378     mdata->cur_transfer = NULL;
0379     complete(&mdata->xfer_done);
0380
0381     return IRQ_HANDLED;
0382 }
0383
0384 static int mtk_spi_slave_probe(struct platform_device *pdev)
0385 {
0386     struct spi_controller *ctlr;
0387     struct mtk_spi_slave *mdata;
0388     int irq, ret;
0389     const struct of_device_id *of_id;
0390
0391     ctlr = spi_alloc_slave(&pdev->dev, sizeof(*mdata));
0392     if (!ctlr) {
0393         dev_err(&pdev->dev, "failed to alloc spi slave\n");
0394         return -ENOMEM;
0395     }
0396
0397     ctlr->auto_runtime_pm = true;
0398     ctlr->dev.of_node = pdev->dev.of_node;
0399     ctlr->mode_bits = SPI_CPOL | SPI_CPHA;
0400     ctlr->mode_bits |= SPI_LSB_FIRST;
0401
0402     ctlr->prepare_message = mtk_spi_slave_prepare_message;
0403     ctlr->transfer_one = mtk_spi_slave_transfer_one;
0404     ctlr->setup = mtk_spi_slave_setup;
0405     ctlr->slave_abort = mtk_slave_abort;
0406
0407     of_id = of_match_node(mtk_spi_slave_of_match, pdev->dev.of_node);
0408     if (!of_id) {
0409         dev_err(&pdev->dev, "failed to probe of_node\n");
0410         ret = -EINVAL;
0411         goto err_put_ctlr;
0412     }
0413     mdata = spi_controller_get_devdata(ctlr);
0414     mdata->dev_comp = of_id->data;
0415
0416     if (mdata->dev_comp->must_rx)
0417         ctlr->flags = SPI_MASTER_MUST_RX;
0418
0419     platform_set_drvdata(pdev, ctlr);
0420
0421     init_completion(&mdata->xfer_done);
0422     mdata->dev = &pdev->dev;
0423     mdata->base = devm_platform_ioremap_resource(pdev, 0);
0424     if (IS_ERR(mdata->base)) {
0425         ret = PTR_ERR(mdata->base);
0426         goto err_put_ctlr;
0427     }
0428
0429     irq = platform_get_irq(pdev, 0);
0430     if (irq < 0) {
0431         ret = irq;
0432         goto err_put_ctlr;
0433     }
0434
0435     ret = devm_request_irq(&pdev->dev, irq, mtk_spi_slave_interrupt,
0436                    IRQF_TRIGGER_NONE, dev_name(&pdev->dev), ctlr);
0437     if (ret) {
0438         dev_err(&pdev->dev, "failed to register irq (%d)\n", ret);
0439         goto err_put_ctlr;
0440     }
0441
0442     mdata->spi_clk = devm_clk_get(&pdev->dev, "spi");
0443     if (IS_ERR(mdata->spi_clk)) {
0444         ret = PTR_ERR(mdata->spi_clk);
0445         dev_err(&pdev->dev, "failed to get spi-clk: %d\n", ret);
0446         goto err_put_ctlr;
0447     }
0448
0449     ret = clk_prepare_enable(mdata->spi_clk);
0450     if (ret < 0) {
0451         dev_err(&pdev->dev, "failed to enable spi_clk (%d)\n", ret);
0452         goto err_put_ctlr;
0453     }
0454
0455     pm_runtime_enable(&pdev->dev);
0456
0457     ret = devm_spi_register_controller(&pdev->dev, ctlr);
0458     if (ret) {
0459         dev_err(&pdev->dev,
0460             "failed to register slave controller(%d)\n", ret);
0461         clk_disable_unprepare(mdata->spi_clk);
0462         goto err_disable_runtime_pm;
0463     }
0464
0465     clk_disable_unprepare(mdata->spi_clk);
0466
0467     return 0;
0468
0469 err_disable_runtime_pm:
0470     pm_runtime_disable(&pdev->dev);
0471 err_put_ctlr:
0472     spi_controller_put(ctlr);
0473
0474     return ret;
0475 }
0476
0477 static int mtk_spi_slave_remove(struct platform_device *pdev)
0478 {
0479     pm_runtime_disable(&pdev->dev);
0480
0481     return 0;
0482 }
0483
0484 #ifdef CONFIG_PM_SLEEP
0485 static int mtk_spi_slave_suspend(struct device *dev)
0486 {
0487     struct spi_controller *ctlr = dev_get_drvdata(dev);
0488     struct mtk_spi_slave *mdata = spi_controller_get_devdata(ctlr);
0489     int ret;
0490
0491     ret = spi_controller_suspend(ctlr);
0492     if (ret)
0493         return ret;
0494
0495     if (!pm_runtime_suspended(dev))
0496         clk_disable_unprepare(mdata->spi_clk);
0497
0498     return ret;
0499 }
0500
0501 static int mtk_spi_slave_resume(struct device *dev)
0502 {
0503     struct spi_controller *ctlr = dev_get_drvdata(dev);
0504     struct mtk_spi_slave *mdata = spi_controller_get_devdata(ctlr);
0505     int ret;
0506
0507     if (!pm_runtime_suspended(dev)) {
0508         ret = clk_prepare_enable(mdata->spi_clk);
0509         if (ret < 0) {
0510             dev_err(dev, "failed to enable spi_clk (%d)\n", ret);
0511             return ret;
0512         }
0513     }
0514
0515     ret = spi_controller_resume(ctlr);
0516     if (ret < 0)
0517         clk_disable_unprepare(mdata->spi_clk);
0518
0519     return ret;
0520 }
0521 #endif /* CONFIG_PM_SLEEP */
0522
0523 #ifdef CONFIG_PM
0524 static int mtk_spi_slave_runtime_suspend(struct device *dev)
0525 {
0526     struct spi_controller *ctlr = dev_get_drvdata(dev);
0527     struct mtk_spi_slave *mdata = spi_controller_get_devdata(ctlr);
0528
0529     clk_disable_unprepare(mdata->spi_clk);
0530
0531     return 0;
0532 }
0533
0534 static int mtk_spi_slave_runtime_resume(struct device *dev)
0535 {
0536     struct spi_controller *ctlr = dev_get_drvdata(dev);
0537     struct mtk_spi_slave *mdata = spi_controller_get_devdata(ctlr);
0538     int ret;
0539
0540     ret = clk_prepare_enable(mdata->spi_clk);
0541     if (ret < 0) {
0542         dev_err(dev, "failed to enable spi_clk (%d)\n", ret);
0543         return ret;
0544     }
0545
0546     return 0;
0547 }
0548 #endif /* CONFIG_PM */
0549
0550 static const struct dev_pm_ops mtk_spi_slave_pm = {
0551     SET_SYSTEM_SLEEP_PM_OPS(mtk_spi_slave_suspend, mtk_spi_slave_resume)
0552     SET_RUNTIME_PM_OPS(mtk_spi_slave_runtime_suspend,
0553                mtk_spi_slave_runtime_resume, NULL)
0554 };
0555
0556 static struct platform_driver mtk_spi_slave_driver = {
0557     .driver = {
0558         .name = "mtk-spi-slave",
0559         .pm = &mtk_spi_slave_pm,
0560         .of_match_table = mtk_spi_slave_of_match,
0561     },
0562     .probe = mtk_spi_slave_probe,
0563     .remove = mtk_spi_slave_remove,
0564 };
0565
0566 module_platform_driver(mtk_spi_slave_driver);
0567
0568 MODULE_DESCRIPTION("MTK SPI Slave Controller driver");
0569 MODULE_AUTHOR("Leilk Liu <leilk.liu@mediatek.com>");
0570 MODULE_LICENSE("GPL v2");
0571 MODULE_ALIAS("platform:mtk-spi-slave");