drivers/spi/spi-sifive.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 //
0003 // Copyright 2018 SiFive, Inc.
0004 //
0005 // SiFive SPI controller driver (master mode only)
0006 //
0007 // Author: SiFive, Inc.
0008 // sifive@sifive.com
0009
0010 #include <linux/clk.h>
0011 #include <linux/module.h>
0012 #include <linux/interrupt.h>
0013 #include <linux/of.h>
0014 #include <linux/platform_device.h>
0015 #include <linux/spi/spi.h>
0016 #include <linux/io.h>
0017 #include <linux/log2.h>
0018
0019 #define SIFIVE_SPI_DRIVER_NAME           "sifive_spi"
0020
0021 #define SIFIVE_SPI_MAX_CS                32
0022 #define SIFIVE_SPI_DEFAULT_DEPTH         8
0023 #define SIFIVE_SPI_DEFAULT_MAX_BITS      8
0024
0025 /* register offsets */
0026 #define SIFIVE_SPI_REG_SCKDIV            0x00 /* Serial clock divisor */
0027 #define SIFIVE_SPI_REG_SCKMODE           0x04 /* Serial clock mode */
0028 #define SIFIVE_SPI_REG_CSID              0x10 /* Chip select ID */
0029 #define SIFIVE_SPI_REG_CSDEF             0x14 /* Chip select default */
0030 #define SIFIVE_SPI_REG_CSMODE            0x18 /* Chip select mode */
0031 #define SIFIVE_SPI_REG_DELAY0            0x28 /* Delay control 0 */
0032 #define SIFIVE_SPI_REG_DELAY1            0x2c /* Delay control 1 */
0033 #define SIFIVE_SPI_REG_FMT               0x40 /* Frame format */
0034 #define SIFIVE_SPI_REG_TXDATA            0x48 /* Tx FIFO data */
0035 #define SIFIVE_SPI_REG_RXDATA            0x4c /* Rx FIFO data */
0036 #define SIFIVE_SPI_REG_TXMARK            0x50 /* Tx FIFO watermark */
0037 #define SIFIVE_SPI_REG_RXMARK            0x54 /* Rx FIFO watermark */
0038 #define SIFIVE_SPI_REG_FCTRL             0x60 /* SPI flash interface control */
0039 #define SIFIVE_SPI_REG_FFMT              0x64 /* SPI flash instruction format */
0040 #define SIFIVE_SPI_REG_IE                0x70 /* Interrupt Enable Register */
0041 #define SIFIVE_SPI_REG_IP                0x74 /* Interrupt Pendings Register */
0042
0043 /* sckdiv bits */
0044 #define SIFIVE_SPI_SCKDIV_DIV_MASK       0xfffU
0045
0046 /* sckmode bits */
0047 #define SIFIVE_SPI_SCKMODE_PHA           BIT(0)
0048 #define SIFIVE_SPI_SCKMODE_POL           BIT(1)
0049 #define SIFIVE_SPI_SCKMODE_MODE_MASK     (SIFIVE_SPI_SCKMODE_PHA | \
0050                       SIFIVE_SPI_SCKMODE_POL)
0051
0052 /* csmode bits */
0053 #define SIFIVE_SPI_CSMODE_MODE_AUTO      0U
0054 #define SIFIVE_SPI_CSMODE_MODE_HOLD      2U
0055 #define SIFIVE_SPI_CSMODE_MODE_OFF       3U
0056
0057 /* delay0 bits */
0058 #define SIFIVE_SPI_DELAY0_CSSCK(x)       ((u32)(x))
0059 #define SIFIVE_SPI_DELAY0_CSSCK_MASK     0xffU
0060 #define SIFIVE_SPI_DELAY0_SCKCS(x)       ((u32)(x) << 16)
0061 #define SIFIVE_SPI_DELAY0_SCKCS_MASK     (0xffU << 16)
0062
0063 /* delay1 bits */
0064 #define SIFIVE_SPI_DELAY1_INTERCS(x)     ((u32)(x))
0065 #define SIFIVE_SPI_DELAY1_INTERCS_MASK   0xffU
0066 #define SIFIVE_SPI_DELAY1_INTERXFR(x)    ((u32)(x) << 16)
0067 #define SIFIVE_SPI_DELAY1_INTERXFR_MASK  (0xffU << 16)
0068
0069 /* fmt bits */
0070 #define SIFIVE_SPI_FMT_PROTO_SINGLE      0U
0071 #define SIFIVE_SPI_FMT_PROTO_DUAL        1U
0072 #define SIFIVE_SPI_FMT_PROTO_QUAD        2U
0073 #define SIFIVE_SPI_FMT_PROTO_MASK        3U
0074 #define SIFIVE_SPI_FMT_ENDIAN            BIT(2)
0075 #define SIFIVE_SPI_FMT_DIR               BIT(3)
0076 #define SIFIVE_SPI_FMT_LEN(x)            ((u32)(x) << 16)
0077 #define SIFIVE_SPI_FMT_LEN_MASK          (0xfU << 16)
0078
0079 /* txdata bits */
0080 #define SIFIVE_SPI_TXDATA_DATA_MASK      0xffU
0081 #define SIFIVE_SPI_TXDATA_FULL           BIT(31)
0082
0083 /* rxdata bits */
0084 #define SIFIVE_SPI_RXDATA_DATA_MASK      0xffU
0085 #define SIFIVE_SPI_RXDATA_EMPTY          BIT(31)
0086
0087 /* ie and ip bits */
0088 #define SIFIVE_SPI_IP_TXWM               BIT(0)
0089 #define SIFIVE_SPI_IP_RXWM               BIT(1)
0090
0091 struct sifive_spi {
0092     void __iomem      *regs;        /* virt. address of control registers */
0093     struct clk        *clk;         /* bus clock */
0094     unsigned int      fifo_depth;   /* fifo depth in words */
0095     u32               cs_inactive;  /* level of the CS pins when inactive */
0096     struct completion done;         /* wake-up from interrupt */
0097 };
0098
0099 static void sifive_spi_write(struct sifive_spi *spi, int offset, u32 value)
0100 {
0101     iowrite32(value, spi->regs + offset);
0102 }
0103
0104 static u32 sifive_spi_read(struct sifive_spi *spi, int offset)
0105 {
0106     return ioread32(spi->regs + offset);
0107 }
0108
0109 static void sifive_spi_init(struct sifive_spi *spi)
0110 {
0111     /* Watermark interrupts are disabled by default */
0112     sifive_spi_write(spi, SIFIVE_SPI_REG_IE, 0);
0113
0114     /* Default watermark FIFO threshold values */
0115     sifive_spi_write(spi, SIFIVE_SPI_REG_TXMARK, 1);
0116     sifive_spi_write(spi, SIFIVE_SPI_REG_RXMARK, 0);
0117
0118     /* Set CS/SCK Delays and Inactive Time to defaults */
0119     sifive_spi_write(spi, SIFIVE_SPI_REG_DELAY0,
0120              SIFIVE_SPI_DELAY0_CSSCK(1) |
0121              SIFIVE_SPI_DELAY0_SCKCS(1));
0122     sifive_spi_write(spi, SIFIVE_SPI_REG_DELAY1,
0123              SIFIVE_SPI_DELAY1_INTERCS(1) |
0124              SIFIVE_SPI_DELAY1_INTERXFR(0));
0125
0126     /* Exit specialized memory-mapped SPI flash mode */
0127     sifive_spi_write(spi, SIFIVE_SPI_REG_FCTRL, 0);
0128 }
0129
0130 static int
0131 sifive_spi_prepare_message(struct spi_master *master, struct spi_message *msg)
0132 {
0133     struct sifive_spi *spi = spi_master_get_devdata(master);
0134     struct spi_device *device = msg->spi;
0135
0136     /* Update the chip select polarity */
0137     if (device->mode & SPI_CS_HIGH)
0138         spi->cs_inactive &= ~BIT(device->chip_select);
0139     else
0140         spi->cs_inactive |= BIT(device->chip_select);
0141     sifive_spi_write(spi, SIFIVE_SPI_REG_CSDEF, spi->cs_inactive);
0142
0143     /* Select the correct device */
0144     sifive_spi_write(spi, SIFIVE_SPI_REG_CSID, device->chip_select);
0145
0146     /* Set clock mode */
0147     sifive_spi_write(spi, SIFIVE_SPI_REG_SCKMODE,
0148              device->mode & SIFIVE_SPI_SCKMODE_MODE_MASK);
0149
0150     return 0;
0151 }
0152
0153 static void sifive_spi_set_cs(struct spi_device *device, bool is_high)
0154 {
0155     struct sifive_spi *spi = spi_master_get_devdata(device->master);
0156
0157     /* Reverse polarity is handled by SCMR/CPOL. Not inverted CS. */
0158     if (device->mode & SPI_CS_HIGH)
0159         is_high = !is_high;
0160
0161     sifive_spi_write(spi, SIFIVE_SPI_REG_CSMODE, is_high ?
0162              SIFIVE_SPI_CSMODE_MODE_AUTO :
0163              SIFIVE_SPI_CSMODE_MODE_HOLD);
0164 }
0165
0166 static int
0167 sifive_spi_prep_transfer(struct sifive_spi *spi, struct spi_device *device,
0168              struct spi_transfer *t)
0169 {
0170     u32 cr;
0171     unsigned int mode;
0172
0173     /* Calculate and program the clock rate */
0174     cr = DIV_ROUND_UP(clk_get_rate(spi->clk) >> 1, t->speed_hz) - 1;
0175     cr &= SIFIVE_SPI_SCKDIV_DIV_MASK;
0176     sifive_spi_write(spi, SIFIVE_SPI_REG_SCKDIV, cr);
0177
0178     mode = max_t(unsigned int, t->rx_nbits, t->tx_nbits);
0179
0180     /* Set frame format */
0181     cr = SIFIVE_SPI_FMT_LEN(t->bits_per_word);
0182     switch (mode) {
0183     case SPI_NBITS_QUAD:
0184         cr |= SIFIVE_SPI_FMT_PROTO_QUAD;
0185         break;
0186     case SPI_NBITS_DUAL:
0187         cr |= SIFIVE_SPI_FMT_PROTO_DUAL;
0188         break;
0189     default:
0190         cr |= SIFIVE_SPI_FMT_PROTO_SINGLE;
0191         break;
0192     }
0193     if (device->mode & SPI_LSB_FIRST)
0194         cr |= SIFIVE_SPI_FMT_ENDIAN;
0195     if (!t->rx_buf)
0196         cr |= SIFIVE_SPI_FMT_DIR;
0197     sifive_spi_write(spi, SIFIVE_SPI_REG_FMT, cr);
0198
0199     /* We will want to poll if the time we need to wait is
0200      * less than the context switching time.
0201      * Let's call that threshold 5us. The operation will take:
0202      *    (8/mode) * fifo_depth / hz <= 5 * 10^-6
0203      *    1600000 * fifo_depth <= hz * mode
0204      */
0205     return 1600000 * spi->fifo_depth <= t->speed_hz * mode;
0206 }
0207
0208 static irqreturn_t sifive_spi_irq(int irq, void *dev_id)
0209 {
0210     struct sifive_spi *spi = dev_id;
0211     u32 ip = sifive_spi_read(spi, SIFIVE_SPI_REG_IP);
0212
0213     if (ip & (SIFIVE_SPI_IP_TXWM | SIFIVE_SPI_IP_RXWM)) {
0214         /* Disable interrupts until next transfer */
0215         sifive_spi_write(spi, SIFIVE_SPI_REG_IE, 0);
0216         complete(&spi->done);
0217         return IRQ_HANDLED;
0218     }
0219
0220     return IRQ_NONE;
0221 }
0222
0223 static void sifive_spi_wait(struct sifive_spi *spi, u32 bit, int poll)
0224 {
0225     if (poll) {
0226         u32 cr;
0227
0228         do {
0229             cr = sifive_spi_read(spi, SIFIVE_SPI_REG_IP);
0230         } while (!(cr & bit));
0231     } else {
0232         reinit_completion(&spi->done);
0233         sifive_spi_write(spi, SIFIVE_SPI_REG_IE, bit);
0234         wait_for_completion(&spi->done);
0235     }
0236 }
0237
0238 static void sifive_spi_tx(struct sifive_spi *spi, const u8 *tx_ptr)
0239 {
0240     WARN_ON_ONCE((sifive_spi_read(spi, SIFIVE_SPI_REG_TXDATA)
0241                 & SIFIVE_SPI_TXDATA_FULL) != 0);
0242     sifive_spi_write(spi, SIFIVE_SPI_REG_TXDATA,
0243              *tx_ptr & SIFIVE_SPI_TXDATA_DATA_MASK);
0244 }
0245
0246 static void sifive_spi_rx(struct sifive_spi *spi, u8 *rx_ptr)
0247 {
0248     u32 data = sifive_spi_read(spi, SIFIVE_SPI_REG_RXDATA);
0249
0250     WARN_ON_ONCE((data & SIFIVE_SPI_RXDATA_EMPTY) != 0);
0251     *rx_ptr = data & SIFIVE_SPI_RXDATA_DATA_MASK;
0252 }
0253
0254 static int
0255 sifive_spi_transfer_one(struct spi_master *master, struct spi_device *device,
0256             struct spi_transfer *t)
0257 {
0258     struct sifive_spi *spi = spi_master_get_devdata(master);
0259     int poll = sifive_spi_prep_transfer(spi, device, t);
0260     const u8 *tx_ptr = t->tx_buf;
0261     u8 *rx_ptr = t->rx_buf;
0262     unsigned int remaining_words = t->len;
0263
0264     while (remaining_words) {
0265         unsigned int n_words = min(remaining_words, spi->fifo_depth);
0266         unsigned int i;
0267
0268         /* Enqueue n_words for transmission */
0269         for (i = 0; i < n_words; i++)
0270             sifive_spi_tx(spi, tx_ptr++);
0271
0272         if (rx_ptr) {
0273             /* Wait for transmission + reception to complete */
0274             sifive_spi_write(spi, SIFIVE_SPI_REG_RXMARK,
0275                      n_words - 1);
0276             sifive_spi_wait(spi, SIFIVE_SPI_IP_RXWM, poll);
0277
0278             /* Read out all the data from the RX FIFO */
0279             for (i = 0; i < n_words; i++)
0280                 sifive_spi_rx(spi, rx_ptr++);
0281         } else {
0282             /* Wait for transmission to complete */
0283             sifive_spi_wait(spi, SIFIVE_SPI_IP_TXWM, poll);
0284         }
0285
0286         remaining_words -= n_words;
0287     }
0288
0289     return 0;
0290 }
0291
0292 static int sifive_spi_probe(struct platform_device *pdev)
0293 {
0294     struct sifive_spi *spi;
0295     int ret, irq, num_cs;
0296     u32 cs_bits, max_bits_per_word;
0297     struct spi_master *master;
0298
0299     master = spi_alloc_master(&pdev->dev, sizeof(struct sifive_spi));
0300     if (!master) {
0301         dev_err(&pdev->dev, "out of memory\n");
0302         return -ENOMEM;
0303     }
0304
0305     spi = spi_master_get_devdata(master);
0306     init_completion(&spi->done);
0307     platform_set_drvdata(pdev, master);
0308
0309     spi->regs = devm_platform_ioremap_resource(pdev, 0);
0310     if (IS_ERR(spi->regs)) {
0311         ret = PTR_ERR(spi->regs);
0312         goto put_master;
0313     }
0314
0315     spi->clk = devm_clk_get(&pdev->dev, NULL);
0316     if (IS_ERR(spi->clk)) {
0317         dev_err(&pdev->dev, "Unable to find bus clock\n");
0318         ret = PTR_ERR(spi->clk);
0319         goto put_master;
0320     }
0321
0322     irq = platform_get_irq(pdev, 0);
0323     if (irq < 0) {
0324         ret = irq;
0325         goto put_master;
0326     }
0327
0328     /* Optional parameters */
0329     ret =
0330       of_property_read_u32(pdev->dev.of_node, "sifive,fifo-depth",
0331                    &spi->fifo_depth);
0332     if (ret < 0)
0333         spi->fifo_depth = SIFIVE_SPI_DEFAULT_DEPTH;
0334
0335     ret =
0336       of_property_read_u32(pdev->dev.of_node, "sifive,max-bits-per-word",
0337                    &max_bits_per_word);
0338
0339     if (!ret && max_bits_per_word < 8) {
0340         dev_err(&pdev->dev, "Only 8bit SPI words supported by the driver\n");
0341         ret = -EINVAL;
0342         goto put_master;
0343     }
0344
0345     /* Spin up the bus clock before hitting registers */
0346     ret = clk_prepare_enable(spi->clk);
0347     if (ret) {
0348         dev_err(&pdev->dev, "Unable to enable bus clock\n");
0349         goto put_master;
0350     }
0351
0352     /* probe the number of CS lines */
0353     spi->cs_inactive = sifive_spi_read(spi, SIFIVE_SPI_REG_CSDEF);
0354     sifive_spi_write(spi, SIFIVE_SPI_REG_CSDEF, 0xffffffffU);
0355     cs_bits = sifive_spi_read(spi, SIFIVE_SPI_REG_CSDEF);
0356     sifive_spi_write(spi, SIFIVE_SPI_REG_CSDEF, spi->cs_inactive);
0357     if (!cs_bits) {
0358         dev_err(&pdev->dev, "Could not auto probe CS lines\n");
0359         ret = -EINVAL;
0360         goto disable_clk;
0361     }
0362
0363     num_cs = ilog2(cs_bits) + 1;
0364     if (num_cs > SIFIVE_SPI_MAX_CS) {
0365         dev_err(&pdev->dev, "Invalid number of spi slaves\n");
0366         ret = -EINVAL;
0367         goto disable_clk;
0368     }
0369
0370     /* Define our master */
0371     master->dev.of_node = pdev->dev.of_node;
0372     master->bus_num = pdev->id;
0373     master->num_chipselect = num_cs;
0374     master->mode_bits = SPI_CPHA | SPI_CPOL
0375               | SPI_CS_HIGH | SPI_LSB_FIRST
0376               | SPI_TX_DUAL | SPI_TX_QUAD
0377               | SPI_RX_DUAL | SPI_RX_QUAD;
0378     /* TODO: add driver support for bits_per_word < 8
0379      * we need to "left-align" the bits (unless SPI_LSB_FIRST)
0380      */
0381     master->bits_per_word_mask = SPI_BPW_MASK(8);
0382     master->flags = SPI_CONTROLLER_MUST_TX | SPI_MASTER_GPIO_SS;
0383     master->prepare_message = sifive_spi_prepare_message;
0384     master->set_cs = sifive_spi_set_cs;
0385     master->transfer_one = sifive_spi_transfer_one;
0386
0387     pdev->dev.dma_mask = NULL;
0388     /* Configure the SPI master hardware */
0389     sifive_spi_init(spi);
0390
0391     /* Register for SPI Interrupt */
0392     ret = devm_request_irq(&pdev->dev, irq, sifive_spi_irq, 0,
0393                    dev_name(&pdev->dev), spi);
0394     if (ret) {
0395         dev_err(&pdev->dev, "Unable to bind to interrupt\n");
0396         goto disable_clk;
0397     }
0398
0399     dev_info(&pdev->dev, "mapped; irq=%d, cs=%d\n",
0400          irq, master->num_chipselect);
0401
0402     ret = devm_spi_register_master(&pdev->dev, master);
0403     if (ret < 0) {
0404         dev_err(&pdev->dev, "spi_register_master failed\n");
0405         goto disable_clk;
0406     }
0407
0408     return 0;
0409
0410 disable_clk:
0411     clk_disable_unprepare(spi->clk);
0412 put_master:
0413     spi_master_put(master);
0414
0415     return ret;
0416 }
0417
0418 static int sifive_spi_remove(struct platform_device *pdev)
0419 {
0420     struct spi_master *master = platform_get_drvdata(pdev);
0421     struct sifive_spi *spi = spi_master_get_devdata(master);
0422
0423     /* Disable all the interrupts just in case */
0424     sifive_spi_write(spi, SIFIVE_SPI_REG_IE, 0);
0425     clk_disable_unprepare(spi->clk);
0426
0427     return 0;
0428 }
0429
0430 static int sifive_spi_suspend(struct device *dev)
0431 {
0432     struct spi_master *master = dev_get_drvdata(dev);
0433     struct sifive_spi *spi = spi_master_get_devdata(master);
0434     int ret;
0435
0436     ret = spi_master_suspend(master);
0437     if (ret)
0438         return ret;
0439
0440     /* Disable all the interrupts just in case */
0441     sifive_spi_write(spi, SIFIVE_SPI_REG_IE, 0);
0442
0443     clk_disable_unprepare(spi->clk);
0444
0445     return ret;
0446 }
0447
0448 static int sifive_spi_resume(struct device *dev)
0449 {
0450     struct spi_master *master = dev_get_drvdata(dev);
0451     struct sifive_spi *spi = spi_master_get_devdata(master);
0452     int ret;
0453
0454     ret = clk_prepare_enable(spi->clk);
0455     if (ret)
0456         return ret;
0457     ret = spi_master_resume(master);
0458     if (ret)
0459         clk_disable_unprepare(spi->clk);
0460
0461     return ret;
0462 }
0463
0464 static DEFINE_SIMPLE_DEV_PM_OPS(sifive_spi_pm_ops,
0465                 sifive_spi_suspend, sifive_spi_resume);
0466
0467
0468 static const struct of_device_id sifive_spi_of_match[] = {
0469     { .compatible = "sifive,spi0", },
0470     {}
0471 };
0472 MODULE_DEVICE_TABLE(of, sifive_spi_of_match);
0473
0474 static struct platform_driver sifive_spi_driver = {
0475     .probe = sifive_spi_probe,
0476     .remove = sifive_spi_remove,
0477     .driver = {
0478         .name = SIFIVE_SPI_DRIVER_NAME,
0479         .pm = &sifive_spi_pm_ops,
0480         .of_match_table = sifive_spi_of_match,
0481     },
0482 };
0483 module_platform_driver(sifive_spi_driver);
0484
0485 MODULE_AUTHOR("SiFive, Inc. <sifive@sifive.com>");
0486 MODULE_DESCRIPTION("SiFive SPI driver");
0487 MODULE_LICENSE("GPL");