drivers/spi/spi-sh.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * SH SPI bus driver
0004  *
0005  * Copyright (C) 2011  Renesas Solutions Corp.
0006  *
0007  * Based on pxa2xx_spi.c:
0008  * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs
0009  */
0010
0011 #include <linux/module.h>
0012 #include <linux/kernel.h>
0013 #include <linux/sched.h>
0014 #include <linux/errno.h>
0015 #include <linux/timer.h>
0016 #include <linux/delay.h>
0017 #include <linux/list.h>
0018 #include <linux/workqueue.h>
0019 #include <linux/interrupt.h>
0020 #include <linux/platform_device.h>
0021 #include <linux/io.h>
0022 #include <linux/spi/spi.h>
0023
0024 #define SPI_SH_TBR      0x00
0025 #define SPI_SH_RBR      0x00
0026 #define SPI_SH_CR1      0x08
0027 #define SPI_SH_CR2      0x10
0028 #define SPI_SH_CR3      0x18
0029 #define SPI_SH_CR4      0x20
0030 #define SPI_SH_CR5      0x28
0031
0032 /* CR1 */
0033 #define SPI_SH_TBE      0x80
0034 #define SPI_SH_TBF      0x40
0035 #define SPI_SH_RBE      0x20
0036 #define SPI_SH_RBF      0x10
0037 #define SPI_SH_PFONRD       0x08
0038 #define SPI_SH_SSDB     0x04
0039 #define SPI_SH_SSD      0x02
0040 #define SPI_SH_SSA      0x01
0041
0042 /* CR2 */
0043 #define SPI_SH_RSTF     0x80
0044 #define SPI_SH_LOOPBK       0x40
0045 #define SPI_SH_CPOL     0x20
0046 #define SPI_SH_CPHA     0x10
0047 #define SPI_SH_L1M0     0x08
0048
0049 /* CR3 */
0050 #define SPI_SH_MAX_BYTE     0xFF
0051
0052 /* CR4 */
0053 #define SPI_SH_TBEI     0x80
0054 #define SPI_SH_TBFI     0x40
0055 #define SPI_SH_RBEI     0x20
0056 #define SPI_SH_RBFI     0x10
0057 #define SPI_SH_WPABRT       0x04
0058 #define SPI_SH_SSS      0x01
0059
0060 /* CR8 */
0061 #define SPI_SH_P1L0     0x80
0062 #define SPI_SH_PP1L0        0x40
0063 #define SPI_SH_MUXI     0x20
0064 #define SPI_SH_MUXIRQ       0x10
0065
0066 #define SPI_SH_FIFO_SIZE    32
0067 #define SPI_SH_SEND_TIMEOUT (3 * HZ)
0068 #define SPI_SH_RECEIVE_TIMEOUT  (HZ >> 3)
0069
0070 #undef DEBUG
0071
0072 struct spi_sh_data {
0073     void __iomem *addr;
0074     int irq;
0075     struct spi_master *master;
0076     unsigned long cr1;
0077     wait_queue_head_t wait;
0078     int width;
0079 };
0080
0081 static void spi_sh_write(struct spi_sh_data *ss, unsigned long data,
0082                  unsigned long offset)
0083 {
0084     if (ss->width == 8)
0085         iowrite8(data, ss->addr + (offset >> 2));
0086     else if (ss->width == 32)
0087         iowrite32(data, ss->addr + offset);
0088 }
0089
0090 static unsigned long spi_sh_read(struct spi_sh_data *ss, unsigned long offset)
0091 {
0092     if (ss->width == 8)
0093         return ioread8(ss->addr + (offset >> 2));
0094     else if (ss->width == 32)
0095         return ioread32(ss->addr + offset);
0096     else
0097         return 0;
0098 }
0099
0100 static void spi_sh_set_bit(struct spi_sh_data *ss, unsigned long val,
0101                 unsigned long offset)
0102 {
0103     unsigned long tmp;
0104
0105     tmp = spi_sh_read(ss, offset);
0106     tmp |= val;
0107     spi_sh_write(ss, tmp, offset);
0108 }
0109
0110 static void spi_sh_clear_bit(struct spi_sh_data *ss, unsigned long val,
0111                 unsigned long offset)
0112 {
0113     unsigned long tmp;
0114
0115     tmp = spi_sh_read(ss, offset);
0116     tmp &= ~val;
0117     spi_sh_write(ss, tmp, offset);
0118 }
0119
0120 static void clear_fifo(struct spi_sh_data *ss)
0121 {
0122     spi_sh_set_bit(ss, SPI_SH_RSTF, SPI_SH_CR2);
0123     spi_sh_clear_bit(ss, SPI_SH_RSTF, SPI_SH_CR2);
0124 }
0125
0126 static int spi_sh_wait_receive_buffer(struct spi_sh_data *ss)
0127 {
0128     int timeout = 100000;
0129
0130     while (spi_sh_read(ss, SPI_SH_CR1) & SPI_SH_RBE) {
0131         udelay(10);
0132         if (timeout-- < 0)
0133             return -ETIMEDOUT;
0134     }
0135     return 0;
0136 }
0137
0138 static int spi_sh_wait_write_buffer_empty(struct spi_sh_data *ss)
0139 {
0140     int timeout = 100000;
0141
0142     while (!(spi_sh_read(ss, SPI_SH_CR1) & SPI_SH_TBE)) {
0143         udelay(10);
0144         if (timeout-- < 0)
0145             return -ETIMEDOUT;
0146     }
0147     return 0;
0148 }
0149
0150 static int spi_sh_send(struct spi_sh_data *ss, struct spi_message *mesg,
0151             struct spi_transfer *t)
0152 {
0153     int i, retval = 0;
0154     int remain = t->len;
0155     int cur_len;
0156     unsigned char *data;
0157     long ret;
0158
0159     if (t->len)
0160         spi_sh_set_bit(ss, SPI_SH_SSA, SPI_SH_CR1);
0161
0162     data = (unsigned char *)t->tx_buf;
0163     while (remain > 0) {
0164         cur_len = min(SPI_SH_FIFO_SIZE, remain);
0165         for (i = 0; i < cur_len &&
0166                 !(spi_sh_read(ss, SPI_SH_CR4) &
0167                             SPI_SH_WPABRT) &&
0168                 !(spi_sh_read(ss, SPI_SH_CR1) & SPI_SH_TBF);
0169                 i++)
0170             spi_sh_write(ss, (unsigned long)data[i], SPI_SH_TBR);
0171
0172         if (spi_sh_read(ss, SPI_SH_CR4) & SPI_SH_WPABRT) {
0173             /* Abort SPI operation */
0174             spi_sh_set_bit(ss, SPI_SH_WPABRT, SPI_SH_CR4);
0175             retval = -EIO;
0176             break;
0177         }
0178
0179         cur_len = i;
0180
0181         remain -= cur_len;
0182         data += cur_len;
0183
0184         if (remain > 0) {
0185             ss->cr1 &= ~SPI_SH_TBE;
0186             spi_sh_set_bit(ss, SPI_SH_TBE, SPI_SH_CR4);
0187             ret = wait_event_interruptible_timeout(ss->wait,
0188                          ss->cr1 & SPI_SH_TBE,
0189                          SPI_SH_SEND_TIMEOUT);
0190             if (ret == 0 && !(ss->cr1 & SPI_SH_TBE)) {
0191                 printk(KERN_ERR "%s: timeout\n", __func__);
0192                 return -ETIMEDOUT;
0193             }
0194         }
0195     }
0196
0197     if (list_is_last(&t->transfer_list, &mesg->transfers)) {
0198         spi_sh_clear_bit(ss, SPI_SH_SSD | SPI_SH_SSDB, SPI_SH_CR1);
0199         spi_sh_set_bit(ss, SPI_SH_SSA, SPI_SH_CR1);
0200
0201         ss->cr1 &= ~SPI_SH_TBE;
0202         spi_sh_set_bit(ss, SPI_SH_TBE, SPI_SH_CR4);
0203         ret = wait_event_interruptible_timeout(ss->wait,
0204                      ss->cr1 & SPI_SH_TBE,
0205                      SPI_SH_SEND_TIMEOUT);
0206         if (ret == 0 && (ss->cr1 & SPI_SH_TBE)) {
0207             printk(KERN_ERR "%s: timeout\n", __func__);
0208             return -ETIMEDOUT;
0209         }
0210     }
0211
0212     return retval;
0213 }
0214
0215 static int spi_sh_receive(struct spi_sh_data *ss, struct spi_message *mesg,
0216               struct spi_transfer *t)
0217 {
0218     int i;
0219     int remain = t->len;
0220     int cur_len;
0221     unsigned char *data;
0222     long ret;
0223
0224     if (t->len > SPI_SH_MAX_BYTE)
0225         spi_sh_write(ss, SPI_SH_MAX_BYTE, SPI_SH_CR3);
0226     else
0227         spi_sh_write(ss, t->len, SPI_SH_CR3);
0228
0229     spi_sh_clear_bit(ss, SPI_SH_SSD | SPI_SH_SSDB, SPI_SH_CR1);
0230     spi_sh_set_bit(ss, SPI_SH_SSA, SPI_SH_CR1);
0231
0232     spi_sh_wait_write_buffer_empty(ss);
0233
0234     data = (unsigned char *)t->rx_buf;
0235     while (remain > 0) {
0236         if (remain >= SPI_SH_FIFO_SIZE) {
0237             ss->cr1 &= ~SPI_SH_RBF;
0238             spi_sh_set_bit(ss, SPI_SH_RBF, SPI_SH_CR4);
0239             ret = wait_event_interruptible_timeout(ss->wait,
0240                          ss->cr1 & SPI_SH_RBF,
0241                          SPI_SH_RECEIVE_TIMEOUT);
0242             if (ret == 0 &&
0243                 spi_sh_read(ss, SPI_SH_CR1) & SPI_SH_RBE) {
0244                 printk(KERN_ERR "%s: timeout\n", __func__);
0245                 return -ETIMEDOUT;
0246             }
0247         }
0248
0249         cur_len = min(SPI_SH_FIFO_SIZE, remain);
0250         for (i = 0; i < cur_len; i++) {
0251             if (spi_sh_wait_receive_buffer(ss))
0252                 break;
0253             data[i] = (unsigned char)spi_sh_read(ss, SPI_SH_RBR);
0254         }
0255
0256         remain -= cur_len;
0257         data += cur_len;
0258     }
0259
0260     /* deassert CS when SPI is receiving. */
0261     if (t->len > SPI_SH_MAX_BYTE) {
0262         clear_fifo(ss);
0263         spi_sh_write(ss, 1, SPI_SH_CR3);
0264     } else {
0265         spi_sh_write(ss, 0, SPI_SH_CR3);
0266     }
0267
0268     return 0;
0269 }
0270
0271 static int spi_sh_transfer_one_message(struct spi_controller *ctlr,
0272                     struct spi_message *mesg)
0273 {
0274     struct spi_sh_data *ss = spi_controller_get_devdata(ctlr);
0275     struct spi_transfer *t;
0276     int ret;
0277
0278     pr_debug("%s: enter\n", __func__);
0279
0280     spi_sh_clear_bit(ss, SPI_SH_SSA, SPI_SH_CR1);
0281
0282     list_for_each_entry(t, &mesg->transfers, transfer_list) {
0283         pr_debug("tx_buf = %p, rx_buf = %p\n",
0284              t->tx_buf, t->rx_buf);
0285         pr_debug("len = %d, delay.value = %d\n",
0286              t->len, t->delay.value);
0287
0288         if (t->tx_buf) {
0289             ret = spi_sh_send(ss, mesg, t);
0290             if (ret < 0)
0291                 goto error;
0292         }
0293         if (t->rx_buf) {
0294             ret = spi_sh_receive(ss, mesg, t);
0295             if (ret < 0)
0296                 goto error;
0297         }
0298         mesg->actual_length += t->len;
0299     }
0300
0301     mesg->status = 0;
0302     spi_finalize_current_message(ctlr);
0303
0304     clear_fifo(ss);
0305     spi_sh_set_bit(ss, SPI_SH_SSD, SPI_SH_CR1);
0306     udelay(100);
0307
0308     spi_sh_clear_bit(ss, SPI_SH_SSA | SPI_SH_SSDB | SPI_SH_SSD,
0309              SPI_SH_CR1);
0310
0311     clear_fifo(ss);
0312
0313     return 0;
0314
0315  error:
0316     mesg->status = ret;
0317     spi_finalize_current_message(ctlr);
0318     if (mesg->complete)
0319         mesg->complete(mesg->context);
0320
0321     spi_sh_clear_bit(ss, SPI_SH_SSA | SPI_SH_SSDB | SPI_SH_SSD,
0322              SPI_SH_CR1);
0323     clear_fifo(ss);
0324
0325     return ret;
0326 }
0327
0328 static int spi_sh_setup(struct spi_device *spi)
0329 {
0330     struct spi_sh_data *ss = spi_master_get_devdata(spi->master);
0331
0332     pr_debug("%s: enter\n", __func__);
0333
0334     spi_sh_write(ss, 0xfe, SPI_SH_CR1); /* SPI sycle stop */
0335     spi_sh_write(ss, 0x00, SPI_SH_CR1); /* CR1 init */
0336     spi_sh_write(ss, 0x00, SPI_SH_CR3); /* CR3 init */
0337
0338     clear_fifo(ss);
0339
0340     /* 1/8 clock */
0341     spi_sh_write(ss, spi_sh_read(ss, SPI_SH_CR2) | 0x07, SPI_SH_CR2);
0342     udelay(10);
0343
0344     return 0;
0345 }
0346
0347 static void spi_sh_cleanup(struct spi_device *spi)
0348 {
0349     struct spi_sh_data *ss = spi_master_get_devdata(spi->master);
0350
0351     pr_debug("%s: enter\n", __func__);
0352
0353     spi_sh_clear_bit(ss, SPI_SH_SSA | SPI_SH_SSDB | SPI_SH_SSD,
0354              SPI_SH_CR1);
0355 }
0356
0357 static irqreturn_t spi_sh_irq(int irq, void *_ss)
0358 {
0359     struct spi_sh_data *ss = (struct spi_sh_data *)_ss;
0360     unsigned long cr1;
0361
0362     cr1 = spi_sh_read(ss, SPI_SH_CR1);
0363     if (cr1 & SPI_SH_TBE)
0364         ss->cr1 |= SPI_SH_TBE;
0365     if (cr1 & SPI_SH_TBF)
0366         ss->cr1 |= SPI_SH_TBF;
0367     if (cr1 & SPI_SH_RBE)
0368         ss->cr1 |= SPI_SH_RBE;
0369     if (cr1 & SPI_SH_RBF)
0370         ss->cr1 |= SPI_SH_RBF;
0371
0372     if (ss->cr1) {
0373         spi_sh_clear_bit(ss, ss->cr1, SPI_SH_CR4);
0374         wake_up(&ss->wait);
0375     }
0376
0377     return IRQ_HANDLED;
0378 }
0379
0380 static int spi_sh_remove(struct platform_device *pdev)
0381 {
0382     struct spi_sh_data *ss = platform_get_drvdata(pdev);
0383
0384     spi_unregister_master(ss->master);
0385     free_irq(ss->irq, ss);
0386
0387     return 0;
0388 }
0389
0390 static int spi_sh_probe(struct platform_device *pdev)
0391 {
0392     struct resource *res;
0393     struct spi_master *master;
0394     struct spi_sh_data *ss;
0395     int ret, irq;
0396
0397     /* get base addr */
0398     res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
0399     if (unlikely(res == NULL)) {
0400         dev_err(&pdev->dev, "invalid resource\n");
0401         return -EINVAL;
0402     }
0403
0404     irq = platform_get_irq(pdev, 0);
0405     if (irq < 0)
0406         return irq;
0407
0408     master = devm_spi_alloc_master(&pdev->dev, sizeof(struct spi_sh_data));
0409     if (master == NULL) {
0410         dev_err(&pdev->dev, "spi_alloc_master error.\n");
0411         return -ENOMEM;
0412     }
0413
0414     ss = spi_master_get_devdata(master);
0415     platform_set_drvdata(pdev, ss);
0416
0417     switch (res->flags & IORESOURCE_MEM_TYPE_MASK) {
0418     case IORESOURCE_MEM_8BIT:
0419         ss->width = 8;
0420         break;
0421     case IORESOURCE_MEM_32BIT:
0422         ss->width = 32;
0423         break;
0424     default:
0425         dev_err(&pdev->dev, "No support width\n");
0426         return -ENODEV;
0427     }
0428     ss->irq = irq;
0429     ss->master = master;
0430     ss->addr = devm_ioremap(&pdev->dev, res->start, resource_size(res));
0431     if (ss->addr == NULL) {
0432         dev_err(&pdev->dev, "ioremap error.\n");
0433         return -ENOMEM;
0434     }
0435     init_waitqueue_head(&ss->wait);
0436
0437     ret = request_irq(irq, spi_sh_irq, 0, "spi_sh", ss);
0438     if (ret < 0) {
0439         dev_err(&pdev->dev, "request_irq error\n");
0440         return ret;
0441     }
0442
0443     master->num_chipselect = 2;
0444     master->bus_num = pdev->id;
0445     master->setup = spi_sh_setup;
0446     master->transfer_one_message = spi_sh_transfer_one_message;
0447     master->cleanup = spi_sh_cleanup;
0448
0449     ret = spi_register_master(master);
0450     if (ret < 0) {
0451         printk(KERN_ERR "spi_register_master error.\n");
0452         goto error3;
0453     }
0454
0455     return 0;
0456
0457  error3:
0458     free_irq(irq, ss);
0459     return ret;
0460 }
0461
0462 static struct platform_driver spi_sh_driver = {
0463     .probe = spi_sh_probe,
0464     .remove = spi_sh_remove,
0465     .driver = {
0466         .name = "sh_spi",
0467     },
0468 };
0469 module_platform_driver(spi_sh_driver);
0470
0471 MODULE_DESCRIPTION("SH SPI bus driver");
0472 MODULE_LICENSE("GPL v2");
0473 MODULE_AUTHOR("Yoshihiro Shimoda");
0474 MODULE_ALIAS("platform:sh_spi");