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0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * SuperH MSIOF SPI Controller Interface
0004  *
0005  * Copyright (c) 2009 Magnus Damm
0006  * Copyright (C) 2014 Renesas Electronics Corporation
0007  * Copyright (C) 2014-2017 Glider bvba
0008  */
0009 
0010 #include <linux/bitmap.h>
0011 #include <linux/clk.h>
0012 #include <linux/completion.h>
0013 #include <linux/delay.h>
0014 #include <linux/dma-mapping.h>
0015 #include <linux/dmaengine.h>
0016 #include <linux/err.h>
0017 #include <linux/interrupt.h>
0018 #include <linux/io.h>
0019 #include <linux/iopoll.h>
0020 #include <linux/kernel.h>
0021 #include <linux/module.h>
0022 #include <linux/of.h>
0023 #include <linux/of_device.h>
0024 #include <linux/platform_device.h>
0025 #include <linux/pm_runtime.h>
0026 #include <linux/sh_dma.h>
0027 
0028 #include <linux/spi/sh_msiof.h>
0029 #include <linux/spi/spi.h>
0030 
0031 #include <asm/unaligned.h>
0032 
0033 struct sh_msiof_chipdata {
0034     u32 bits_per_word_mask;
0035     u16 tx_fifo_size;
0036     u16 rx_fifo_size;
0037     u16 ctlr_flags;
0038     u16 min_div_pow;
0039 };
0040 
0041 struct sh_msiof_spi_priv {
0042     struct spi_controller *ctlr;
0043     void __iomem *mapbase;
0044     struct clk *clk;
0045     struct platform_device *pdev;
0046     struct sh_msiof_spi_info *info;
0047     struct completion done;
0048     struct completion done_txdma;
0049     unsigned int tx_fifo_size;
0050     unsigned int rx_fifo_size;
0051     unsigned int min_div_pow;
0052     void *tx_dma_page;
0053     void *rx_dma_page;
0054     dma_addr_t tx_dma_addr;
0055     dma_addr_t rx_dma_addr;
0056     bool native_cs_inited;
0057     bool native_cs_high;
0058     bool slave_aborted;
0059 };
0060 
0061 #define MAX_SS  3   /* Maximum number of native chip selects */
0062 
0063 #define SITMDR1 0x00    /* Transmit Mode Register 1 */
0064 #define SITMDR2 0x04    /* Transmit Mode Register 2 */
0065 #define SITMDR3 0x08    /* Transmit Mode Register 3 */
0066 #define SIRMDR1 0x10    /* Receive Mode Register 1 */
0067 #define SIRMDR2 0x14    /* Receive Mode Register 2 */
0068 #define SIRMDR3 0x18    /* Receive Mode Register 3 */
0069 #define SITSCR  0x20    /* Transmit Clock Select Register */
0070 #define SIRSCR  0x22    /* Receive Clock Select Register (SH, A1, APE6) */
0071 #define SICTR   0x28    /* Control Register */
0072 #define SIFCTR  0x30    /* FIFO Control Register */
0073 #define SISTR   0x40    /* Status Register */
0074 #define SIIER   0x44    /* Interrupt Enable Register */
0075 #define SITDR1  0x48    /* Transmit Control Data Register 1 (SH, A1) */
0076 #define SITDR2  0x4c    /* Transmit Control Data Register 2 (SH, A1) */
0077 #define SITFDR  0x50    /* Transmit FIFO Data Register */
0078 #define SIRDR1  0x58    /* Receive Control Data Register 1 (SH, A1) */
0079 #define SIRDR2  0x5c    /* Receive Control Data Register 2 (SH, A1) */
0080 #define SIRFDR  0x60    /* Receive FIFO Data Register */
0081 
0082 /* SITMDR1 and SIRMDR1 */
0083 #define SIMDR1_TRMD     BIT(31)     /* Transfer Mode (1 = Master mode) */
0084 #define SIMDR1_SYNCMD_MASK  GENMASK(29, 28) /* SYNC Mode */
0085 #define SIMDR1_SYNCMD_SPI   (2 << 28)   /*   Level mode/SPI */
0086 #define SIMDR1_SYNCMD_LR    (3 << 28)   /*   L/R mode */
0087 #define SIMDR1_SYNCAC_SHIFT 25      /* Sync Polarity (1 = Active-low) */
0088 #define SIMDR1_BITLSB_SHIFT 24      /* MSB/LSB First (1 = LSB first) */
0089 #define SIMDR1_DTDL_SHIFT   20      /* Data Pin Bit Delay for MSIOF_SYNC */
0090 #define SIMDR1_SYNCDL_SHIFT 16      /* Frame Sync Signal Timing Delay */
0091 #define SIMDR1_FLD_MASK     GENMASK(3, 2)   /* Frame Sync Signal Interval (0-3) */
0092 #define SIMDR1_FLD_SHIFT    2
0093 #define SIMDR1_XXSTP        BIT(0)      /* Transmission/Reception Stop on FIFO */
0094 /* SITMDR1 */
0095 #define SITMDR1_PCON        BIT(30)     /* Transfer Signal Connection */
0096 #define SITMDR1_SYNCCH_MASK GENMASK(27, 26) /* Sync Signal Channel Select */
0097 #define SITMDR1_SYNCCH_SHIFT    26      /* 0=MSIOF_SYNC, 1=MSIOF_SS1, 2=MSIOF_SS2 */
0098 
0099 /* SITMDR2 and SIRMDR2 */
0100 #define SIMDR2_BITLEN1(i)   (((i) - 1) << 24) /* Data Size (8-32 bits) */
0101 #define SIMDR2_WDLEN1(i)    (((i) - 1) << 16) /* Word Count (1-64/256 (SH, A1))) */
0102 #define SIMDR2_GRPMASK1     BIT(0)      /* Group Output Mask 1 (SH, A1) */
0103 
0104 /* SITSCR and SIRSCR */
0105 #define SISCR_BRPS_MASK     GENMASK(12, 8)  /* Prescaler Setting (1-32) */
0106 #define SISCR_BRPS(i)       (((i) - 1) << 8)
0107 #define SISCR_BRDV_MASK     GENMASK(2, 0)   /* Baud Rate Generator's Division Ratio */
0108 #define SISCR_BRDV_DIV_2    0
0109 #define SISCR_BRDV_DIV_4    1
0110 #define SISCR_BRDV_DIV_8    2
0111 #define SISCR_BRDV_DIV_16   3
0112 #define SISCR_BRDV_DIV_32   4
0113 #define SISCR_BRDV_DIV_1    7
0114 
0115 /* SICTR */
0116 #define SICTR_TSCKIZ_MASK   GENMASK(31, 30) /* Transmit Clock I/O Polarity Select */
0117 #define SICTR_TSCKIZ_SCK    BIT(31)     /*   Disable SCK when TX disabled */
0118 #define SICTR_TSCKIZ_POL_SHIFT  30      /*   Transmit Clock Polarity */
0119 #define SICTR_RSCKIZ_MASK   GENMASK(29, 28) /* Receive Clock Polarity Select */
0120 #define SICTR_RSCKIZ_SCK    BIT(29)     /*   Must match CTR_TSCKIZ_SCK */
0121 #define SICTR_RSCKIZ_POL_SHIFT  28      /*   Receive Clock Polarity */
0122 #define SICTR_TEDG_SHIFT    27      /* Transmit Timing (1 = falling edge) */
0123 #define SICTR_REDG_SHIFT    26      /* Receive Timing (1 = falling edge) */
0124 #define SICTR_TXDIZ_MASK    GENMASK(23, 22) /* Pin Output When TX is Disabled */
0125 #define SICTR_TXDIZ_LOW     (0 << 22)   /*   0 */
0126 #define SICTR_TXDIZ_HIGH    (1 << 22)   /*   1 */
0127 #define SICTR_TXDIZ_HIZ     (2 << 22)   /*   High-impedance */
0128 #define SICTR_TSCKE     BIT(15)     /* Transmit Serial Clock Output Enable */
0129 #define SICTR_TFSE      BIT(14)     /* Transmit Frame Sync Signal Output Enable */
0130 #define SICTR_TXE       BIT(9)      /* Transmit Enable */
0131 #define SICTR_RXE       BIT(8)      /* Receive Enable */
0132 #define SICTR_TXRST     BIT(1)      /* Transmit Reset */
0133 #define SICTR_RXRST     BIT(0)      /* Receive Reset */
0134 
0135 /* SIFCTR */
0136 #define SIFCTR_TFWM_MASK    GENMASK(31, 29) /* Transmit FIFO Watermark */
0137 #define SIFCTR_TFWM_64      (0 << 29)   /*  Transfer Request when 64 empty stages */
0138 #define SIFCTR_TFWM_32      (1 << 29)   /*  Transfer Request when 32 empty stages */
0139 #define SIFCTR_TFWM_24      (2 << 29)   /*  Transfer Request when 24 empty stages */
0140 #define SIFCTR_TFWM_16      (3 << 29)   /*  Transfer Request when 16 empty stages */
0141 #define SIFCTR_TFWM_12      (4 << 29)   /*  Transfer Request when 12 empty stages */
0142 #define SIFCTR_TFWM_8       (5 << 29)   /*  Transfer Request when 8 empty stages */
0143 #define SIFCTR_TFWM_4       (6 << 29)   /*  Transfer Request when 4 empty stages */
0144 #define SIFCTR_TFWM_1       (7 << 29)   /*  Transfer Request when 1 empty stage */
0145 #define SIFCTR_TFUA_MASK    GENMASK(26, 20) /* Transmit FIFO Usable Area */
0146 #define SIFCTR_TFUA_SHIFT   20
0147 #define SIFCTR_TFUA(i)      ((i) << SIFCTR_TFUA_SHIFT)
0148 #define SIFCTR_RFWM_MASK    GENMASK(15, 13) /* Receive FIFO Watermark */
0149 #define SIFCTR_RFWM_1       (0 << 13)   /*  Transfer Request when 1 valid stages */
0150 #define SIFCTR_RFWM_4       (1 << 13)   /*  Transfer Request when 4 valid stages */
0151 #define SIFCTR_RFWM_8       (2 << 13)   /*  Transfer Request when 8 valid stages */
0152 #define SIFCTR_RFWM_16      (3 << 13)   /*  Transfer Request when 16 valid stages */
0153 #define SIFCTR_RFWM_32      (4 << 13)   /*  Transfer Request when 32 valid stages */
0154 #define SIFCTR_RFWM_64      (5 << 13)   /*  Transfer Request when 64 valid stages */
0155 #define SIFCTR_RFWM_128     (6 << 13)   /*  Transfer Request when 128 valid stages */
0156 #define SIFCTR_RFWM_256     (7 << 13)   /*  Transfer Request when 256 valid stages */
0157 #define SIFCTR_RFUA_MASK    GENMASK(12, 4)  /* Receive FIFO Usable Area (0x40 = full) */
0158 #define SIFCTR_RFUA_SHIFT   4
0159 #define SIFCTR_RFUA(i)      ((i) << SIFCTR_RFUA_SHIFT)
0160 
0161 /* SISTR */
0162 #define SISTR_TFEMP     BIT(29) /* Transmit FIFO Empty */
0163 #define SISTR_TDREQ     BIT(28) /* Transmit Data Transfer Request */
0164 #define SISTR_TEOF      BIT(23) /* Frame Transmission End */
0165 #define SISTR_TFSERR        BIT(21) /* Transmit Frame Synchronization Error */
0166 #define SISTR_TFOVF     BIT(20) /* Transmit FIFO Overflow */
0167 #define SISTR_TFUDF     BIT(19) /* Transmit FIFO Underflow */
0168 #define SISTR_RFFUL     BIT(13) /* Receive FIFO Full */
0169 #define SISTR_RDREQ     BIT(12) /* Receive Data Transfer Request */
0170 #define SISTR_REOF      BIT(7)  /* Frame Reception End */
0171 #define SISTR_RFSERR        BIT(5)  /* Receive Frame Synchronization Error */
0172 #define SISTR_RFUDF     BIT(4)  /* Receive FIFO Underflow */
0173 #define SISTR_RFOVF     BIT(3)  /* Receive FIFO Overflow */
0174 
0175 /* SIIER */
0176 #define SIIER_TDMAE     BIT(31) /* Transmit Data DMA Transfer Req. Enable */
0177 #define SIIER_TFEMPE        BIT(29) /* Transmit FIFO Empty Enable */
0178 #define SIIER_TDREQE        BIT(28) /* Transmit Data Transfer Request Enable */
0179 #define SIIER_TEOFE     BIT(23) /* Frame Transmission End Enable */
0180 #define SIIER_TFSERRE       BIT(21) /* Transmit Frame Sync Error Enable */
0181 #define SIIER_TFOVFE        BIT(20) /* Transmit FIFO Overflow Enable */
0182 #define SIIER_TFUDFE        BIT(19) /* Transmit FIFO Underflow Enable */
0183 #define SIIER_RDMAE     BIT(15) /* Receive Data DMA Transfer Req. Enable */
0184 #define SIIER_RFFULE        BIT(13) /* Receive FIFO Full Enable */
0185 #define SIIER_RDREQE        BIT(12) /* Receive Data Transfer Request Enable */
0186 #define SIIER_REOFE     BIT(7)  /* Frame Reception End Enable */
0187 #define SIIER_RFSERRE       BIT(5)  /* Receive Frame Sync Error Enable */
0188 #define SIIER_RFUDFE        BIT(4)  /* Receive FIFO Underflow Enable */
0189 #define SIIER_RFOVFE        BIT(3)  /* Receive FIFO Overflow Enable */
0190 
0191 
0192 static u32 sh_msiof_read(struct sh_msiof_spi_priv *p, int reg_offs)
0193 {
0194     switch (reg_offs) {
0195     case SITSCR:
0196     case SIRSCR:
0197         return ioread16(p->mapbase + reg_offs);
0198     default:
0199         return ioread32(p->mapbase + reg_offs);
0200     }
0201 }
0202 
0203 static void sh_msiof_write(struct sh_msiof_spi_priv *p, int reg_offs,
0204                u32 value)
0205 {
0206     switch (reg_offs) {
0207     case SITSCR:
0208     case SIRSCR:
0209         iowrite16(value, p->mapbase + reg_offs);
0210         break;
0211     default:
0212         iowrite32(value, p->mapbase + reg_offs);
0213         break;
0214     }
0215 }
0216 
0217 static int sh_msiof_modify_ctr_wait(struct sh_msiof_spi_priv *p,
0218                     u32 clr, u32 set)
0219 {
0220     u32 mask = clr | set;
0221     u32 data;
0222 
0223     data = sh_msiof_read(p, SICTR);
0224     data &= ~clr;
0225     data |= set;
0226     sh_msiof_write(p, SICTR, data);
0227 
0228     return readl_poll_timeout_atomic(p->mapbase + SICTR, data,
0229                      (data & mask) == set, 1, 100);
0230 }
0231 
0232 static irqreturn_t sh_msiof_spi_irq(int irq, void *data)
0233 {
0234     struct sh_msiof_spi_priv *p = data;
0235 
0236     /* just disable the interrupt and wake up */
0237     sh_msiof_write(p, SIIER, 0);
0238     complete(&p->done);
0239 
0240     return IRQ_HANDLED;
0241 }
0242 
0243 static void sh_msiof_spi_reset_regs(struct sh_msiof_spi_priv *p)
0244 {
0245     u32 mask = SICTR_TXRST | SICTR_RXRST;
0246     u32 data;
0247 
0248     data = sh_msiof_read(p, SICTR);
0249     data |= mask;
0250     sh_msiof_write(p, SICTR, data);
0251 
0252     readl_poll_timeout_atomic(p->mapbase + SICTR, data, !(data & mask), 1,
0253                   100);
0254 }
0255 
0256 static const u32 sh_msiof_spi_div_array[] = {
0257     SISCR_BRDV_DIV_1, SISCR_BRDV_DIV_2, SISCR_BRDV_DIV_4,
0258     SISCR_BRDV_DIV_8, SISCR_BRDV_DIV_16, SISCR_BRDV_DIV_32,
0259 };
0260 
0261 static void sh_msiof_spi_set_clk_regs(struct sh_msiof_spi_priv *p,
0262                       struct spi_transfer *t)
0263 {
0264     unsigned long parent_rate = clk_get_rate(p->clk);
0265     unsigned int div_pow = p->min_div_pow;
0266     u32 spi_hz = t->speed_hz;
0267     unsigned long div;
0268     u32 brps, scr;
0269 
0270     if (!spi_hz || !parent_rate) {
0271         WARN(1, "Invalid clock rate parameters %lu and %u\n",
0272              parent_rate, spi_hz);
0273         return;
0274     }
0275 
0276     div = DIV_ROUND_UP(parent_rate, spi_hz);
0277     if (div <= 1024) {
0278         /* SISCR_BRDV_DIV_1 is valid only if BRPS is x 1/1 or x 1/2 */
0279         if (!div_pow && div <= 32 && div > 2)
0280             div_pow = 1;
0281 
0282         if (div_pow)
0283             brps = (div + 1) >> div_pow;
0284         else
0285             brps = div;
0286 
0287         for (; brps > 32; div_pow++)
0288             brps = (brps + 1) >> 1;
0289     } else {
0290         /* Set transfer rate composite divisor to 2^5 * 32 = 1024 */
0291         dev_err(&p->pdev->dev,
0292             "Requested SPI transfer rate %d is too low\n", spi_hz);
0293         div_pow = 5;
0294         brps = 32;
0295     }
0296 
0297     t->effective_speed_hz = parent_rate / (brps << div_pow);
0298 
0299     scr = sh_msiof_spi_div_array[div_pow] | SISCR_BRPS(brps);
0300     sh_msiof_write(p, SITSCR, scr);
0301     if (!(p->ctlr->flags & SPI_CONTROLLER_MUST_TX))
0302         sh_msiof_write(p, SIRSCR, scr);
0303 }
0304 
0305 static u32 sh_msiof_get_delay_bit(u32 dtdl_or_syncdl)
0306 {
0307     /*
0308      * DTDL/SYNCDL bit  : p->info->dtdl or p->info->syncdl
0309      * b'000        : 0
0310      * b'001        : 100
0311      * b'010        : 200
0312      * b'011 (SYNCDL only)  : 300
0313      * b'101        : 50
0314      * b'110        : 150
0315      */
0316     if (dtdl_or_syncdl % 100)
0317         return dtdl_or_syncdl / 100 + 5;
0318     else
0319         return dtdl_or_syncdl / 100;
0320 }
0321 
0322 static u32 sh_msiof_spi_get_dtdl_and_syncdl(struct sh_msiof_spi_priv *p)
0323 {
0324     u32 val;
0325 
0326     if (!p->info)
0327         return 0;
0328 
0329     /* check if DTDL and SYNCDL is allowed value */
0330     if (p->info->dtdl > 200 || p->info->syncdl > 300) {
0331         dev_warn(&p->pdev->dev, "DTDL or SYNCDL is too large\n");
0332         return 0;
0333     }
0334 
0335     /* check if the sum of DTDL and SYNCDL becomes an integer value  */
0336     if ((p->info->dtdl + p->info->syncdl) % 100) {
0337         dev_warn(&p->pdev->dev, "the sum of DTDL/SYNCDL is not good\n");
0338         return 0;
0339     }
0340 
0341     val = sh_msiof_get_delay_bit(p->info->dtdl) << SIMDR1_DTDL_SHIFT;
0342     val |= sh_msiof_get_delay_bit(p->info->syncdl) << SIMDR1_SYNCDL_SHIFT;
0343 
0344     return val;
0345 }
0346 
0347 static void sh_msiof_spi_set_pin_regs(struct sh_msiof_spi_priv *p, u32 ss,
0348                       u32 cpol, u32 cpha,
0349                       u32 tx_hi_z, u32 lsb_first, u32 cs_high)
0350 {
0351     u32 tmp;
0352     int edge;
0353 
0354     /*
0355      * CPOL CPHA     TSCKIZ RSCKIZ TEDG REDG
0356      *    0    0         10     10    1    1
0357      *    0    1         10     10    0    0
0358      *    1    0         11     11    0    0
0359      *    1    1         11     11    1    1
0360      */
0361     tmp = SIMDR1_SYNCMD_SPI | 1 << SIMDR1_FLD_SHIFT | SIMDR1_XXSTP;
0362     tmp |= !cs_high << SIMDR1_SYNCAC_SHIFT;
0363     tmp |= lsb_first << SIMDR1_BITLSB_SHIFT;
0364     tmp |= sh_msiof_spi_get_dtdl_and_syncdl(p);
0365     if (spi_controller_is_slave(p->ctlr)) {
0366         sh_msiof_write(p, SITMDR1, tmp | SITMDR1_PCON);
0367     } else {
0368         sh_msiof_write(p, SITMDR1,
0369                    tmp | SIMDR1_TRMD | SITMDR1_PCON |
0370                    (ss < MAX_SS ? ss : 0) << SITMDR1_SYNCCH_SHIFT);
0371     }
0372     if (p->ctlr->flags & SPI_CONTROLLER_MUST_TX) {
0373         /* These bits are reserved if RX needs TX */
0374         tmp &= ~0x0000ffff;
0375     }
0376     sh_msiof_write(p, SIRMDR1, tmp);
0377 
0378     tmp = 0;
0379     tmp |= SICTR_TSCKIZ_SCK | cpol << SICTR_TSCKIZ_POL_SHIFT;
0380     tmp |= SICTR_RSCKIZ_SCK | cpol << SICTR_RSCKIZ_POL_SHIFT;
0381 
0382     edge = cpol ^ !cpha;
0383 
0384     tmp |= edge << SICTR_TEDG_SHIFT;
0385     tmp |= edge << SICTR_REDG_SHIFT;
0386     tmp |= tx_hi_z ? SICTR_TXDIZ_HIZ : SICTR_TXDIZ_LOW;
0387     sh_msiof_write(p, SICTR, tmp);
0388 }
0389 
0390 static void sh_msiof_spi_set_mode_regs(struct sh_msiof_spi_priv *p,
0391                        const void *tx_buf, void *rx_buf,
0392                        u32 bits, u32 words)
0393 {
0394     u32 dr2 = SIMDR2_BITLEN1(bits) | SIMDR2_WDLEN1(words);
0395 
0396     if (tx_buf || (p->ctlr->flags & SPI_CONTROLLER_MUST_TX))
0397         sh_msiof_write(p, SITMDR2, dr2);
0398     else
0399         sh_msiof_write(p, SITMDR2, dr2 | SIMDR2_GRPMASK1);
0400 
0401     if (rx_buf)
0402         sh_msiof_write(p, SIRMDR2, dr2);
0403 }
0404 
0405 static void sh_msiof_reset_str(struct sh_msiof_spi_priv *p)
0406 {
0407     sh_msiof_write(p, SISTR,
0408                sh_msiof_read(p, SISTR) & ~(SISTR_TDREQ | SISTR_RDREQ));
0409 }
0410 
0411 static void sh_msiof_spi_write_fifo_8(struct sh_msiof_spi_priv *p,
0412                       const void *tx_buf, int words, int fs)
0413 {
0414     const u8 *buf_8 = tx_buf;
0415     int k;
0416 
0417     for (k = 0; k < words; k++)
0418         sh_msiof_write(p, SITFDR, buf_8[k] << fs);
0419 }
0420 
0421 static void sh_msiof_spi_write_fifo_16(struct sh_msiof_spi_priv *p,
0422                        const void *tx_buf, int words, int fs)
0423 {
0424     const u16 *buf_16 = tx_buf;
0425     int k;
0426 
0427     for (k = 0; k < words; k++)
0428         sh_msiof_write(p, SITFDR, buf_16[k] << fs);
0429 }
0430 
0431 static void sh_msiof_spi_write_fifo_16u(struct sh_msiof_spi_priv *p,
0432                     const void *tx_buf, int words, int fs)
0433 {
0434     const u16 *buf_16 = tx_buf;
0435     int k;
0436 
0437     for (k = 0; k < words; k++)
0438         sh_msiof_write(p, SITFDR, get_unaligned(&buf_16[k]) << fs);
0439 }
0440 
0441 static void sh_msiof_spi_write_fifo_32(struct sh_msiof_spi_priv *p,
0442                        const void *tx_buf, int words, int fs)
0443 {
0444     const u32 *buf_32 = tx_buf;
0445     int k;
0446 
0447     for (k = 0; k < words; k++)
0448         sh_msiof_write(p, SITFDR, buf_32[k] << fs);
0449 }
0450 
0451 static void sh_msiof_spi_write_fifo_32u(struct sh_msiof_spi_priv *p,
0452                     const void *tx_buf, int words, int fs)
0453 {
0454     const u32 *buf_32 = tx_buf;
0455     int k;
0456 
0457     for (k = 0; k < words; k++)
0458         sh_msiof_write(p, SITFDR, get_unaligned(&buf_32[k]) << fs);
0459 }
0460 
0461 static void sh_msiof_spi_write_fifo_s32(struct sh_msiof_spi_priv *p,
0462                     const void *tx_buf, int words, int fs)
0463 {
0464     const u32 *buf_32 = tx_buf;
0465     int k;
0466 
0467     for (k = 0; k < words; k++)
0468         sh_msiof_write(p, SITFDR, swab32(buf_32[k] << fs));
0469 }
0470 
0471 static void sh_msiof_spi_write_fifo_s32u(struct sh_msiof_spi_priv *p,
0472                      const void *tx_buf, int words, int fs)
0473 {
0474     const u32 *buf_32 = tx_buf;
0475     int k;
0476 
0477     for (k = 0; k < words; k++)
0478         sh_msiof_write(p, SITFDR, swab32(get_unaligned(&buf_32[k]) << fs));
0479 }
0480 
0481 static void sh_msiof_spi_read_fifo_8(struct sh_msiof_spi_priv *p,
0482                      void *rx_buf, int words, int fs)
0483 {
0484     u8 *buf_8 = rx_buf;
0485     int k;
0486 
0487     for (k = 0; k < words; k++)
0488         buf_8[k] = sh_msiof_read(p, SIRFDR) >> fs;
0489 }
0490 
0491 static void sh_msiof_spi_read_fifo_16(struct sh_msiof_spi_priv *p,
0492                       void *rx_buf, int words, int fs)
0493 {
0494     u16 *buf_16 = rx_buf;
0495     int k;
0496 
0497     for (k = 0; k < words; k++)
0498         buf_16[k] = sh_msiof_read(p, SIRFDR) >> fs;
0499 }
0500 
0501 static void sh_msiof_spi_read_fifo_16u(struct sh_msiof_spi_priv *p,
0502                        void *rx_buf, int words, int fs)
0503 {
0504     u16 *buf_16 = rx_buf;
0505     int k;
0506 
0507     for (k = 0; k < words; k++)
0508         put_unaligned(sh_msiof_read(p, SIRFDR) >> fs, &buf_16[k]);
0509 }
0510 
0511 static void sh_msiof_spi_read_fifo_32(struct sh_msiof_spi_priv *p,
0512                       void *rx_buf, int words, int fs)
0513 {
0514     u32 *buf_32 = rx_buf;
0515     int k;
0516 
0517     for (k = 0; k < words; k++)
0518         buf_32[k] = sh_msiof_read(p, SIRFDR) >> fs;
0519 }
0520 
0521 static void sh_msiof_spi_read_fifo_32u(struct sh_msiof_spi_priv *p,
0522                        void *rx_buf, int words, int fs)
0523 {
0524     u32 *buf_32 = rx_buf;
0525     int k;
0526 
0527     for (k = 0; k < words; k++)
0528         put_unaligned(sh_msiof_read(p, SIRFDR) >> fs, &buf_32[k]);
0529 }
0530 
0531 static void sh_msiof_spi_read_fifo_s32(struct sh_msiof_spi_priv *p,
0532                        void *rx_buf, int words, int fs)
0533 {
0534     u32 *buf_32 = rx_buf;
0535     int k;
0536 
0537     for (k = 0; k < words; k++)
0538         buf_32[k] = swab32(sh_msiof_read(p, SIRFDR) >> fs);
0539 }
0540 
0541 static void sh_msiof_spi_read_fifo_s32u(struct sh_msiof_spi_priv *p,
0542                        void *rx_buf, int words, int fs)
0543 {
0544     u32 *buf_32 = rx_buf;
0545     int k;
0546 
0547     for (k = 0; k < words; k++)
0548         put_unaligned(swab32(sh_msiof_read(p, SIRFDR) >> fs), &buf_32[k]);
0549 }
0550 
0551 static int sh_msiof_spi_setup(struct spi_device *spi)
0552 {
0553     struct sh_msiof_spi_priv *p =
0554         spi_controller_get_devdata(spi->controller);
0555     u32 clr, set, tmp;
0556 
0557     if (spi->cs_gpiod || spi_controller_is_slave(p->ctlr))
0558         return 0;
0559 
0560     if (p->native_cs_inited &&
0561         (p->native_cs_high == !!(spi->mode & SPI_CS_HIGH)))
0562         return 0;
0563 
0564     /* Configure native chip select mode/polarity early */
0565     clr = SIMDR1_SYNCMD_MASK;
0566     set = SIMDR1_SYNCMD_SPI;
0567     if (spi->mode & SPI_CS_HIGH)
0568         clr |= BIT(SIMDR1_SYNCAC_SHIFT);
0569     else
0570         set |= BIT(SIMDR1_SYNCAC_SHIFT);
0571     pm_runtime_get_sync(&p->pdev->dev);
0572     tmp = sh_msiof_read(p, SITMDR1) & ~clr;
0573     sh_msiof_write(p, SITMDR1, tmp | set | SIMDR1_TRMD | SITMDR1_PCON);
0574     tmp = sh_msiof_read(p, SIRMDR1) & ~clr;
0575     sh_msiof_write(p, SIRMDR1, tmp | set);
0576     pm_runtime_put(&p->pdev->dev);
0577     p->native_cs_high = spi->mode & SPI_CS_HIGH;
0578     p->native_cs_inited = true;
0579     return 0;
0580 }
0581 
0582 static int sh_msiof_prepare_message(struct spi_controller *ctlr,
0583                     struct spi_message *msg)
0584 {
0585     struct sh_msiof_spi_priv *p = spi_controller_get_devdata(ctlr);
0586     const struct spi_device *spi = msg->spi;
0587     u32 ss, cs_high;
0588 
0589     /* Configure pins before asserting CS */
0590     if (spi->cs_gpiod) {
0591         ss = ctlr->unused_native_cs;
0592         cs_high = p->native_cs_high;
0593     } else {
0594         ss = spi->chip_select;
0595         cs_high = !!(spi->mode & SPI_CS_HIGH);
0596     }
0597     sh_msiof_spi_set_pin_regs(p, ss, !!(spi->mode & SPI_CPOL),
0598                   !!(spi->mode & SPI_CPHA),
0599                   !!(spi->mode & SPI_3WIRE),
0600                   !!(spi->mode & SPI_LSB_FIRST), cs_high);
0601     return 0;
0602 }
0603 
0604 static int sh_msiof_spi_start(struct sh_msiof_spi_priv *p, void *rx_buf)
0605 {
0606     bool slave = spi_controller_is_slave(p->ctlr);
0607     int ret = 0;
0608 
0609     /* setup clock and rx/tx signals */
0610     if (!slave)
0611         ret = sh_msiof_modify_ctr_wait(p, 0, SICTR_TSCKE);
0612     if (rx_buf && !ret)
0613         ret = sh_msiof_modify_ctr_wait(p, 0, SICTR_RXE);
0614     if (!ret)
0615         ret = sh_msiof_modify_ctr_wait(p, 0, SICTR_TXE);
0616 
0617     /* start by setting frame bit */
0618     if (!ret && !slave)
0619         ret = sh_msiof_modify_ctr_wait(p, 0, SICTR_TFSE);
0620 
0621     return ret;
0622 }
0623 
0624 static int sh_msiof_spi_stop(struct sh_msiof_spi_priv *p, void *rx_buf)
0625 {
0626     bool slave = spi_controller_is_slave(p->ctlr);
0627     int ret = 0;
0628 
0629     /* shut down frame, rx/tx and clock signals */
0630     if (!slave)
0631         ret = sh_msiof_modify_ctr_wait(p, SICTR_TFSE, 0);
0632     if (!ret)
0633         ret = sh_msiof_modify_ctr_wait(p, SICTR_TXE, 0);
0634     if (rx_buf && !ret)
0635         ret = sh_msiof_modify_ctr_wait(p, SICTR_RXE, 0);
0636     if (!ret && !slave)
0637         ret = sh_msiof_modify_ctr_wait(p, SICTR_TSCKE, 0);
0638 
0639     return ret;
0640 }
0641 
0642 static int sh_msiof_slave_abort(struct spi_controller *ctlr)
0643 {
0644     struct sh_msiof_spi_priv *p = spi_controller_get_devdata(ctlr);
0645 
0646     p->slave_aborted = true;
0647     complete(&p->done);
0648     complete(&p->done_txdma);
0649     return 0;
0650 }
0651 
0652 static int sh_msiof_wait_for_completion(struct sh_msiof_spi_priv *p,
0653                     struct completion *x)
0654 {
0655     if (spi_controller_is_slave(p->ctlr)) {
0656         if (wait_for_completion_interruptible(x) ||
0657             p->slave_aborted) {
0658             dev_dbg(&p->pdev->dev, "interrupted\n");
0659             return -EINTR;
0660         }
0661     } else {
0662         if (!wait_for_completion_timeout(x, HZ)) {
0663             dev_err(&p->pdev->dev, "timeout\n");
0664             return -ETIMEDOUT;
0665         }
0666     }
0667 
0668     return 0;
0669 }
0670 
0671 static int sh_msiof_spi_txrx_once(struct sh_msiof_spi_priv *p,
0672                   void (*tx_fifo)(struct sh_msiof_spi_priv *,
0673                           const void *, int, int),
0674                   void (*rx_fifo)(struct sh_msiof_spi_priv *,
0675                           void *, int, int),
0676                   const void *tx_buf, void *rx_buf,
0677                   int words, int bits)
0678 {
0679     int fifo_shift;
0680     int ret;
0681 
0682     /* limit maximum word transfer to rx/tx fifo size */
0683     if (tx_buf)
0684         words = min_t(int, words, p->tx_fifo_size);
0685     if (rx_buf)
0686         words = min_t(int, words, p->rx_fifo_size);
0687 
0688     /* the fifo contents need shifting */
0689     fifo_shift = 32 - bits;
0690 
0691     /* default FIFO watermarks for PIO */
0692     sh_msiof_write(p, SIFCTR, 0);
0693 
0694     /* setup msiof transfer mode registers */
0695     sh_msiof_spi_set_mode_regs(p, tx_buf, rx_buf, bits, words);
0696     sh_msiof_write(p, SIIER, SIIER_TEOFE | SIIER_REOFE);
0697 
0698     /* write tx fifo */
0699     if (tx_buf)
0700         tx_fifo(p, tx_buf, words, fifo_shift);
0701 
0702     reinit_completion(&p->done);
0703     p->slave_aborted = false;
0704 
0705     ret = sh_msiof_spi_start(p, rx_buf);
0706     if (ret) {
0707         dev_err(&p->pdev->dev, "failed to start hardware\n");
0708         goto stop_ier;
0709     }
0710 
0711     /* wait for tx fifo to be emptied / rx fifo to be filled */
0712     ret = sh_msiof_wait_for_completion(p, &p->done);
0713     if (ret)
0714         goto stop_reset;
0715 
0716     /* read rx fifo */
0717     if (rx_buf)
0718         rx_fifo(p, rx_buf, words, fifo_shift);
0719 
0720     /* clear status bits */
0721     sh_msiof_reset_str(p);
0722 
0723     ret = sh_msiof_spi_stop(p, rx_buf);
0724     if (ret) {
0725         dev_err(&p->pdev->dev, "failed to shut down hardware\n");
0726         return ret;
0727     }
0728 
0729     return words;
0730 
0731 stop_reset:
0732     sh_msiof_reset_str(p);
0733     sh_msiof_spi_stop(p, rx_buf);
0734 stop_ier:
0735     sh_msiof_write(p, SIIER, 0);
0736     return ret;
0737 }
0738 
0739 static void sh_msiof_dma_complete(void *arg)
0740 {
0741     complete(arg);
0742 }
0743 
0744 static int sh_msiof_dma_once(struct sh_msiof_spi_priv *p, const void *tx,
0745                  void *rx, unsigned int len)
0746 {
0747     u32 ier_bits = 0;
0748     struct dma_async_tx_descriptor *desc_tx = NULL, *desc_rx = NULL;
0749     dma_cookie_t cookie;
0750     int ret;
0751 
0752     /* First prepare and submit the DMA request(s), as this may fail */
0753     if (rx) {
0754         ier_bits |= SIIER_RDREQE | SIIER_RDMAE;
0755         desc_rx = dmaengine_prep_slave_single(p->ctlr->dma_rx,
0756                     p->rx_dma_addr, len, DMA_DEV_TO_MEM,
0757                     DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
0758         if (!desc_rx)
0759             return -EAGAIN;
0760 
0761         desc_rx->callback = sh_msiof_dma_complete;
0762         desc_rx->callback_param = &p->done;
0763         cookie = dmaengine_submit(desc_rx);
0764         if (dma_submit_error(cookie))
0765             return cookie;
0766     }
0767 
0768     if (tx) {
0769         ier_bits |= SIIER_TDREQE | SIIER_TDMAE;
0770         dma_sync_single_for_device(p->ctlr->dma_tx->device->dev,
0771                        p->tx_dma_addr, len, DMA_TO_DEVICE);
0772         desc_tx = dmaengine_prep_slave_single(p->ctlr->dma_tx,
0773                     p->tx_dma_addr, len, DMA_MEM_TO_DEV,
0774                     DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
0775         if (!desc_tx) {
0776             ret = -EAGAIN;
0777             goto no_dma_tx;
0778         }
0779 
0780         desc_tx->callback = sh_msiof_dma_complete;
0781         desc_tx->callback_param = &p->done_txdma;
0782         cookie = dmaengine_submit(desc_tx);
0783         if (dma_submit_error(cookie)) {
0784             ret = cookie;
0785             goto no_dma_tx;
0786         }
0787     }
0788 
0789     /* 1 stage FIFO watermarks for DMA */
0790     sh_msiof_write(p, SIFCTR, SIFCTR_TFWM_1 | SIFCTR_RFWM_1);
0791 
0792     /* setup msiof transfer mode registers (32-bit words) */
0793     sh_msiof_spi_set_mode_regs(p, tx, rx, 32, len / 4);
0794 
0795     sh_msiof_write(p, SIIER, ier_bits);
0796 
0797     reinit_completion(&p->done);
0798     if (tx)
0799         reinit_completion(&p->done_txdma);
0800     p->slave_aborted = false;
0801 
0802     /* Now start DMA */
0803     if (rx)
0804         dma_async_issue_pending(p->ctlr->dma_rx);
0805     if (tx)
0806         dma_async_issue_pending(p->ctlr->dma_tx);
0807 
0808     ret = sh_msiof_spi_start(p, rx);
0809     if (ret) {
0810         dev_err(&p->pdev->dev, "failed to start hardware\n");
0811         goto stop_dma;
0812     }
0813 
0814     if (tx) {
0815         /* wait for tx DMA completion */
0816         ret = sh_msiof_wait_for_completion(p, &p->done_txdma);
0817         if (ret)
0818             goto stop_reset;
0819     }
0820 
0821     if (rx) {
0822         /* wait for rx DMA completion */
0823         ret = sh_msiof_wait_for_completion(p, &p->done);
0824         if (ret)
0825             goto stop_reset;
0826 
0827         sh_msiof_write(p, SIIER, 0);
0828     } else {
0829         /* wait for tx fifo to be emptied */
0830         sh_msiof_write(p, SIIER, SIIER_TEOFE);
0831         ret = sh_msiof_wait_for_completion(p, &p->done);
0832         if (ret)
0833             goto stop_reset;
0834     }
0835 
0836     /* clear status bits */
0837     sh_msiof_reset_str(p);
0838 
0839     ret = sh_msiof_spi_stop(p, rx);
0840     if (ret) {
0841         dev_err(&p->pdev->dev, "failed to shut down hardware\n");
0842         return ret;
0843     }
0844 
0845     if (rx)
0846         dma_sync_single_for_cpu(p->ctlr->dma_rx->device->dev,
0847                     p->rx_dma_addr, len, DMA_FROM_DEVICE);
0848 
0849     return 0;
0850 
0851 stop_reset:
0852     sh_msiof_reset_str(p);
0853     sh_msiof_spi_stop(p, rx);
0854 stop_dma:
0855     if (tx)
0856         dmaengine_terminate_sync(p->ctlr->dma_tx);
0857 no_dma_tx:
0858     if (rx)
0859         dmaengine_terminate_sync(p->ctlr->dma_rx);
0860     sh_msiof_write(p, SIIER, 0);
0861     return ret;
0862 }
0863 
0864 static void copy_bswap32(u32 *dst, const u32 *src, unsigned int words)
0865 {
0866     /* src or dst can be unaligned, but not both */
0867     if ((unsigned long)src & 3) {
0868         while (words--) {
0869             *dst++ = swab32(get_unaligned(src));
0870             src++;
0871         }
0872     } else if ((unsigned long)dst & 3) {
0873         while (words--) {
0874             put_unaligned(swab32(*src++), dst);
0875             dst++;
0876         }
0877     } else {
0878         while (words--)
0879             *dst++ = swab32(*src++);
0880     }
0881 }
0882 
0883 static void copy_wswap32(u32 *dst, const u32 *src, unsigned int words)
0884 {
0885     /* src or dst can be unaligned, but not both */
0886     if ((unsigned long)src & 3) {
0887         while (words--) {
0888             *dst++ = swahw32(get_unaligned(src));
0889             src++;
0890         }
0891     } else if ((unsigned long)dst & 3) {
0892         while (words--) {
0893             put_unaligned(swahw32(*src++), dst);
0894             dst++;
0895         }
0896     } else {
0897         while (words--)
0898             *dst++ = swahw32(*src++);
0899     }
0900 }
0901 
0902 static void copy_plain32(u32 *dst, const u32 *src, unsigned int words)
0903 {
0904     memcpy(dst, src, words * 4);
0905 }
0906 
0907 static int sh_msiof_transfer_one(struct spi_controller *ctlr,
0908                  struct spi_device *spi,
0909                  struct spi_transfer *t)
0910 {
0911     struct sh_msiof_spi_priv *p = spi_controller_get_devdata(ctlr);
0912     void (*copy32)(u32 *, const u32 *, unsigned int);
0913     void (*tx_fifo)(struct sh_msiof_spi_priv *, const void *, int, int);
0914     void (*rx_fifo)(struct sh_msiof_spi_priv *, void *, int, int);
0915     const void *tx_buf = t->tx_buf;
0916     void *rx_buf = t->rx_buf;
0917     unsigned int len = t->len;
0918     unsigned int bits = t->bits_per_word;
0919     unsigned int bytes_per_word;
0920     unsigned int words;
0921     int n;
0922     bool swab;
0923     int ret;
0924 
0925     /* reset registers */
0926     sh_msiof_spi_reset_regs(p);
0927 
0928     /* setup clocks (clock already enabled in chipselect()) */
0929     if (!spi_controller_is_slave(p->ctlr))
0930         sh_msiof_spi_set_clk_regs(p, t);
0931 
0932     while (ctlr->dma_tx && len > 15) {
0933         /*
0934          *  DMA supports 32-bit words only, hence pack 8-bit and 16-bit
0935          *  words, with byte resp. word swapping.
0936          */
0937         unsigned int l = 0;
0938 
0939         if (tx_buf)
0940             l = min(round_down(len, 4), p->tx_fifo_size * 4);
0941         if (rx_buf)
0942             l = min(round_down(len, 4), p->rx_fifo_size * 4);
0943 
0944         if (bits <= 8) {
0945             copy32 = copy_bswap32;
0946         } else if (bits <= 16) {
0947             copy32 = copy_wswap32;
0948         } else {
0949             copy32 = copy_plain32;
0950         }
0951 
0952         if (tx_buf)
0953             copy32(p->tx_dma_page, tx_buf, l / 4);
0954 
0955         ret = sh_msiof_dma_once(p, tx_buf, rx_buf, l);
0956         if (ret == -EAGAIN) {
0957             dev_warn_once(&p->pdev->dev,
0958                 "DMA not available, falling back to PIO\n");
0959             break;
0960         }
0961         if (ret)
0962             return ret;
0963 
0964         if (rx_buf) {
0965             copy32(rx_buf, p->rx_dma_page, l / 4);
0966             rx_buf += l;
0967         }
0968         if (tx_buf)
0969             tx_buf += l;
0970 
0971         len -= l;
0972         if (!len)
0973             return 0;
0974     }
0975 
0976     if (bits <= 8 && len > 15) {
0977         bits = 32;
0978         swab = true;
0979     } else {
0980         swab = false;
0981     }
0982 
0983     /* setup bytes per word and fifo read/write functions */
0984     if (bits <= 8) {
0985         bytes_per_word = 1;
0986         tx_fifo = sh_msiof_spi_write_fifo_8;
0987         rx_fifo = sh_msiof_spi_read_fifo_8;
0988     } else if (bits <= 16) {
0989         bytes_per_word = 2;
0990         if ((unsigned long)tx_buf & 0x01)
0991             tx_fifo = sh_msiof_spi_write_fifo_16u;
0992         else
0993             tx_fifo = sh_msiof_spi_write_fifo_16;
0994 
0995         if ((unsigned long)rx_buf & 0x01)
0996             rx_fifo = sh_msiof_spi_read_fifo_16u;
0997         else
0998             rx_fifo = sh_msiof_spi_read_fifo_16;
0999     } else if (swab) {
1000         bytes_per_word = 4;
1001         if ((unsigned long)tx_buf & 0x03)
1002             tx_fifo = sh_msiof_spi_write_fifo_s32u;
1003         else
1004             tx_fifo = sh_msiof_spi_write_fifo_s32;
1005 
1006         if ((unsigned long)rx_buf & 0x03)
1007             rx_fifo = sh_msiof_spi_read_fifo_s32u;
1008         else
1009             rx_fifo = sh_msiof_spi_read_fifo_s32;
1010     } else {
1011         bytes_per_word = 4;
1012         if ((unsigned long)tx_buf & 0x03)
1013             tx_fifo = sh_msiof_spi_write_fifo_32u;
1014         else
1015             tx_fifo = sh_msiof_spi_write_fifo_32;
1016 
1017         if ((unsigned long)rx_buf & 0x03)
1018             rx_fifo = sh_msiof_spi_read_fifo_32u;
1019         else
1020             rx_fifo = sh_msiof_spi_read_fifo_32;
1021     }
1022 
1023     /* transfer in fifo sized chunks */
1024     words = len / bytes_per_word;
1025 
1026     while (words > 0) {
1027         n = sh_msiof_spi_txrx_once(p, tx_fifo, rx_fifo, tx_buf, rx_buf,
1028                        words, bits);
1029         if (n < 0)
1030             return n;
1031 
1032         if (tx_buf)
1033             tx_buf += n * bytes_per_word;
1034         if (rx_buf)
1035             rx_buf += n * bytes_per_word;
1036         words -= n;
1037 
1038         if (words == 0 && (len % bytes_per_word)) {
1039             words = len % bytes_per_word;
1040             bits = t->bits_per_word;
1041             bytes_per_word = 1;
1042             tx_fifo = sh_msiof_spi_write_fifo_8;
1043             rx_fifo = sh_msiof_spi_read_fifo_8;
1044         }
1045     }
1046 
1047     return 0;
1048 }
1049 
1050 static const struct sh_msiof_chipdata sh_data = {
1051     .bits_per_word_mask = SPI_BPW_RANGE_MASK(8, 32),
1052     .tx_fifo_size = 64,
1053     .rx_fifo_size = 64,
1054     .ctlr_flags = 0,
1055     .min_div_pow = 0,
1056 };
1057 
1058 static const struct sh_msiof_chipdata rcar_gen2_data = {
1059     .bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16) |
1060                   SPI_BPW_MASK(24) | SPI_BPW_MASK(32),
1061     .tx_fifo_size = 64,
1062     .rx_fifo_size = 64,
1063     .ctlr_flags = SPI_CONTROLLER_MUST_TX,
1064     .min_div_pow = 0,
1065 };
1066 
1067 static const struct sh_msiof_chipdata rcar_gen3_data = {
1068     .bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16) |
1069                   SPI_BPW_MASK(24) | SPI_BPW_MASK(32),
1070     .tx_fifo_size = 64,
1071     .rx_fifo_size = 64,
1072     .ctlr_flags = SPI_CONTROLLER_MUST_TX,
1073     .min_div_pow = 1,
1074 };
1075 
1076 static const struct of_device_id sh_msiof_match[] = {
1077     { .compatible = "renesas,sh-mobile-msiof", .data = &sh_data },
1078     { .compatible = "renesas,msiof-r8a7743",   .data = &rcar_gen2_data },
1079     { .compatible = "renesas,msiof-r8a7745",   .data = &rcar_gen2_data },
1080     { .compatible = "renesas,msiof-r8a7790",   .data = &rcar_gen2_data },
1081     { .compatible = "renesas,msiof-r8a7791",   .data = &rcar_gen2_data },
1082     { .compatible = "renesas,msiof-r8a7792",   .data = &rcar_gen2_data },
1083     { .compatible = "renesas,msiof-r8a7793",   .data = &rcar_gen2_data },
1084     { .compatible = "renesas,msiof-r8a7794",   .data = &rcar_gen2_data },
1085     { .compatible = "renesas,rcar-gen2-msiof", .data = &rcar_gen2_data },
1086     { .compatible = "renesas,msiof-r8a7796",   .data = &rcar_gen3_data },
1087     { .compatible = "renesas,rcar-gen3-msiof", .data = &rcar_gen3_data },
1088     { .compatible = "renesas,sh-msiof",        .data = &sh_data }, /* Deprecated */
1089     {},
1090 };
1091 MODULE_DEVICE_TABLE(of, sh_msiof_match);
1092 
1093 #ifdef CONFIG_OF
1094 static struct sh_msiof_spi_info *sh_msiof_spi_parse_dt(struct device *dev)
1095 {
1096     struct sh_msiof_spi_info *info;
1097     struct device_node *np = dev->of_node;
1098     u32 num_cs = 1;
1099 
1100     info = devm_kzalloc(dev, sizeof(struct sh_msiof_spi_info), GFP_KERNEL);
1101     if (!info)
1102         return NULL;
1103 
1104     info->mode = of_property_read_bool(np, "spi-slave") ? MSIOF_SPI_SLAVE
1105                                 : MSIOF_SPI_MASTER;
1106 
1107     /* Parse the MSIOF properties */
1108     if (info->mode == MSIOF_SPI_MASTER)
1109         of_property_read_u32(np, "num-cs", &num_cs);
1110     of_property_read_u32(np, "renesas,tx-fifo-size",
1111                     &info->tx_fifo_override);
1112     of_property_read_u32(np, "renesas,rx-fifo-size",
1113                     &info->rx_fifo_override);
1114     of_property_read_u32(np, "renesas,dtdl", &info->dtdl);
1115     of_property_read_u32(np, "renesas,syncdl", &info->syncdl);
1116 
1117     info->num_chipselect = num_cs;
1118 
1119     return info;
1120 }
1121 #else
1122 static struct sh_msiof_spi_info *sh_msiof_spi_parse_dt(struct device *dev)
1123 {
1124     return NULL;
1125 }
1126 #endif
1127 
1128 static struct dma_chan *sh_msiof_request_dma_chan(struct device *dev,
1129     enum dma_transfer_direction dir, unsigned int id, dma_addr_t port_addr)
1130 {
1131     dma_cap_mask_t mask;
1132     struct dma_chan *chan;
1133     struct dma_slave_config cfg;
1134     int ret;
1135 
1136     dma_cap_zero(mask);
1137     dma_cap_set(DMA_SLAVE, mask);
1138 
1139     chan = dma_request_slave_channel_compat(mask, shdma_chan_filter,
1140                 (void *)(unsigned long)id, dev,
1141                 dir == DMA_MEM_TO_DEV ? "tx" : "rx");
1142     if (!chan) {
1143         dev_warn(dev, "dma_request_slave_channel_compat failed\n");
1144         return NULL;
1145     }
1146 
1147     memset(&cfg, 0, sizeof(cfg));
1148     cfg.direction = dir;
1149     if (dir == DMA_MEM_TO_DEV) {
1150         cfg.dst_addr = port_addr;
1151         cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1152     } else {
1153         cfg.src_addr = port_addr;
1154         cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1155     }
1156 
1157     ret = dmaengine_slave_config(chan, &cfg);
1158     if (ret) {
1159         dev_warn(dev, "dmaengine_slave_config failed %d\n", ret);
1160         dma_release_channel(chan);
1161         return NULL;
1162     }
1163 
1164     return chan;
1165 }
1166 
1167 static int sh_msiof_request_dma(struct sh_msiof_spi_priv *p)
1168 {
1169     struct platform_device *pdev = p->pdev;
1170     struct device *dev = &pdev->dev;
1171     const struct sh_msiof_spi_info *info = p->info;
1172     unsigned int dma_tx_id, dma_rx_id;
1173     const struct resource *res;
1174     struct spi_controller *ctlr;
1175     struct device *tx_dev, *rx_dev;
1176 
1177     if (dev->of_node) {
1178         /* In the OF case we will get the slave IDs from the DT */
1179         dma_tx_id = 0;
1180         dma_rx_id = 0;
1181     } else if (info && info->dma_tx_id && info->dma_rx_id) {
1182         dma_tx_id = info->dma_tx_id;
1183         dma_rx_id = info->dma_rx_id;
1184     } else {
1185         /* The driver assumes no error */
1186         return 0;
1187     }
1188 
1189     /* The DMA engine uses the second register set, if present */
1190     res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1191     if (!res)
1192         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1193 
1194     ctlr = p->ctlr;
1195     ctlr->dma_tx = sh_msiof_request_dma_chan(dev, DMA_MEM_TO_DEV,
1196                          dma_tx_id, res->start + SITFDR);
1197     if (!ctlr->dma_tx)
1198         return -ENODEV;
1199 
1200     ctlr->dma_rx = sh_msiof_request_dma_chan(dev, DMA_DEV_TO_MEM,
1201                          dma_rx_id, res->start + SIRFDR);
1202     if (!ctlr->dma_rx)
1203         goto free_tx_chan;
1204 
1205     p->tx_dma_page = (void *)__get_free_page(GFP_KERNEL | GFP_DMA);
1206     if (!p->tx_dma_page)
1207         goto free_rx_chan;
1208 
1209     p->rx_dma_page = (void *)__get_free_page(GFP_KERNEL | GFP_DMA);
1210     if (!p->rx_dma_page)
1211         goto free_tx_page;
1212 
1213     tx_dev = ctlr->dma_tx->device->dev;
1214     p->tx_dma_addr = dma_map_single(tx_dev, p->tx_dma_page, PAGE_SIZE,
1215                     DMA_TO_DEVICE);
1216     if (dma_mapping_error(tx_dev, p->tx_dma_addr))
1217         goto free_rx_page;
1218 
1219     rx_dev = ctlr->dma_rx->device->dev;
1220     p->rx_dma_addr = dma_map_single(rx_dev, p->rx_dma_page, PAGE_SIZE,
1221                     DMA_FROM_DEVICE);
1222     if (dma_mapping_error(rx_dev, p->rx_dma_addr))
1223         goto unmap_tx_page;
1224 
1225     dev_info(dev, "DMA available");
1226     return 0;
1227 
1228 unmap_tx_page:
1229     dma_unmap_single(tx_dev, p->tx_dma_addr, PAGE_SIZE, DMA_TO_DEVICE);
1230 free_rx_page:
1231     free_page((unsigned long)p->rx_dma_page);
1232 free_tx_page:
1233     free_page((unsigned long)p->tx_dma_page);
1234 free_rx_chan:
1235     dma_release_channel(ctlr->dma_rx);
1236 free_tx_chan:
1237     dma_release_channel(ctlr->dma_tx);
1238     ctlr->dma_tx = NULL;
1239     return -ENODEV;
1240 }
1241 
1242 static void sh_msiof_release_dma(struct sh_msiof_spi_priv *p)
1243 {
1244     struct spi_controller *ctlr = p->ctlr;
1245 
1246     if (!ctlr->dma_tx)
1247         return;
1248 
1249     dma_unmap_single(ctlr->dma_rx->device->dev, p->rx_dma_addr, PAGE_SIZE,
1250              DMA_FROM_DEVICE);
1251     dma_unmap_single(ctlr->dma_tx->device->dev, p->tx_dma_addr, PAGE_SIZE,
1252              DMA_TO_DEVICE);
1253     free_page((unsigned long)p->rx_dma_page);
1254     free_page((unsigned long)p->tx_dma_page);
1255     dma_release_channel(ctlr->dma_rx);
1256     dma_release_channel(ctlr->dma_tx);
1257 }
1258 
1259 static int sh_msiof_spi_probe(struct platform_device *pdev)
1260 {
1261     struct spi_controller *ctlr;
1262     const struct sh_msiof_chipdata *chipdata;
1263     struct sh_msiof_spi_info *info;
1264     struct sh_msiof_spi_priv *p;
1265     unsigned long clksrc;
1266     int i;
1267     int ret;
1268 
1269     chipdata = of_device_get_match_data(&pdev->dev);
1270     if (chipdata) {
1271         info = sh_msiof_spi_parse_dt(&pdev->dev);
1272     } else {
1273         chipdata = (const void *)pdev->id_entry->driver_data;
1274         info = dev_get_platdata(&pdev->dev);
1275     }
1276 
1277     if (!info) {
1278         dev_err(&pdev->dev, "failed to obtain device info\n");
1279         return -ENXIO;
1280     }
1281 
1282     if (info->mode == MSIOF_SPI_SLAVE)
1283         ctlr = spi_alloc_slave(&pdev->dev,
1284                        sizeof(struct sh_msiof_spi_priv));
1285     else
1286         ctlr = spi_alloc_master(&pdev->dev,
1287                     sizeof(struct sh_msiof_spi_priv));
1288     if (ctlr == NULL)
1289         return -ENOMEM;
1290 
1291     p = spi_controller_get_devdata(ctlr);
1292 
1293     platform_set_drvdata(pdev, p);
1294     p->ctlr = ctlr;
1295     p->info = info;
1296     p->min_div_pow = chipdata->min_div_pow;
1297 
1298     init_completion(&p->done);
1299     init_completion(&p->done_txdma);
1300 
1301     p->clk = devm_clk_get(&pdev->dev, NULL);
1302     if (IS_ERR(p->clk)) {
1303         dev_err(&pdev->dev, "cannot get clock\n");
1304         ret = PTR_ERR(p->clk);
1305         goto err1;
1306     }
1307 
1308     i = platform_get_irq(pdev, 0);
1309     if (i < 0) {
1310         ret = i;
1311         goto err1;
1312     }
1313 
1314     p->mapbase = devm_platform_ioremap_resource(pdev, 0);
1315     if (IS_ERR(p->mapbase)) {
1316         ret = PTR_ERR(p->mapbase);
1317         goto err1;
1318     }
1319 
1320     ret = devm_request_irq(&pdev->dev, i, sh_msiof_spi_irq, 0,
1321                    dev_name(&pdev->dev), p);
1322     if (ret) {
1323         dev_err(&pdev->dev, "unable to request irq\n");
1324         goto err1;
1325     }
1326 
1327     p->pdev = pdev;
1328     pm_runtime_enable(&pdev->dev);
1329 
1330     /* Platform data may override FIFO sizes */
1331     p->tx_fifo_size = chipdata->tx_fifo_size;
1332     p->rx_fifo_size = chipdata->rx_fifo_size;
1333     if (p->info->tx_fifo_override)
1334         p->tx_fifo_size = p->info->tx_fifo_override;
1335     if (p->info->rx_fifo_override)
1336         p->rx_fifo_size = p->info->rx_fifo_override;
1337 
1338     /* init controller code */
1339     ctlr->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1340     ctlr->mode_bits |= SPI_LSB_FIRST | SPI_3WIRE;
1341     clksrc = clk_get_rate(p->clk);
1342     ctlr->min_speed_hz = DIV_ROUND_UP(clksrc, 1024);
1343     ctlr->max_speed_hz = DIV_ROUND_UP(clksrc, 1 << p->min_div_pow);
1344     ctlr->flags = chipdata->ctlr_flags;
1345     ctlr->bus_num = pdev->id;
1346     ctlr->num_chipselect = p->info->num_chipselect;
1347     ctlr->dev.of_node = pdev->dev.of_node;
1348     ctlr->setup = sh_msiof_spi_setup;
1349     ctlr->prepare_message = sh_msiof_prepare_message;
1350     ctlr->slave_abort = sh_msiof_slave_abort;
1351     ctlr->bits_per_word_mask = chipdata->bits_per_word_mask;
1352     ctlr->auto_runtime_pm = true;
1353     ctlr->transfer_one = sh_msiof_transfer_one;
1354     ctlr->use_gpio_descriptors = true;
1355     ctlr->max_native_cs = MAX_SS;
1356 
1357     ret = sh_msiof_request_dma(p);
1358     if (ret < 0)
1359         dev_warn(&pdev->dev, "DMA not available, using PIO\n");
1360 
1361     ret = devm_spi_register_controller(&pdev->dev, ctlr);
1362     if (ret < 0) {
1363         dev_err(&pdev->dev, "devm_spi_register_controller error.\n");
1364         goto err2;
1365     }
1366 
1367     return 0;
1368 
1369  err2:
1370     sh_msiof_release_dma(p);
1371     pm_runtime_disable(&pdev->dev);
1372  err1:
1373     spi_controller_put(ctlr);
1374     return ret;
1375 }
1376 
1377 static int sh_msiof_spi_remove(struct platform_device *pdev)
1378 {
1379     struct sh_msiof_spi_priv *p = platform_get_drvdata(pdev);
1380 
1381     sh_msiof_release_dma(p);
1382     pm_runtime_disable(&pdev->dev);
1383     return 0;
1384 }
1385 
1386 static const struct platform_device_id spi_driver_ids[] = {
1387     { "spi_sh_msiof",   (kernel_ulong_t)&sh_data },
1388     {},
1389 };
1390 MODULE_DEVICE_TABLE(platform, spi_driver_ids);
1391 
1392 #ifdef CONFIG_PM_SLEEP
1393 static int sh_msiof_spi_suspend(struct device *dev)
1394 {
1395     struct sh_msiof_spi_priv *p = dev_get_drvdata(dev);
1396 
1397     return spi_controller_suspend(p->ctlr);
1398 }
1399 
1400 static int sh_msiof_spi_resume(struct device *dev)
1401 {
1402     struct sh_msiof_spi_priv *p = dev_get_drvdata(dev);
1403 
1404     return spi_controller_resume(p->ctlr);
1405 }
1406 
1407 static SIMPLE_DEV_PM_OPS(sh_msiof_spi_pm_ops, sh_msiof_spi_suspend,
1408              sh_msiof_spi_resume);
1409 #define DEV_PM_OPS  (&sh_msiof_spi_pm_ops)
1410 #else
1411 #define DEV_PM_OPS  NULL
1412 #endif /* CONFIG_PM_SLEEP */
1413 
1414 static struct platform_driver sh_msiof_spi_drv = {
1415     .probe      = sh_msiof_spi_probe,
1416     .remove     = sh_msiof_spi_remove,
1417     .id_table   = spi_driver_ids,
1418     .driver     = {
1419         .name       = "spi_sh_msiof",
1420         .pm     = DEV_PM_OPS,
1421         .of_match_table = of_match_ptr(sh_msiof_match),
1422     },
1423 };
1424 module_platform_driver(sh_msiof_spi_drv);
1425 
1426 MODULE_DESCRIPTION("SuperH MSIOF SPI Controller Interface Driver");
1427 MODULE_AUTHOR("Magnus Damm");
1428 MODULE_LICENSE("GPL v2");
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