drivers/spi/spi-s3c24xx.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (c) 2006 Ben Dooks
0004  * Copyright 2006-2009 Simtec Electronics
0005  *  Ben Dooks <ben@simtec.co.uk>
0006 */
0007
0008 #include <linux/spinlock.h>
0009 #include <linux/interrupt.h>
0010 #include <linux/delay.h>
0011 #include <linux/errno.h>
0012 #include <linux/err.h>
0013 #include <linux/clk.h>
0014 #include <linux/platform_device.h>
0015 #include <linux/io.h>
0016 #include <linux/slab.h>
0017
0018 #include <linux/spi/spi.h>
0019 #include <linux/spi/spi_bitbang.h>
0020 #include <linux/spi/s3c24xx.h>
0021 #include <linux/spi/s3c24xx-fiq.h>
0022 #include <linux/module.h>
0023
0024 #include <asm/fiq.h>
0025
0026 #include "spi-s3c24xx-regs.h"
0027
0028 /**
0029  * struct s3c24xx_spi_devstate - per device data
0030  * @hz: Last frequency calculated for @sppre field.
0031  * @mode: Last mode setting for the @spcon field.
0032  * @spcon: Value to write to the SPCON register.
0033  * @sppre: Value to write to the SPPRE register.
0034  */
0035 struct s3c24xx_spi_devstate {
0036     unsigned int    hz;
0037     unsigned int    mode;
0038     u8      spcon;
0039     u8      sppre;
0040 };
0041
0042 enum spi_fiq_mode {
0043     FIQ_MODE_NONE   = 0,
0044     FIQ_MODE_TX = 1,
0045     FIQ_MODE_RX = 2,
0046     FIQ_MODE_TXRX   = 3,
0047 };
0048
0049 struct s3c24xx_spi {
0050     /* bitbang has to be first */
0051     struct spi_bitbang   bitbang;
0052     struct completion    done;
0053
0054     void __iomem        *regs;
0055     int          irq;
0056     int          len;
0057     int          count;
0058
0059     struct fiq_handler   fiq_handler;
0060     enum spi_fiq_mode    fiq_mode;
0061     unsigned char        fiq_inuse;
0062     unsigned char        fiq_claimed;
0063
0064     /* data buffers */
0065     const unsigned char *tx;
0066     unsigned char       *rx;
0067
0068     struct clk      *clk;
0069     struct spi_master   *master;
0070     struct spi_device   *curdev;
0071     struct device       *dev;
0072     struct s3c2410_spi_info *pdata;
0073 };
0074
0075 #define SPCON_DEFAULT (S3C2410_SPCON_MSTR | S3C2410_SPCON_SMOD_INT)
0076 #define SPPIN_DEFAULT (S3C2410_SPPIN_KEEP)
0077
0078 static inline struct s3c24xx_spi *to_hw(struct spi_device *sdev)
0079 {
0080     return spi_master_get_devdata(sdev->master);
0081 }
0082
0083 static void s3c24xx_spi_chipsel(struct spi_device *spi, int value)
0084 {
0085     struct s3c24xx_spi_devstate *cs = spi->controller_state;
0086     struct s3c24xx_spi *hw = to_hw(spi);
0087
0088     /* change the chipselect state and the state of the spi engine clock */
0089
0090     switch (value) {
0091     case BITBANG_CS_INACTIVE:
0092         writeb(cs->spcon, hw->regs + S3C2410_SPCON);
0093         break;
0094
0095     case BITBANG_CS_ACTIVE:
0096         writeb(cs->spcon | S3C2410_SPCON_ENSCK,
0097                hw->regs + S3C2410_SPCON);
0098         break;
0099     }
0100 }
0101
0102 static int s3c24xx_spi_update_state(struct spi_device *spi,
0103                     struct spi_transfer *t)
0104 {
0105     struct s3c24xx_spi *hw = to_hw(spi);
0106     struct s3c24xx_spi_devstate *cs = spi->controller_state;
0107     unsigned int hz;
0108     unsigned int div;
0109     unsigned long clk;
0110
0111     hz  = t ? t->speed_hz : spi->max_speed_hz;
0112
0113     if (!hz)
0114         hz = spi->max_speed_hz;
0115
0116     if (spi->mode != cs->mode) {
0117         u8 spcon = SPCON_DEFAULT | S3C2410_SPCON_ENSCK;
0118
0119         if (spi->mode & SPI_CPHA)
0120             spcon |= S3C2410_SPCON_CPHA_FMTB;
0121
0122         if (spi->mode & SPI_CPOL)
0123             spcon |= S3C2410_SPCON_CPOL_HIGH;
0124
0125         cs->mode = spi->mode;
0126         cs->spcon = spcon;
0127     }
0128
0129     if (cs->hz != hz) {
0130         clk = clk_get_rate(hw->clk);
0131         div = DIV_ROUND_UP(clk, hz * 2) - 1;
0132
0133         if (div > 255)
0134             div = 255;
0135
0136         dev_dbg(&spi->dev, "pre-scaler=%d (wanted %d, got %ld)\n",
0137             div, hz, clk / (2 * (div + 1)));
0138
0139         cs->hz = hz;
0140         cs->sppre = div;
0141     }
0142
0143     return 0;
0144 }
0145
0146 static int s3c24xx_spi_setupxfer(struct spi_device *spi,
0147                  struct spi_transfer *t)
0148 {
0149     struct s3c24xx_spi_devstate *cs = spi->controller_state;
0150     struct s3c24xx_spi *hw = to_hw(spi);
0151     int ret;
0152
0153     ret = s3c24xx_spi_update_state(spi, t);
0154     if (!ret)
0155         writeb(cs->sppre, hw->regs + S3C2410_SPPRE);
0156
0157     return ret;
0158 }
0159
0160 static int s3c24xx_spi_setup(struct spi_device *spi)
0161 {
0162     struct s3c24xx_spi_devstate *cs = spi->controller_state;
0163     struct s3c24xx_spi *hw = to_hw(spi);
0164     int ret;
0165
0166     /* allocate settings on the first call */
0167     if (!cs) {
0168         cs = devm_kzalloc(&spi->dev,
0169                   sizeof(struct s3c24xx_spi_devstate),
0170                   GFP_KERNEL);
0171         if (!cs)
0172             return -ENOMEM;
0173
0174         cs->spcon = SPCON_DEFAULT;
0175         cs->hz = -1;
0176         spi->controller_state = cs;
0177     }
0178
0179     /* initialise the state from the device */
0180     ret = s3c24xx_spi_update_state(spi, NULL);
0181     if (ret)
0182         return ret;
0183
0184     mutex_lock(&hw->bitbang.lock);
0185     if (!hw->bitbang.busy) {
0186         hw->bitbang.chipselect(spi, BITBANG_CS_INACTIVE);
0187         /* need to ndelay for 0.5 clocktick ? */
0188     }
0189     mutex_unlock(&hw->bitbang.lock);
0190
0191     return 0;
0192 }
0193
0194 static inline unsigned int hw_txbyte(struct s3c24xx_spi *hw, int count)
0195 {
0196     return hw->tx ? hw->tx[count] : 0;
0197 }
0198
0199 #ifdef CONFIG_SPI_S3C24XX_FIQ
0200 /* Support for FIQ based pseudo-DMA to improve the transfer speed.
0201  *
0202  * This code uses the assembly helper in spi_s3c24xx_spi.S which is
0203  * used by the FIQ core to move data between main memory and the peripheral
0204  * block. Since this is code running on the processor, there is no problem
0205  * with cache coherency of the buffers, so we can use any buffer we like.
0206  */
0207
0208 /**
0209  * struct spi_fiq_code - FIQ code and header
0210  * @length: The length of the code fragment, excluding this header.
0211  * @ack_offset: The offset from @data to the word to place the IRQ ACK bit at.
0212  * @data: The code itself to install as a FIQ handler.
0213  */
0214 struct spi_fiq_code {
0215     u32 length;
0216     u32 ack_offset;
0217     u8  data[];
0218 };
0219
0220 /**
0221  * s3c24xx_spi_tryfiq - attempt to claim and setup FIQ for transfer
0222  * @hw: The hardware state.
0223  *
0224  * Claim the FIQ handler (only one can be active at any one time) and
0225  * then setup the correct transfer code for this transfer.
0226  *
0227  * This call updates all the necessary state information if successful,
0228  * so the caller does not need to do anything more than start the transfer
0229  * as normal, since the IRQ will have been re-routed to the FIQ handler.
0230 */
0231 static void s3c24xx_spi_tryfiq(struct s3c24xx_spi *hw)
0232 {
0233     struct pt_regs regs;
0234     enum spi_fiq_mode mode;
0235     struct spi_fiq_code *code;
0236     u32 *ack_ptr = NULL;
0237     int ret;
0238
0239     if (!hw->fiq_claimed) {
0240         /* try and claim fiq if we haven't got it, and if not
0241          * then return and simply use another transfer method */
0242
0243         ret = claim_fiq(&hw->fiq_handler);
0244         if (ret)
0245             return;
0246     }
0247
0248     if (hw->tx && !hw->rx)
0249         mode = FIQ_MODE_TX;
0250     else if (hw->rx && !hw->tx)
0251         mode = FIQ_MODE_RX;
0252     else
0253         mode = FIQ_MODE_TXRX;
0254
0255     regs.uregs[fiq_rspi] = (long)hw->regs;
0256     regs.uregs[fiq_rrx]  = (long)hw->rx;
0257     regs.uregs[fiq_rtx]  = (long)hw->tx + 1;
0258     regs.uregs[fiq_rcount] = hw->len - 1;
0259
0260     set_fiq_regs(&regs);
0261
0262     if (hw->fiq_mode != mode) {
0263         hw->fiq_mode = mode;
0264
0265         switch (mode) {
0266         case FIQ_MODE_TX:
0267             code = &s3c24xx_spi_fiq_tx;
0268             break;
0269         case FIQ_MODE_RX:
0270             code = &s3c24xx_spi_fiq_rx;
0271             break;
0272         case FIQ_MODE_TXRX:
0273             code = &s3c24xx_spi_fiq_txrx;
0274             break;
0275         default:
0276             code = NULL;
0277         }
0278
0279         BUG_ON(!code);
0280
0281         ack_ptr = (u32 *)&code->data[code->ack_offset];
0282         set_fiq_handler(&code->data, code->length);
0283     }
0284
0285     s3c24xx_set_fiq(hw->irq, ack_ptr, true);
0286
0287     hw->fiq_mode = mode;
0288     hw->fiq_inuse = 1;
0289 }
0290
0291 /**
0292  * s3c24xx_spi_fiqop - FIQ core code callback
0293  * @pw: Data registered with the handler
0294  * @release: Whether this is a release or a return.
0295  *
0296  * Called by the FIQ code when another module wants to use the FIQ, so
0297  * return whether we are currently using this or not and then update our
0298  * internal state.
0299  */
0300 static int s3c24xx_spi_fiqop(void *pw, int release)
0301 {
0302     struct s3c24xx_spi *hw = pw;
0303     int ret = 0;
0304
0305     if (release) {
0306         if (hw->fiq_inuse)
0307             ret = -EBUSY;
0308
0309         /* note, we do not need to unroute the FIQ, as the FIQ
0310          * vector code de-routes it to signal the end of transfer */
0311
0312         hw->fiq_mode = FIQ_MODE_NONE;
0313         hw->fiq_claimed = 0;
0314     } else {
0315         hw->fiq_claimed = 1;
0316     }
0317
0318     return ret;
0319 }
0320
0321 /**
0322  * s3c24xx_spi_initfiq - setup the information for the FIQ core
0323  * @hw: The hardware state.
0324  *
0325  * Setup the fiq_handler block to pass to the FIQ core.
0326  */
0327 static inline void s3c24xx_spi_initfiq(struct s3c24xx_spi *hw)
0328 {
0329     hw->fiq_handler.dev_id = hw;
0330     hw->fiq_handler.name = dev_name(hw->dev);
0331     hw->fiq_handler.fiq_op = s3c24xx_spi_fiqop;
0332 }
0333
0334 /**
0335  * s3c24xx_spi_usefiq - return if we should be using FIQ.
0336  * @hw: The hardware state.
0337  *
0338  * Return true if the platform data specifies whether this channel is
0339  * allowed to use the FIQ.
0340  */
0341 static inline bool s3c24xx_spi_usefiq(struct s3c24xx_spi *hw)
0342 {
0343     return hw->pdata->use_fiq;
0344 }
0345
0346 /**
0347  * s3c24xx_spi_usingfiq - return if channel is using FIQ
0348  * @spi: The hardware state.
0349  *
0350  * Return whether the channel is currently using the FIQ (separate from
0351  * whether the FIQ is claimed).
0352  */
0353 static inline bool s3c24xx_spi_usingfiq(struct s3c24xx_spi *spi)
0354 {
0355     return spi->fiq_inuse;
0356 }
0357 #else
0358
0359 static inline void s3c24xx_spi_initfiq(struct s3c24xx_spi *s) { }
0360 static inline void s3c24xx_spi_tryfiq(struct s3c24xx_spi *s) { }
0361 static inline bool s3c24xx_spi_usefiq(struct s3c24xx_spi *s) { return false; }
0362 static inline bool s3c24xx_spi_usingfiq(struct s3c24xx_spi *s) { return false; }
0363
0364 #endif /* CONFIG_SPI_S3C24XX_FIQ */
0365
0366 static int s3c24xx_spi_txrx(struct spi_device *spi, struct spi_transfer *t)
0367 {
0368     struct s3c24xx_spi *hw = to_hw(spi);
0369
0370     hw->tx = t->tx_buf;
0371     hw->rx = t->rx_buf;
0372     hw->len = t->len;
0373     hw->count = 0;
0374
0375     init_completion(&hw->done);
0376
0377     hw->fiq_inuse = 0;
0378     if (s3c24xx_spi_usefiq(hw) && t->len >= 3)
0379         s3c24xx_spi_tryfiq(hw);
0380
0381     /* send the first byte */
0382     writeb(hw_txbyte(hw, 0), hw->regs + S3C2410_SPTDAT);
0383
0384     wait_for_completion(&hw->done);
0385     return hw->count;
0386 }
0387
0388 static irqreturn_t s3c24xx_spi_irq(int irq, void *dev)
0389 {
0390     struct s3c24xx_spi *hw = dev;
0391     unsigned int spsta = readb(hw->regs + S3C2410_SPSTA);
0392     unsigned int count = hw->count;
0393
0394     if (spsta & S3C2410_SPSTA_DCOL) {
0395         dev_dbg(hw->dev, "data-collision\n");
0396         complete(&hw->done);
0397         goto irq_done;
0398     }
0399
0400     if (!(spsta & S3C2410_SPSTA_READY)) {
0401         dev_dbg(hw->dev, "spi not ready for tx?\n");
0402         complete(&hw->done);
0403         goto irq_done;
0404     }
0405
0406     if (!s3c24xx_spi_usingfiq(hw)) {
0407         hw->count++;
0408
0409         if (hw->rx)
0410             hw->rx[count] = readb(hw->regs + S3C2410_SPRDAT);
0411
0412         count++;
0413
0414         if (count < hw->len)
0415             writeb(hw_txbyte(hw, count), hw->regs + S3C2410_SPTDAT);
0416         else
0417             complete(&hw->done);
0418     } else {
0419         hw->count = hw->len;
0420         hw->fiq_inuse = 0;
0421
0422         if (hw->rx)
0423             hw->rx[hw->len-1] = readb(hw->regs + S3C2410_SPRDAT);
0424
0425         complete(&hw->done);
0426     }
0427
0428  irq_done:
0429     return IRQ_HANDLED;
0430 }
0431
0432 static void s3c24xx_spi_initialsetup(struct s3c24xx_spi *hw)
0433 {
0434     /* for the moment, permanently enable the clock */
0435
0436     clk_enable(hw->clk);
0437
0438     /* program defaults into the registers */
0439
0440     writeb(0xff, hw->regs + S3C2410_SPPRE);
0441     writeb(SPPIN_DEFAULT, hw->regs + S3C2410_SPPIN);
0442     writeb(SPCON_DEFAULT, hw->regs + S3C2410_SPCON);
0443 }
0444
0445 static int s3c24xx_spi_probe(struct platform_device *pdev)
0446 {
0447     struct s3c2410_spi_info *pdata;
0448     struct s3c24xx_spi *hw;
0449     struct spi_master *master;
0450     int err = 0;
0451
0452     master = spi_alloc_master(&pdev->dev, sizeof(struct s3c24xx_spi));
0453     if (master == NULL) {
0454         dev_err(&pdev->dev, "No memory for spi_master\n");
0455         return -ENOMEM;
0456     }
0457
0458     hw = spi_master_get_devdata(master);
0459
0460     hw->master = master;
0461     hw->pdata = pdata = dev_get_platdata(&pdev->dev);
0462     hw->dev = &pdev->dev;
0463
0464     if (pdata == NULL) {
0465         dev_err(&pdev->dev, "No platform data supplied\n");
0466         err = -ENOENT;
0467         goto err_no_pdata;
0468     }
0469
0470     platform_set_drvdata(pdev, hw);
0471     init_completion(&hw->done);
0472
0473     /* initialise fiq handler */
0474
0475     s3c24xx_spi_initfiq(hw);
0476
0477     /* setup the master state. */
0478
0479     /* the spi->mode bits understood by this driver: */
0480     master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
0481
0482     master->num_chipselect = hw->pdata->num_cs;
0483     master->bus_num = pdata->bus_num;
0484     master->bits_per_word_mask = SPI_BPW_MASK(8);
0485     /* we need to call the local chipselect callback */
0486     master->flags = SPI_MASTER_GPIO_SS;
0487     master->use_gpio_descriptors = true;
0488
0489     /* setup the state for the bitbang driver */
0490
0491     hw->bitbang.master         = hw->master;
0492     hw->bitbang.setup_transfer = s3c24xx_spi_setupxfer;
0493     hw->bitbang.chipselect     = s3c24xx_spi_chipsel;
0494     hw->bitbang.txrx_bufs      = s3c24xx_spi_txrx;
0495
0496     hw->master->setup  = s3c24xx_spi_setup;
0497
0498     dev_dbg(hw->dev, "bitbang at %p\n", &hw->bitbang);
0499
0500     /* find and map our resources */
0501     hw->regs = devm_platform_ioremap_resource(pdev, 0);
0502     if (IS_ERR(hw->regs)) {
0503         err = PTR_ERR(hw->regs);
0504         goto err_no_pdata;
0505     }
0506
0507     hw->irq = platform_get_irq(pdev, 0);
0508     if (hw->irq < 0) {
0509         err = -ENOENT;
0510         goto err_no_pdata;
0511     }
0512
0513     err = devm_request_irq(&pdev->dev, hw->irq, s3c24xx_spi_irq, 0,
0514                 pdev->name, hw);
0515     if (err) {
0516         dev_err(&pdev->dev, "Cannot claim IRQ\n");
0517         goto err_no_pdata;
0518     }
0519
0520     hw->clk = devm_clk_get(&pdev->dev, "spi");
0521     if (IS_ERR(hw->clk)) {
0522         dev_err(&pdev->dev, "No clock for device\n");
0523         err = PTR_ERR(hw->clk);
0524         goto err_no_pdata;
0525     }
0526
0527     s3c24xx_spi_initialsetup(hw);
0528
0529     /* register our spi controller */
0530
0531     err = spi_bitbang_start(&hw->bitbang);
0532     if (err) {
0533         dev_err(&pdev->dev, "Failed to register SPI master\n");
0534         goto err_register;
0535     }
0536
0537     return 0;
0538
0539  err_register:
0540     clk_disable(hw->clk);
0541
0542  err_no_pdata:
0543     spi_master_put(hw->master);
0544     return err;
0545 }
0546
0547 static int s3c24xx_spi_remove(struct platform_device *dev)
0548 {
0549     struct s3c24xx_spi *hw = platform_get_drvdata(dev);
0550
0551     spi_bitbang_stop(&hw->bitbang);
0552     clk_disable(hw->clk);
0553     spi_master_put(hw->master);
0554     return 0;
0555 }
0556
0557
0558 #ifdef CONFIG_PM
0559
0560 static int s3c24xx_spi_suspend(struct device *dev)
0561 {
0562     struct s3c24xx_spi *hw = dev_get_drvdata(dev);
0563     int ret;
0564
0565     ret = spi_master_suspend(hw->master);
0566     if (ret)
0567         return ret;
0568
0569     clk_disable(hw->clk);
0570     return 0;
0571 }
0572
0573 static int s3c24xx_spi_resume(struct device *dev)
0574 {
0575     struct s3c24xx_spi *hw = dev_get_drvdata(dev);
0576
0577     s3c24xx_spi_initialsetup(hw);
0578     return spi_master_resume(hw->master);
0579 }
0580
0581 static const struct dev_pm_ops s3c24xx_spi_pmops = {
0582     .suspend    = s3c24xx_spi_suspend,
0583     .resume     = s3c24xx_spi_resume,
0584 };
0585
0586 #define S3C24XX_SPI_PMOPS &s3c24xx_spi_pmops
0587 #else
0588 #define S3C24XX_SPI_PMOPS NULL
0589 #endif /* CONFIG_PM */
0590
0591 MODULE_ALIAS("platform:s3c2410-spi");
0592 static struct platform_driver s3c24xx_spi_driver = {
0593     .probe      = s3c24xx_spi_probe,
0594     .remove     = s3c24xx_spi_remove,
0595     .driver     = {
0596         .name   = "s3c2410-spi",
0597         .pm = S3C24XX_SPI_PMOPS,
0598     },
0599 };
0600 module_platform_driver(s3c24xx_spi_driver);
0601
0602 MODULE_DESCRIPTION("S3C24XX SPI Driver");
0603 MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>");
0604 MODULE_LICENSE("GPL");