drivers/spi/spi-s3c24xx-regs.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * Copyright (c) 2004 Fetron GmbH
0004  *
0005  * S3C2410 SPI register definition
0006  */
0007
0008 #ifndef __SPI_S3C2410_H
0009 #define __SPI_S3C2410_H
0010
0011 #define S3C2410_SPCON       (0x00)
0012
0013 #define S3C2410_SPCON_SMOD_DMA  (2 << 5)    /* DMA mode */
0014 #define S3C2410_SPCON_SMOD_INT  (1 << 5)    /* interrupt mode */
0015 #define S3C2410_SPCON_SMOD_POLL (0 << 5)    /* polling mode */
0016 #define S3C2410_SPCON_ENSCK (1 << 4)    /* Enable SCK */
0017 #define S3C2410_SPCON_MSTR  (1 << 3)    /* Master:1, Slave:0 select */
0018 #define S3C2410_SPCON_CPOL_HIGH (1 << 2)    /* Clock polarity select */
0019 #define S3C2410_SPCON_CPOL_LOW  (0 << 2)    /* Clock polarity select */
0020
0021 #define S3C2410_SPCON_CPHA_FMTB (1 << 1)    /* Clock Phase Select */
0022 #define S3C2410_SPCON_CPHA_FMTA (0 << 1)    /* Clock Phase Select */
0023
0024 #define S3C2410_SPSTA       (0x04)
0025
0026 #define S3C2410_SPSTA_DCOL  (1 << 2)    /* Data Collision Error */
0027 #define S3C2410_SPSTA_MULD  (1 << 1)    /* Multi Master Error */
0028 #define S3C2410_SPSTA_READY (1 << 0)    /* Data Tx/Rx ready */
0029 #define S3C2412_SPSTA_READY_ORG (1 << 3)
0030
0031 #define S3C2410_SPPIN       (0x08)
0032
0033 #define S3C2410_SPPIN_ENMUL (1 << 2)    /* Multi Master Error detect */
0034 #define S3C2410_SPPIN_RESERVED  (1 << 1)
0035 #define S3C2410_SPPIN_KEEP  (1 << 0)    /* Master Out keep */
0036
0037 #define S3C2410_SPPRE       (0x0C)
0038 #define S3C2410_SPTDAT      (0x10)
0039 #define S3C2410_SPRDAT      (0x14)
0040
0041 #endif /* __SPI_S3C2410_H */