Back to home page

OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd
0004  * Author: Addy Ke <addy.ke@rock-chips.com>
0005  */
0006 
0007 #include <linux/clk.h>
0008 #include <linux/dmaengine.h>
0009 #include <linux/interrupt.h>
0010 #include <linux/module.h>
0011 #include <linux/of.h>
0012 #include <linux/pinctrl/consumer.h>
0013 #include <linux/platform_device.h>
0014 #include <linux/spi/spi.h>
0015 #include <linux/pm_runtime.h>
0016 #include <linux/scatterlist.h>
0017 
0018 #define DRIVER_NAME "rockchip-spi"
0019 
0020 #define ROCKCHIP_SPI_CLR_BITS(reg, bits) \
0021         writel_relaxed(readl_relaxed(reg) & ~(bits), reg)
0022 #define ROCKCHIP_SPI_SET_BITS(reg, bits) \
0023         writel_relaxed(readl_relaxed(reg) | (bits), reg)
0024 
0025 /* SPI register offsets */
0026 #define ROCKCHIP_SPI_CTRLR0         0x0000
0027 #define ROCKCHIP_SPI_CTRLR1         0x0004
0028 #define ROCKCHIP_SPI_SSIENR         0x0008
0029 #define ROCKCHIP_SPI_SER            0x000c
0030 #define ROCKCHIP_SPI_BAUDR          0x0010
0031 #define ROCKCHIP_SPI_TXFTLR         0x0014
0032 #define ROCKCHIP_SPI_RXFTLR         0x0018
0033 #define ROCKCHIP_SPI_TXFLR          0x001c
0034 #define ROCKCHIP_SPI_RXFLR          0x0020
0035 #define ROCKCHIP_SPI_SR             0x0024
0036 #define ROCKCHIP_SPI_IPR            0x0028
0037 #define ROCKCHIP_SPI_IMR            0x002c
0038 #define ROCKCHIP_SPI_ISR            0x0030
0039 #define ROCKCHIP_SPI_RISR           0x0034
0040 #define ROCKCHIP_SPI_ICR            0x0038
0041 #define ROCKCHIP_SPI_DMACR          0x003c
0042 #define ROCKCHIP_SPI_DMATDLR            0x0040
0043 #define ROCKCHIP_SPI_DMARDLR            0x0044
0044 #define ROCKCHIP_SPI_VERSION            0x0048
0045 #define ROCKCHIP_SPI_TXDR           0x0400
0046 #define ROCKCHIP_SPI_RXDR           0x0800
0047 
0048 /* Bit fields in CTRLR0 */
0049 #define CR0_DFS_OFFSET              0
0050 #define CR0_DFS_4BIT                0x0
0051 #define CR0_DFS_8BIT                0x1
0052 #define CR0_DFS_16BIT               0x2
0053 
0054 #define CR0_CFS_OFFSET              2
0055 
0056 #define CR0_SCPH_OFFSET             6
0057 
0058 #define CR0_SCPOL_OFFSET            7
0059 
0060 #define CR0_CSM_OFFSET              8
0061 #define CR0_CSM_KEEP                0x0
0062 /* ss_n be high for half sclk_out cycles */
0063 #define CR0_CSM_HALF                0X1
0064 /* ss_n be high for one sclk_out cycle */
0065 #define CR0_CSM_ONE                 0x2
0066 
0067 /* ss_n to sclk_out delay */
0068 #define CR0_SSD_OFFSET              10
0069 /*
0070  * The period between ss_n active and
0071  * sclk_out active is half sclk_out cycles
0072  */
0073 #define CR0_SSD_HALF                0x0
0074 /*
0075  * The period between ss_n active and
0076  * sclk_out active is one sclk_out cycle
0077  */
0078 #define CR0_SSD_ONE                 0x1
0079 
0080 #define CR0_EM_OFFSET               11
0081 #define CR0_EM_LITTLE               0x0
0082 #define CR0_EM_BIG                  0x1
0083 
0084 #define CR0_FBM_OFFSET              12
0085 #define CR0_FBM_MSB                 0x0
0086 #define CR0_FBM_LSB                 0x1
0087 
0088 #define CR0_BHT_OFFSET              13
0089 #define CR0_BHT_16BIT               0x0
0090 #define CR0_BHT_8BIT                0x1
0091 
0092 #define CR0_RSD_OFFSET              14
0093 #define CR0_RSD_MAX             0x3
0094 
0095 #define CR0_FRF_OFFSET              16
0096 #define CR0_FRF_SPI                 0x0
0097 #define CR0_FRF_SSP                 0x1
0098 #define CR0_FRF_MICROWIRE           0x2
0099 
0100 #define CR0_XFM_OFFSET              18
0101 #define CR0_XFM_MASK                (0x03 << SPI_XFM_OFFSET)
0102 #define CR0_XFM_TR                  0x0
0103 #define CR0_XFM_TO                  0x1
0104 #define CR0_XFM_RO                  0x2
0105 
0106 #define CR0_OPM_OFFSET              20
0107 #define CR0_OPM_MASTER              0x0
0108 #define CR0_OPM_SLAVE               0x1
0109 
0110 #define CR0_SOI_OFFSET              23
0111 
0112 #define CR0_MTM_OFFSET              0x21
0113 
0114 /* Bit fields in SER, 2bit */
0115 #define SER_MASK                    0x3
0116 
0117 /* Bit fields in BAUDR */
0118 #define BAUDR_SCKDV_MIN             2
0119 #define BAUDR_SCKDV_MAX             65534
0120 
0121 /* Bit fields in SR, 6bit */
0122 #define SR_MASK                     0x3f
0123 #define SR_BUSY                     (1 << 0)
0124 #define SR_TF_FULL                  (1 << 1)
0125 #define SR_TF_EMPTY                 (1 << 2)
0126 #define SR_RF_EMPTY                 (1 << 3)
0127 #define SR_RF_FULL                  (1 << 4)
0128 #define SR_SLAVE_TX_BUSY                (1 << 5)
0129 
0130 /* Bit fields in ISR, IMR, ISR, RISR, 5bit */
0131 #define INT_MASK                    0x1f
0132 #define INT_TF_EMPTY                (1 << 0)
0133 #define INT_TF_OVERFLOW             (1 << 1)
0134 #define INT_RF_UNDERFLOW            (1 << 2)
0135 #define INT_RF_OVERFLOW             (1 << 3)
0136 #define INT_RF_FULL             (1 << 4)
0137 #define INT_CS_INACTIVE             (1 << 6)
0138 
0139 /* Bit fields in ICR, 4bit */
0140 #define ICR_MASK                    0x0f
0141 #define ICR_ALL                     (1 << 0)
0142 #define ICR_RF_UNDERFLOW            (1 << 1)
0143 #define ICR_RF_OVERFLOW             (1 << 2)
0144 #define ICR_TF_OVERFLOW             (1 << 3)
0145 
0146 /* Bit fields in DMACR */
0147 #define RF_DMA_EN                   (1 << 0)
0148 #define TF_DMA_EN                   (1 << 1)
0149 
0150 /* Driver state flags */
0151 #define RXDMA                   (1 << 0)
0152 #define TXDMA                   (1 << 1)
0153 
0154 /* sclk_out: spi master internal logic in rk3x can support 50Mhz */
0155 #define MAX_SCLK_OUT                50000000U
0156 
0157 /*
0158  * SPI_CTRLR1 is 16-bits, so we should support lengths of 0xffff + 1. However,
0159  * the controller seems to hang when given 0x10000, so stick with this for now.
0160  */
0161 #define ROCKCHIP_SPI_MAX_TRANLEN        0xffff
0162 
0163 /* 2 for native cs, 2 for cs-gpio */
0164 #define ROCKCHIP_SPI_MAX_CS_NUM         4
0165 #define ROCKCHIP_SPI_VER2_TYPE1         0x05EC0002
0166 #define ROCKCHIP_SPI_VER2_TYPE2         0x00110002
0167 
0168 #define ROCKCHIP_AUTOSUSPEND_TIMEOUT        2000
0169 
0170 struct rockchip_spi {
0171     struct device *dev;
0172 
0173     struct clk *spiclk;
0174     struct clk *apb_pclk;
0175 
0176     void __iomem *regs;
0177     dma_addr_t dma_addr_rx;
0178     dma_addr_t dma_addr_tx;
0179 
0180     const void *tx;
0181     void *rx;
0182     unsigned int tx_left;
0183     unsigned int rx_left;
0184 
0185     atomic_t state;
0186 
0187     /*depth of the FIFO buffer */
0188     u32 fifo_len;
0189     /* frequency of spiclk */
0190     u32 freq;
0191 
0192     u8 n_bytes;
0193     u8 rsd;
0194 
0195     bool cs_asserted[ROCKCHIP_SPI_MAX_CS_NUM];
0196 
0197     bool slave_abort;
0198     bool cs_inactive; /* spi slave tansmition stop when cs inactive */
0199     bool cs_high_supported; /* native CS supports active-high polarity */
0200 
0201     struct spi_transfer *xfer; /* Store xfer temporarily */
0202 };
0203 
0204 static inline void spi_enable_chip(struct rockchip_spi *rs, bool enable)
0205 {
0206     writel_relaxed((enable ? 1U : 0U), rs->regs + ROCKCHIP_SPI_SSIENR);
0207 }
0208 
0209 static inline void wait_for_tx_idle(struct rockchip_spi *rs, bool slave_mode)
0210 {
0211     unsigned long timeout = jiffies + msecs_to_jiffies(5);
0212 
0213     do {
0214         if (slave_mode) {
0215             if (!(readl_relaxed(rs->regs + ROCKCHIP_SPI_SR) & SR_SLAVE_TX_BUSY) &&
0216                 !((readl_relaxed(rs->regs + ROCKCHIP_SPI_SR) & SR_BUSY)))
0217                 return;
0218         } else {
0219             if (!(readl_relaxed(rs->regs + ROCKCHIP_SPI_SR) & SR_BUSY))
0220                 return;
0221         }
0222     } while (!time_after(jiffies, timeout));
0223 
0224     dev_warn(rs->dev, "spi controller is in busy state!\n");
0225 }
0226 
0227 static u32 get_fifo_len(struct rockchip_spi *rs)
0228 {
0229     u32 ver;
0230 
0231     ver = readl_relaxed(rs->regs + ROCKCHIP_SPI_VERSION);
0232 
0233     switch (ver) {
0234     case ROCKCHIP_SPI_VER2_TYPE1:
0235     case ROCKCHIP_SPI_VER2_TYPE2:
0236         return 64;
0237     default:
0238         return 32;
0239     }
0240 }
0241 
0242 static void rockchip_spi_set_cs(struct spi_device *spi, bool enable)
0243 {
0244     struct spi_controller *ctlr = spi->controller;
0245     struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
0246     bool cs_asserted = spi->mode & SPI_CS_HIGH ? enable : !enable;
0247 
0248     /* Return immediately for no-op */
0249     if (cs_asserted == rs->cs_asserted[spi->chip_select])
0250         return;
0251 
0252     if (cs_asserted) {
0253         /* Keep things powered as long as CS is asserted */
0254         pm_runtime_get_sync(rs->dev);
0255 
0256         if (spi->cs_gpiod)
0257             ROCKCHIP_SPI_SET_BITS(rs->regs + ROCKCHIP_SPI_SER, 1);
0258         else
0259             ROCKCHIP_SPI_SET_BITS(rs->regs + ROCKCHIP_SPI_SER, BIT(spi->chip_select));
0260     } else {
0261         if (spi->cs_gpiod)
0262             ROCKCHIP_SPI_CLR_BITS(rs->regs + ROCKCHIP_SPI_SER, 1);
0263         else
0264             ROCKCHIP_SPI_CLR_BITS(rs->regs + ROCKCHIP_SPI_SER, BIT(spi->chip_select));
0265 
0266         /* Drop reference from when we first asserted CS */
0267         pm_runtime_put(rs->dev);
0268     }
0269 
0270     rs->cs_asserted[spi->chip_select] = cs_asserted;
0271 }
0272 
0273 static void rockchip_spi_handle_err(struct spi_controller *ctlr,
0274                     struct spi_message *msg)
0275 {
0276     struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
0277 
0278     /* stop running spi transfer
0279      * this also flushes both rx and tx fifos
0280      */
0281     spi_enable_chip(rs, false);
0282 
0283     /* make sure all interrupts are masked and status cleared */
0284     writel_relaxed(0, rs->regs + ROCKCHIP_SPI_IMR);
0285     writel_relaxed(0xffffffff, rs->regs + ROCKCHIP_SPI_ICR);
0286 
0287     if (atomic_read(&rs->state) & TXDMA)
0288         dmaengine_terminate_async(ctlr->dma_tx);
0289 
0290     if (atomic_read(&rs->state) & RXDMA)
0291         dmaengine_terminate_async(ctlr->dma_rx);
0292 }
0293 
0294 static void rockchip_spi_pio_writer(struct rockchip_spi *rs)
0295 {
0296     u32 tx_free = rs->fifo_len - readl_relaxed(rs->regs + ROCKCHIP_SPI_TXFLR);
0297     u32 words = min(rs->tx_left, tx_free);
0298 
0299     rs->tx_left -= words;
0300     for (; words; words--) {
0301         u32 txw;
0302 
0303         if (rs->n_bytes == 1)
0304             txw = *(u8 *)rs->tx;
0305         else
0306             txw = *(u16 *)rs->tx;
0307 
0308         writel_relaxed(txw, rs->regs + ROCKCHIP_SPI_TXDR);
0309         rs->tx += rs->n_bytes;
0310     }
0311 }
0312 
0313 static void rockchip_spi_pio_reader(struct rockchip_spi *rs)
0314 {
0315     u32 words = readl_relaxed(rs->regs + ROCKCHIP_SPI_RXFLR);
0316     u32 rx_left = (rs->rx_left > words) ? rs->rx_left - words : 0;
0317 
0318     /* the hardware doesn't allow us to change fifo threshold
0319      * level while spi is enabled, so instead make sure to leave
0320      * enough words in the rx fifo to get the last interrupt
0321      * exactly when all words have been received
0322      */
0323     if (rx_left) {
0324         u32 ftl = readl_relaxed(rs->regs + ROCKCHIP_SPI_RXFTLR) + 1;
0325 
0326         if (rx_left < ftl) {
0327             rx_left = ftl;
0328             words = rs->rx_left - rx_left;
0329         }
0330     }
0331 
0332     rs->rx_left = rx_left;
0333     for (; words; words--) {
0334         u32 rxw = readl_relaxed(rs->regs + ROCKCHIP_SPI_RXDR);
0335 
0336         if (!rs->rx)
0337             continue;
0338 
0339         if (rs->n_bytes == 1)
0340             *(u8 *)rs->rx = (u8)rxw;
0341         else
0342             *(u16 *)rs->rx = (u16)rxw;
0343         rs->rx += rs->n_bytes;
0344     }
0345 }
0346 
0347 static irqreturn_t rockchip_spi_isr(int irq, void *dev_id)
0348 {
0349     struct spi_controller *ctlr = dev_id;
0350     struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
0351 
0352     /* When int_cs_inactive comes, spi slave abort */
0353     if (rs->cs_inactive && readl_relaxed(rs->regs + ROCKCHIP_SPI_IMR) & INT_CS_INACTIVE) {
0354         ctlr->slave_abort(ctlr);
0355         writel_relaxed(0, rs->regs + ROCKCHIP_SPI_IMR);
0356         writel_relaxed(0xffffffff, rs->regs + ROCKCHIP_SPI_ICR);
0357 
0358         return IRQ_HANDLED;
0359     }
0360 
0361     if (rs->tx_left)
0362         rockchip_spi_pio_writer(rs);
0363 
0364     rockchip_spi_pio_reader(rs);
0365     if (!rs->rx_left) {
0366         spi_enable_chip(rs, false);
0367         writel_relaxed(0, rs->regs + ROCKCHIP_SPI_IMR);
0368         writel_relaxed(0xffffffff, rs->regs + ROCKCHIP_SPI_ICR);
0369         spi_finalize_current_transfer(ctlr);
0370     }
0371 
0372     return IRQ_HANDLED;
0373 }
0374 
0375 static int rockchip_spi_prepare_irq(struct rockchip_spi *rs,
0376                     struct spi_controller *ctlr,
0377                     struct spi_transfer *xfer)
0378 {
0379     rs->tx = xfer->tx_buf;
0380     rs->rx = xfer->rx_buf;
0381     rs->tx_left = rs->tx ? xfer->len / rs->n_bytes : 0;
0382     rs->rx_left = xfer->len / rs->n_bytes;
0383 
0384     writel_relaxed(0xffffffff, rs->regs + ROCKCHIP_SPI_ICR);
0385 
0386     spi_enable_chip(rs, true);
0387 
0388     if (rs->tx_left)
0389         rockchip_spi_pio_writer(rs);
0390 
0391     if (rs->cs_inactive)
0392         writel_relaxed(INT_RF_FULL | INT_CS_INACTIVE, rs->regs + ROCKCHIP_SPI_IMR);
0393     else
0394         writel_relaxed(INT_RF_FULL, rs->regs + ROCKCHIP_SPI_IMR);
0395 
0396     /* 1 means the transfer is in progress */
0397     return 1;
0398 }
0399 
0400 static void rockchip_spi_dma_rxcb(void *data)
0401 {
0402     struct spi_controller *ctlr = data;
0403     struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
0404     int state = atomic_fetch_andnot(RXDMA, &rs->state);
0405 
0406     if (state & TXDMA && !rs->slave_abort)
0407         return;
0408 
0409     if (rs->cs_inactive)
0410         writel_relaxed(0, rs->regs + ROCKCHIP_SPI_IMR);
0411 
0412     spi_enable_chip(rs, false);
0413     spi_finalize_current_transfer(ctlr);
0414 }
0415 
0416 static void rockchip_spi_dma_txcb(void *data)
0417 {
0418     struct spi_controller *ctlr = data;
0419     struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
0420     int state = atomic_fetch_andnot(TXDMA, &rs->state);
0421 
0422     if (state & RXDMA && !rs->slave_abort)
0423         return;
0424 
0425     /* Wait until the FIFO data completely. */
0426     wait_for_tx_idle(rs, ctlr->slave);
0427 
0428     spi_enable_chip(rs, false);
0429     spi_finalize_current_transfer(ctlr);
0430 }
0431 
0432 static u32 rockchip_spi_calc_burst_size(u32 data_len)
0433 {
0434     u32 i;
0435 
0436     /* burst size: 1, 2, 4, 8 */
0437     for (i = 1; i < 8; i <<= 1) {
0438         if (data_len & i)
0439             break;
0440     }
0441 
0442     return i;
0443 }
0444 
0445 static int rockchip_spi_prepare_dma(struct rockchip_spi *rs,
0446         struct spi_controller *ctlr, struct spi_transfer *xfer)
0447 {
0448     struct dma_async_tx_descriptor *rxdesc, *txdesc;
0449 
0450     atomic_set(&rs->state, 0);
0451 
0452     rs->tx = xfer->tx_buf;
0453     rs->rx = xfer->rx_buf;
0454 
0455     rxdesc = NULL;
0456     if (xfer->rx_buf) {
0457         struct dma_slave_config rxconf = {
0458             .direction = DMA_DEV_TO_MEM,
0459             .src_addr = rs->dma_addr_rx,
0460             .src_addr_width = rs->n_bytes,
0461             .src_maxburst = rockchip_spi_calc_burst_size(xfer->len / rs->n_bytes),
0462         };
0463 
0464         dmaengine_slave_config(ctlr->dma_rx, &rxconf);
0465 
0466         rxdesc = dmaengine_prep_slave_sg(
0467                 ctlr->dma_rx,
0468                 xfer->rx_sg.sgl, xfer->rx_sg.nents,
0469                 DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT);
0470         if (!rxdesc)
0471             return -EINVAL;
0472 
0473         rxdesc->callback = rockchip_spi_dma_rxcb;
0474         rxdesc->callback_param = ctlr;
0475     }
0476 
0477     txdesc = NULL;
0478     if (xfer->tx_buf) {
0479         struct dma_slave_config txconf = {
0480             .direction = DMA_MEM_TO_DEV,
0481             .dst_addr = rs->dma_addr_tx,
0482             .dst_addr_width = rs->n_bytes,
0483             .dst_maxburst = rs->fifo_len / 4,
0484         };
0485 
0486         dmaengine_slave_config(ctlr->dma_tx, &txconf);
0487 
0488         txdesc = dmaengine_prep_slave_sg(
0489                 ctlr->dma_tx,
0490                 xfer->tx_sg.sgl, xfer->tx_sg.nents,
0491                 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
0492         if (!txdesc) {
0493             if (rxdesc)
0494                 dmaengine_terminate_sync(ctlr->dma_rx);
0495             return -EINVAL;
0496         }
0497 
0498         txdesc->callback = rockchip_spi_dma_txcb;
0499         txdesc->callback_param = ctlr;
0500     }
0501 
0502     /* rx must be started before tx due to spi instinct */
0503     if (rxdesc) {
0504         atomic_or(RXDMA, &rs->state);
0505         ctlr->dma_rx->cookie = dmaengine_submit(rxdesc);
0506         dma_async_issue_pending(ctlr->dma_rx);
0507     }
0508 
0509     if (rs->cs_inactive)
0510         writel_relaxed(INT_CS_INACTIVE, rs->regs + ROCKCHIP_SPI_IMR);
0511 
0512     spi_enable_chip(rs, true);
0513 
0514     if (txdesc) {
0515         atomic_or(TXDMA, &rs->state);
0516         dmaengine_submit(txdesc);
0517         dma_async_issue_pending(ctlr->dma_tx);
0518     }
0519 
0520     /* 1 means the transfer is in progress */
0521     return 1;
0522 }
0523 
0524 static int rockchip_spi_config(struct rockchip_spi *rs,
0525         struct spi_device *spi, struct spi_transfer *xfer,
0526         bool use_dma, bool slave_mode)
0527 {
0528     u32 cr0 = CR0_FRF_SPI  << CR0_FRF_OFFSET
0529         | CR0_BHT_8BIT << CR0_BHT_OFFSET
0530         | CR0_SSD_ONE  << CR0_SSD_OFFSET
0531         | CR0_EM_BIG   << CR0_EM_OFFSET;
0532     u32 cr1;
0533     u32 dmacr = 0;
0534 
0535     if (slave_mode)
0536         cr0 |= CR0_OPM_SLAVE << CR0_OPM_OFFSET;
0537     rs->slave_abort = false;
0538 
0539     cr0 |= rs->rsd << CR0_RSD_OFFSET;
0540     cr0 |= (spi->mode & 0x3U) << CR0_SCPH_OFFSET;
0541     if (spi->mode & SPI_LSB_FIRST)
0542         cr0 |= CR0_FBM_LSB << CR0_FBM_OFFSET;
0543     if (spi->mode & SPI_CS_HIGH)
0544         cr0 |= BIT(spi->chip_select) << CR0_SOI_OFFSET;
0545 
0546     if (xfer->rx_buf && xfer->tx_buf)
0547         cr0 |= CR0_XFM_TR << CR0_XFM_OFFSET;
0548     else if (xfer->rx_buf)
0549         cr0 |= CR0_XFM_RO << CR0_XFM_OFFSET;
0550     else if (use_dma)
0551         cr0 |= CR0_XFM_TO << CR0_XFM_OFFSET;
0552 
0553     switch (xfer->bits_per_word) {
0554     case 4:
0555         cr0 |= CR0_DFS_4BIT << CR0_DFS_OFFSET;
0556         cr1 = xfer->len - 1;
0557         break;
0558     case 8:
0559         cr0 |= CR0_DFS_8BIT << CR0_DFS_OFFSET;
0560         cr1 = xfer->len - 1;
0561         break;
0562     case 16:
0563         cr0 |= CR0_DFS_16BIT << CR0_DFS_OFFSET;
0564         cr1 = xfer->len / 2 - 1;
0565         break;
0566     default:
0567         /* we only whitelist 4, 8 and 16 bit words in
0568          * ctlr->bits_per_word_mask, so this shouldn't
0569          * happen
0570          */
0571         dev_err(rs->dev, "unknown bits per word: %d\n",
0572             xfer->bits_per_word);
0573         return -EINVAL;
0574     }
0575 
0576     if (use_dma) {
0577         if (xfer->tx_buf)
0578             dmacr |= TF_DMA_EN;
0579         if (xfer->rx_buf)
0580             dmacr |= RF_DMA_EN;
0581     }
0582 
0583     writel_relaxed(cr0, rs->regs + ROCKCHIP_SPI_CTRLR0);
0584     writel_relaxed(cr1, rs->regs + ROCKCHIP_SPI_CTRLR1);
0585 
0586     /* unfortunately setting the fifo threshold level to generate an
0587      * interrupt exactly when the fifo is full doesn't seem to work,
0588      * so we need the strict inequality here
0589      */
0590     if ((xfer->len / rs->n_bytes) < rs->fifo_len)
0591         writel_relaxed(xfer->len / rs->n_bytes - 1, rs->regs + ROCKCHIP_SPI_RXFTLR);
0592     else
0593         writel_relaxed(rs->fifo_len / 2 - 1, rs->regs + ROCKCHIP_SPI_RXFTLR);
0594 
0595     writel_relaxed(rs->fifo_len / 2 - 1, rs->regs + ROCKCHIP_SPI_DMATDLR);
0596     writel_relaxed(rockchip_spi_calc_burst_size(xfer->len / rs->n_bytes) - 1,
0597                rs->regs + ROCKCHIP_SPI_DMARDLR);
0598     writel_relaxed(dmacr, rs->regs + ROCKCHIP_SPI_DMACR);
0599 
0600     /* the hardware only supports an even clock divisor, so
0601      * round divisor = spiclk / speed up to nearest even number
0602      * so that the resulting speed is <= the requested speed
0603      */
0604     writel_relaxed(2 * DIV_ROUND_UP(rs->freq, 2 * xfer->speed_hz),
0605             rs->regs + ROCKCHIP_SPI_BAUDR);
0606 
0607     return 0;
0608 }
0609 
0610 static size_t rockchip_spi_max_transfer_size(struct spi_device *spi)
0611 {
0612     return ROCKCHIP_SPI_MAX_TRANLEN;
0613 }
0614 
0615 static int rockchip_spi_slave_abort(struct spi_controller *ctlr)
0616 {
0617     struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
0618     u32 rx_fifo_left;
0619     struct dma_tx_state state;
0620     enum dma_status status;
0621 
0622     /* Get current dma rx point */
0623     if (atomic_read(&rs->state) & RXDMA) {
0624         dmaengine_pause(ctlr->dma_rx);
0625         status = dmaengine_tx_status(ctlr->dma_rx, ctlr->dma_rx->cookie, &state);
0626         if (status == DMA_ERROR) {
0627             rs->rx = rs->xfer->rx_buf;
0628             rs->xfer->len = 0;
0629             rx_fifo_left = readl_relaxed(rs->regs + ROCKCHIP_SPI_RXFLR);
0630             for (; rx_fifo_left; rx_fifo_left--)
0631                 readl_relaxed(rs->regs + ROCKCHIP_SPI_RXDR);
0632             goto out;
0633         } else {
0634             rs->rx += rs->xfer->len - rs->n_bytes * state.residue;
0635         }
0636     }
0637 
0638     /* Get the valid data left in rx fifo and set rs->xfer->len real rx size */
0639     if (rs->rx) {
0640         rx_fifo_left = readl_relaxed(rs->regs + ROCKCHIP_SPI_RXFLR);
0641         for (; rx_fifo_left; rx_fifo_left--) {
0642             u32 rxw = readl_relaxed(rs->regs + ROCKCHIP_SPI_RXDR);
0643 
0644             if (rs->n_bytes == 1)
0645                 *(u8 *)rs->rx = (u8)rxw;
0646             else
0647                 *(u16 *)rs->rx = (u16)rxw;
0648             rs->rx += rs->n_bytes;
0649         }
0650         rs->xfer->len = (unsigned int)(rs->rx - rs->xfer->rx_buf);
0651     }
0652 
0653 out:
0654     if (atomic_read(&rs->state) & RXDMA)
0655         dmaengine_terminate_sync(ctlr->dma_rx);
0656     if (atomic_read(&rs->state) & TXDMA)
0657         dmaengine_terminate_sync(ctlr->dma_tx);
0658     atomic_set(&rs->state, 0);
0659     spi_enable_chip(rs, false);
0660     rs->slave_abort = true;
0661     spi_finalize_current_transfer(ctlr);
0662 
0663     return 0;
0664 }
0665 
0666 static int rockchip_spi_transfer_one(
0667         struct spi_controller *ctlr,
0668         struct spi_device *spi,
0669         struct spi_transfer *xfer)
0670 {
0671     struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
0672     int ret;
0673     bool use_dma;
0674 
0675     /* Zero length transfers won't trigger an interrupt on completion */
0676     if (!xfer->len) {
0677         spi_finalize_current_transfer(ctlr);
0678         return 1;
0679     }
0680 
0681     WARN_ON(readl_relaxed(rs->regs + ROCKCHIP_SPI_SSIENR) &&
0682         (readl_relaxed(rs->regs + ROCKCHIP_SPI_SR) & SR_BUSY));
0683 
0684     if (!xfer->tx_buf && !xfer->rx_buf) {
0685         dev_err(rs->dev, "No buffer for transfer\n");
0686         return -EINVAL;
0687     }
0688 
0689     if (xfer->len > ROCKCHIP_SPI_MAX_TRANLEN) {
0690         dev_err(rs->dev, "Transfer is too long (%d)\n", xfer->len);
0691         return -EINVAL;
0692     }
0693 
0694     rs->n_bytes = xfer->bits_per_word <= 8 ? 1 : 2;
0695     rs->xfer = xfer;
0696     use_dma = ctlr->can_dma ? ctlr->can_dma(ctlr, spi, xfer) : false;
0697 
0698     ret = rockchip_spi_config(rs, spi, xfer, use_dma, ctlr->slave);
0699     if (ret)
0700         return ret;
0701 
0702     if (use_dma)
0703         return rockchip_spi_prepare_dma(rs, ctlr, xfer);
0704 
0705     return rockchip_spi_prepare_irq(rs, ctlr, xfer);
0706 }
0707 
0708 static bool rockchip_spi_can_dma(struct spi_controller *ctlr,
0709                  struct spi_device *spi,
0710                  struct spi_transfer *xfer)
0711 {
0712     struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
0713     unsigned int bytes_per_word = xfer->bits_per_word <= 8 ? 1 : 2;
0714 
0715     /* if the numbor of spi words to transfer is less than the fifo
0716      * length we can just fill the fifo and wait for a single irq,
0717      * so don't bother setting up dma
0718      */
0719     return xfer->len / bytes_per_word >= rs->fifo_len;
0720 }
0721 
0722 static int rockchip_spi_setup(struct spi_device *spi)
0723 {
0724     struct rockchip_spi *rs = spi_controller_get_devdata(spi->controller);
0725     u32 cr0;
0726 
0727     if (!spi->cs_gpiod && (spi->mode & SPI_CS_HIGH) && !rs->cs_high_supported) {
0728         dev_warn(&spi->dev, "setup: non GPIO CS can't be active-high\n");
0729         return -EINVAL;
0730     }
0731 
0732     pm_runtime_get_sync(rs->dev);
0733 
0734     cr0 = readl_relaxed(rs->regs + ROCKCHIP_SPI_CTRLR0);
0735 
0736     cr0 &= ~(0x3 << CR0_SCPH_OFFSET);
0737     cr0 |= ((spi->mode & 0x3) << CR0_SCPH_OFFSET);
0738     if (spi->mode & SPI_CS_HIGH && spi->chip_select <= 1)
0739         cr0 |= BIT(spi->chip_select) << CR0_SOI_OFFSET;
0740     else if (spi->chip_select <= 1)
0741         cr0 &= ~(BIT(spi->chip_select) << CR0_SOI_OFFSET);
0742 
0743     writel_relaxed(cr0, rs->regs + ROCKCHIP_SPI_CTRLR0);
0744 
0745     pm_runtime_put(rs->dev);
0746 
0747     return 0;
0748 }
0749 
0750 static int rockchip_spi_probe(struct platform_device *pdev)
0751 {
0752     int ret;
0753     struct rockchip_spi *rs;
0754     struct spi_controller *ctlr;
0755     struct resource *mem;
0756     struct device_node *np = pdev->dev.of_node;
0757     u32 rsd_nsecs, num_cs;
0758     bool slave_mode;
0759 
0760     slave_mode = of_property_read_bool(np, "spi-slave");
0761 
0762     if (slave_mode)
0763         ctlr = spi_alloc_slave(&pdev->dev,
0764                 sizeof(struct rockchip_spi));
0765     else
0766         ctlr = spi_alloc_master(&pdev->dev,
0767                 sizeof(struct rockchip_spi));
0768 
0769     if (!ctlr)
0770         return -ENOMEM;
0771 
0772     platform_set_drvdata(pdev, ctlr);
0773 
0774     rs = spi_controller_get_devdata(ctlr);
0775     ctlr->slave = slave_mode;
0776 
0777     /* Get basic io resource and map it */
0778     mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
0779     rs->regs = devm_ioremap_resource(&pdev->dev, mem);
0780     if (IS_ERR(rs->regs)) {
0781         ret =  PTR_ERR(rs->regs);
0782         goto err_put_ctlr;
0783     }
0784 
0785     rs->apb_pclk = devm_clk_get(&pdev->dev, "apb_pclk");
0786     if (IS_ERR(rs->apb_pclk)) {
0787         dev_err(&pdev->dev, "Failed to get apb_pclk\n");
0788         ret = PTR_ERR(rs->apb_pclk);
0789         goto err_put_ctlr;
0790     }
0791 
0792     rs->spiclk = devm_clk_get(&pdev->dev, "spiclk");
0793     if (IS_ERR(rs->spiclk)) {
0794         dev_err(&pdev->dev, "Failed to get spi_pclk\n");
0795         ret = PTR_ERR(rs->spiclk);
0796         goto err_put_ctlr;
0797     }
0798 
0799     ret = clk_prepare_enable(rs->apb_pclk);
0800     if (ret < 0) {
0801         dev_err(&pdev->dev, "Failed to enable apb_pclk\n");
0802         goto err_put_ctlr;
0803     }
0804 
0805     ret = clk_prepare_enable(rs->spiclk);
0806     if (ret < 0) {
0807         dev_err(&pdev->dev, "Failed to enable spi_clk\n");
0808         goto err_disable_apbclk;
0809     }
0810 
0811     spi_enable_chip(rs, false);
0812 
0813     ret = platform_get_irq(pdev, 0);
0814     if (ret < 0)
0815         goto err_disable_spiclk;
0816 
0817     ret = devm_request_threaded_irq(&pdev->dev, ret, rockchip_spi_isr, NULL,
0818             IRQF_ONESHOT, dev_name(&pdev->dev), ctlr);
0819     if (ret)
0820         goto err_disable_spiclk;
0821 
0822     rs->dev = &pdev->dev;
0823     rs->freq = clk_get_rate(rs->spiclk);
0824 
0825     if (!of_property_read_u32(pdev->dev.of_node, "rx-sample-delay-ns",
0826                   &rsd_nsecs)) {
0827         /* rx sample delay is expressed in parent clock cycles (max 3) */
0828         u32 rsd = DIV_ROUND_CLOSEST(rsd_nsecs * (rs->freq >> 8),
0829                 1000000000 >> 8);
0830         if (!rsd) {
0831             dev_warn(rs->dev, "%u Hz are too slow to express %u ns delay\n",
0832                     rs->freq, rsd_nsecs);
0833         } else if (rsd > CR0_RSD_MAX) {
0834             rsd = CR0_RSD_MAX;
0835             dev_warn(rs->dev, "%u Hz are too fast to express %u ns delay, clamping at %u ns\n",
0836                     rs->freq, rsd_nsecs,
0837                     CR0_RSD_MAX * 1000000000U / rs->freq);
0838         }
0839         rs->rsd = rsd;
0840     }
0841 
0842     rs->fifo_len = get_fifo_len(rs);
0843     if (!rs->fifo_len) {
0844         dev_err(&pdev->dev, "Failed to get fifo length\n");
0845         ret = -EINVAL;
0846         goto err_disable_spiclk;
0847     }
0848 
0849     pm_runtime_set_autosuspend_delay(&pdev->dev, ROCKCHIP_AUTOSUSPEND_TIMEOUT);
0850     pm_runtime_use_autosuspend(&pdev->dev);
0851     pm_runtime_set_active(&pdev->dev);
0852     pm_runtime_enable(&pdev->dev);
0853 
0854     ctlr->auto_runtime_pm = true;
0855     ctlr->bus_num = pdev->id;
0856     ctlr->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LOOP | SPI_LSB_FIRST;
0857     if (slave_mode) {
0858         ctlr->mode_bits |= SPI_NO_CS;
0859         ctlr->slave_abort = rockchip_spi_slave_abort;
0860     } else {
0861         ctlr->flags = SPI_MASTER_GPIO_SS;
0862         ctlr->max_native_cs = ROCKCHIP_SPI_MAX_CS_NUM;
0863         /*
0864          * rk spi0 has two native cs, spi1..5 one cs only
0865          * if num-cs is missing in the dts, default to 1
0866          */
0867         if (of_property_read_u32(np, "num-cs", &num_cs))
0868             num_cs = 1;
0869         ctlr->num_chipselect = num_cs;
0870         ctlr->use_gpio_descriptors = true;
0871     }
0872     ctlr->dev.of_node = pdev->dev.of_node;
0873     ctlr->bits_per_word_mask = SPI_BPW_MASK(16) | SPI_BPW_MASK(8) | SPI_BPW_MASK(4);
0874     ctlr->min_speed_hz = rs->freq / BAUDR_SCKDV_MAX;
0875     ctlr->max_speed_hz = min(rs->freq / BAUDR_SCKDV_MIN, MAX_SCLK_OUT);
0876 
0877     ctlr->setup = rockchip_spi_setup;
0878     ctlr->set_cs = rockchip_spi_set_cs;
0879     ctlr->transfer_one = rockchip_spi_transfer_one;
0880     ctlr->max_transfer_size = rockchip_spi_max_transfer_size;
0881     ctlr->handle_err = rockchip_spi_handle_err;
0882 
0883     ctlr->dma_tx = dma_request_chan(rs->dev, "tx");
0884     if (IS_ERR(ctlr->dma_tx)) {
0885         /* Check tx to see if we need defer probing driver */
0886         if (PTR_ERR(ctlr->dma_tx) == -EPROBE_DEFER) {
0887             ret = -EPROBE_DEFER;
0888             goto err_disable_pm_runtime;
0889         }
0890         dev_warn(rs->dev, "Failed to request TX DMA channel\n");
0891         ctlr->dma_tx = NULL;
0892     }
0893 
0894     ctlr->dma_rx = dma_request_chan(rs->dev, "rx");
0895     if (IS_ERR(ctlr->dma_rx)) {
0896         if (PTR_ERR(ctlr->dma_rx) == -EPROBE_DEFER) {
0897             ret = -EPROBE_DEFER;
0898             goto err_free_dma_tx;
0899         }
0900         dev_warn(rs->dev, "Failed to request RX DMA channel\n");
0901         ctlr->dma_rx = NULL;
0902     }
0903 
0904     if (ctlr->dma_tx && ctlr->dma_rx) {
0905         rs->dma_addr_tx = mem->start + ROCKCHIP_SPI_TXDR;
0906         rs->dma_addr_rx = mem->start + ROCKCHIP_SPI_RXDR;
0907         ctlr->can_dma = rockchip_spi_can_dma;
0908     }
0909 
0910     switch (readl_relaxed(rs->regs + ROCKCHIP_SPI_VERSION)) {
0911     case ROCKCHIP_SPI_VER2_TYPE2:
0912         rs->cs_high_supported = true;
0913         ctlr->mode_bits |= SPI_CS_HIGH;
0914         if (ctlr->can_dma && slave_mode)
0915             rs->cs_inactive = true;
0916         else
0917             rs->cs_inactive = false;
0918         break;
0919     default:
0920         rs->cs_inactive = false;
0921         break;
0922     }
0923 
0924     ret = devm_spi_register_controller(&pdev->dev, ctlr);
0925     if (ret < 0) {
0926         dev_err(&pdev->dev, "Failed to register controller\n");
0927         goto err_free_dma_rx;
0928     }
0929 
0930     return 0;
0931 
0932 err_free_dma_rx:
0933     if (ctlr->dma_rx)
0934         dma_release_channel(ctlr->dma_rx);
0935 err_free_dma_tx:
0936     if (ctlr->dma_tx)
0937         dma_release_channel(ctlr->dma_tx);
0938 err_disable_pm_runtime:
0939     pm_runtime_disable(&pdev->dev);
0940 err_disable_spiclk:
0941     clk_disable_unprepare(rs->spiclk);
0942 err_disable_apbclk:
0943     clk_disable_unprepare(rs->apb_pclk);
0944 err_put_ctlr:
0945     spi_controller_put(ctlr);
0946 
0947     return ret;
0948 }
0949 
0950 static int rockchip_spi_remove(struct platform_device *pdev)
0951 {
0952     struct spi_controller *ctlr = spi_controller_get(platform_get_drvdata(pdev));
0953     struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
0954 
0955     pm_runtime_get_sync(&pdev->dev);
0956 
0957     clk_disable_unprepare(rs->spiclk);
0958     clk_disable_unprepare(rs->apb_pclk);
0959 
0960     pm_runtime_put_noidle(&pdev->dev);
0961     pm_runtime_disable(&pdev->dev);
0962     pm_runtime_set_suspended(&pdev->dev);
0963 
0964     if (ctlr->dma_tx)
0965         dma_release_channel(ctlr->dma_tx);
0966     if (ctlr->dma_rx)
0967         dma_release_channel(ctlr->dma_rx);
0968 
0969     spi_controller_put(ctlr);
0970 
0971     return 0;
0972 }
0973 
0974 #ifdef CONFIG_PM_SLEEP
0975 static int rockchip_spi_suspend(struct device *dev)
0976 {
0977     int ret;
0978     struct spi_controller *ctlr = dev_get_drvdata(dev);
0979     struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
0980 
0981     ret = spi_controller_suspend(ctlr);
0982     if (ret < 0)
0983         return ret;
0984 
0985     clk_disable_unprepare(rs->spiclk);
0986     clk_disable_unprepare(rs->apb_pclk);
0987 
0988     pinctrl_pm_select_sleep_state(dev);
0989 
0990     return 0;
0991 }
0992 
0993 static int rockchip_spi_resume(struct device *dev)
0994 {
0995     int ret;
0996     struct spi_controller *ctlr = dev_get_drvdata(dev);
0997     struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
0998 
0999     pinctrl_pm_select_default_state(dev);
1000 
1001     ret = clk_prepare_enable(rs->apb_pclk);
1002     if (ret < 0)
1003         return ret;
1004 
1005     ret = clk_prepare_enable(rs->spiclk);
1006     if (ret < 0)
1007         clk_disable_unprepare(rs->apb_pclk);
1008 
1009     ret = spi_controller_resume(ctlr);
1010     if (ret < 0) {
1011         clk_disable_unprepare(rs->spiclk);
1012         clk_disable_unprepare(rs->apb_pclk);
1013     }
1014 
1015     return 0;
1016 }
1017 #endif /* CONFIG_PM_SLEEP */
1018 
1019 #ifdef CONFIG_PM
1020 static int rockchip_spi_runtime_suspend(struct device *dev)
1021 {
1022     struct spi_controller *ctlr = dev_get_drvdata(dev);
1023     struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
1024 
1025     clk_disable_unprepare(rs->spiclk);
1026     clk_disable_unprepare(rs->apb_pclk);
1027 
1028     return 0;
1029 }
1030 
1031 static int rockchip_spi_runtime_resume(struct device *dev)
1032 {
1033     int ret;
1034     struct spi_controller *ctlr = dev_get_drvdata(dev);
1035     struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
1036 
1037     ret = clk_prepare_enable(rs->apb_pclk);
1038     if (ret < 0)
1039         return ret;
1040 
1041     ret = clk_prepare_enable(rs->spiclk);
1042     if (ret < 0)
1043         clk_disable_unprepare(rs->apb_pclk);
1044 
1045     return 0;
1046 }
1047 #endif /* CONFIG_PM */
1048 
1049 static const struct dev_pm_ops rockchip_spi_pm = {
1050     SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(rockchip_spi_suspend, rockchip_spi_resume)
1051     SET_RUNTIME_PM_OPS(rockchip_spi_runtime_suspend,
1052                rockchip_spi_runtime_resume, NULL)
1053 };
1054 
1055 static const struct of_device_id rockchip_spi_dt_match[] = {
1056     { .compatible = "rockchip,px30-spi", },
1057     { .compatible = "rockchip,rk3036-spi", },
1058     { .compatible = "rockchip,rk3066-spi", },
1059     { .compatible = "rockchip,rk3188-spi", },
1060     { .compatible = "rockchip,rk3228-spi", },
1061     { .compatible = "rockchip,rk3288-spi", },
1062     { .compatible = "rockchip,rk3308-spi", },
1063     { .compatible = "rockchip,rk3328-spi", },
1064     { .compatible = "rockchip,rk3368-spi", },
1065     { .compatible = "rockchip,rk3399-spi", },
1066     { .compatible = "rockchip,rv1108-spi", },
1067     { .compatible = "rockchip,rv1126-spi", },
1068     { },
1069 };
1070 MODULE_DEVICE_TABLE(of, rockchip_spi_dt_match);
1071 
1072 static struct platform_driver rockchip_spi_driver = {
1073     .driver = {
1074         .name   = DRIVER_NAME,
1075         .pm = &rockchip_spi_pm,
1076         .of_match_table = of_match_ptr(rockchip_spi_dt_match),
1077     },
1078     .probe = rockchip_spi_probe,
1079     .remove = rockchip_spi_remove,
1080 };
1081 
1082 module_platform_driver(rockchip_spi_driver);
1083 
1084 MODULE_AUTHOR("Addy Ke <addy.ke@rock-chips.com>");
1085 MODULE_DESCRIPTION("ROCKCHIP SPI Controller Driver");
1086 MODULE_LICENSE("GPL v2");
[ Source navigation ] [ Diff markup ] [ Identifier search ] [ general search ]

This page was automatically generated by the 2.1.0 LXR engine.

The LXR team
Valid CSS 2.1! Valid HTML 4.01!