Back to home page

OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Rockchip Serial Flash Controller Driver
0004  *
0005  * Copyright (c) 2017-2021, Rockchip Inc.
0006  * Author: Shawn Lin <shawn.lin@rock-chips.com>
0007  *     Chris Morgan <macroalpha82@gmail.com>
0008  *     Jon Lin <Jon.lin@rock-chips.com>
0009  */
0010 
0011 #include <linux/bitops.h>
0012 #include <linux/clk.h>
0013 #include <linux/completion.h>
0014 #include <linux/dma-mapping.h>
0015 #include <linux/iopoll.h>
0016 #include <linux/mm.h>
0017 #include <linux/module.h>
0018 #include <linux/of.h>
0019 #include <linux/platform_device.h>
0020 #include <linux/slab.h>
0021 #include <linux/interrupt.h>
0022 #include <linux/spi/spi-mem.h>
0023 
0024 /* System control */
0025 #define SFC_CTRL            0x0
0026 #define  SFC_CTRL_PHASE_SEL_NEGETIVE    BIT(1)
0027 #define  SFC_CTRL_CMD_BITS_SHIFT    8
0028 #define  SFC_CTRL_ADDR_BITS_SHIFT   10
0029 #define  SFC_CTRL_DATA_BITS_SHIFT   12
0030 
0031 /* Interrupt mask */
0032 #define SFC_IMR             0x4
0033 #define  SFC_IMR_RX_FULL        BIT(0)
0034 #define  SFC_IMR_RX_UFLOW       BIT(1)
0035 #define  SFC_IMR_TX_OFLOW       BIT(2)
0036 #define  SFC_IMR_TX_EMPTY       BIT(3)
0037 #define  SFC_IMR_TRAN_FINISH        BIT(4)
0038 #define  SFC_IMR_BUS_ERR        BIT(5)
0039 #define  SFC_IMR_NSPI_ERR       BIT(6)
0040 #define  SFC_IMR_DMA            BIT(7)
0041 
0042 /* Interrupt clear */
0043 #define SFC_ICLR            0x8
0044 #define  SFC_ICLR_RX_FULL       BIT(0)
0045 #define  SFC_ICLR_RX_UFLOW      BIT(1)
0046 #define  SFC_ICLR_TX_OFLOW      BIT(2)
0047 #define  SFC_ICLR_TX_EMPTY      BIT(3)
0048 #define  SFC_ICLR_TRAN_FINISH       BIT(4)
0049 #define  SFC_ICLR_BUS_ERR       BIT(5)
0050 #define  SFC_ICLR_NSPI_ERR      BIT(6)
0051 #define  SFC_ICLR_DMA           BIT(7)
0052 
0053 /* FIFO threshold level */
0054 #define SFC_FTLR            0xc
0055 #define  SFC_FTLR_TX_SHIFT      0
0056 #define  SFC_FTLR_TX_MASK       0x1f
0057 #define  SFC_FTLR_RX_SHIFT      8
0058 #define  SFC_FTLR_RX_MASK       0x1f
0059 
0060 /* Reset FSM and FIFO */
0061 #define SFC_RCVR            0x10
0062 #define  SFC_RCVR_RESET         BIT(0)
0063 
0064 /* Enhanced mode */
0065 #define SFC_AX              0x14
0066 
0067 /* Address Bit number */
0068 #define SFC_ABIT            0x18
0069 
0070 /* Interrupt status */
0071 #define SFC_ISR             0x1c
0072 #define  SFC_ISR_RX_FULL_SHIFT      BIT(0)
0073 #define  SFC_ISR_RX_UFLOW_SHIFT     BIT(1)
0074 #define  SFC_ISR_TX_OFLOW_SHIFT     BIT(2)
0075 #define  SFC_ISR_TX_EMPTY_SHIFT     BIT(3)
0076 #define  SFC_ISR_TX_FINISH_SHIFT    BIT(4)
0077 #define  SFC_ISR_BUS_ERR_SHIFT      BIT(5)
0078 #define  SFC_ISR_NSPI_ERR_SHIFT     BIT(6)
0079 #define  SFC_ISR_DMA_SHIFT      BIT(7)
0080 
0081 /* FIFO status */
0082 #define SFC_FSR             0x20
0083 #define  SFC_FSR_TX_IS_FULL     BIT(0)
0084 #define  SFC_FSR_TX_IS_EMPTY        BIT(1)
0085 #define  SFC_FSR_RX_IS_EMPTY        BIT(2)
0086 #define  SFC_FSR_RX_IS_FULL     BIT(3)
0087 #define  SFC_FSR_TXLV_MASK      GENMASK(12, 8)
0088 #define  SFC_FSR_TXLV_SHIFT     8
0089 #define  SFC_FSR_RXLV_MASK      GENMASK(20, 16)
0090 #define  SFC_FSR_RXLV_SHIFT     16
0091 
0092 /* FSM status */
0093 #define SFC_SR              0x24
0094 #define  SFC_SR_IS_IDLE         0x0
0095 #define  SFC_SR_IS_BUSY         0x1
0096 
0097 /* Raw interrupt status */
0098 #define SFC_RISR            0x28
0099 #define  SFC_RISR_RX_FULL       BIT(0)
0100 #define  SFC_RISR_RX_UNDERFLOW      BIT(1)
0101 #define  SFC_RISR_TX_OVERFLOW       BIT(2)
0102 #define  SFC_RISR_TX_EMPTY      BIT(3)
0103 #define  SFC_RISR_TRAN_FINISH       BIT(4)
0104 #define  SFC_RISR_BUS_ERR       BIT(5)
0105 #define  SFC_RISR_NSPI_ERR      BIT(6)
0106 #define  SFC_RISR_DMA           BIT(7)
0107 
0108 /* Version */
0109 #define SFC_VER             0x2C
0110 #define  SFC_VER_3          0x3
0111 #define  SFC_VER_4          0x4
0112 #define  SFC_VER_5          0x5
0113 
0114 /* Delay line controller resiter */
0115 #define SFC_DLL_CTRL0           0x3C
0116 #define SFC_DLL_CTRL0_SCLK_SMP_DLL  BIT(15)
0117 #define SFC_DLL_CTRL0_DLL_MAX_VER4  0xFFU
0118 #define SFC_DLL_CTRL0_DLL_MAX_VER5  0x1FFU
0119 
0120 /* Master trigger */
0121 #define SFC_DMA_TRIGGER         0x80
0122 #define SFC_DMA_TRIGGER_START       1
0123 
0124 /* Src or Dst addr for master */
0125 #define SFC_DMA_ADDR            0x84
0126 
0127 /* Length control register extension 32GB */
0128 #define SFC_LEN_CTRL            0x88
0129 #define SFC_LEN_CTRL_TRB_SEL        1
0130 #define SFC_LEN_EXT         0x8C
0131 
0132 /* Command */
0133 #define SFC_CMD             0x100
0134 #define  SFC_CMD_IDX_SHIFT      0
0135 #define  SFC_CMD_DUMMY_SHIFT        8
0136 #define  SFC_CMD_DIR_SHIFT      12
0137 #define  SFC_CMD_DIR_RD         0
0138 #define  SFC_CMD_DIR_WR         1
0139 #define  SFC_CMD_ADDR_SHIFT     14
0140 #define  SFC_CMD_ADDR_0BITS     0
0141 #define  SFC_CMD_ADDR_24BITS        1
0142 #define  SFC_CMD_ADDR_32BITS        2
0143 #define  SFC_CMD_ADDR_XBITS     3
0144 #define  SFC_CMD_TRAN_BYTES_SHIFT   16
0145 #define  SFC_CMD_CS_SHIFT       30
0146 
0147 /* Address */
0148 #define SFC_ADDR            0x104
0149 
0150 /* Data */
0151 #define SFC_DATA            0x108
0152 
0153 /* The controller and documentation reports that it supports up to 4 CS
0154  * devices (0-3), however I have only been able to test a single CS (CS 0)
0155  * due to the configuration of my device.
0156  */
0157 #define SFC_MAX_CHIPSELECT_NUM      4
0158 
0159 /* The SFC can transfer max 16KB - 1 at one time
0160  * we set it to 15.5KB here for alignment.
0161  */
0162 #define SFC_MAX_IOSIZE_VER3     (512 * 31)
0163 
0164 /* DMA is only enabled for large data transmission */
0165 #define SFC_DMA_TRANS_THRETHOLD     (0x40)
0166 
0167 /* Maximum clock values from datasheet suggest keeping clock value under
0168  * 150MHz. No minimum or average value is suggested.
0169  */
0170 #define SFC_MAX_SPEED       (150 * 1000 * 1000)
0171 
0172 struct rockchip_sfc {
0173     struct device *dev;
0174     void __iomem *regbase;
0175     struct clk *hclk;
0176     struct clk *clk;
0177     u32 frequency;
0178     /* virtual mapped addr for dma_buffer */
0179     void *buffer;
0180     dma_addr_t dma_buffer;
0181     struct completion cp;
0182     bool use_dma;
0183     u32 max_iosize;
0184     u16 version;
0185 };
0186 
0187 static int rockchip_sfc_reset(struct rockchip_sfc *sfc)
0188 {
0189     int err;
0190     u32 status;
0191 
0192     writel_relaxed(SFC_RCVR_RESET, sfc->regbase + SFC_RCVR);
0193 
0194     err = readl_poll_timeout(sfc->regbase + SFC_RCVR, status,
0195                  !(status & SFC_RCVR_RESET), 20,
0196                  jiffies_to_usecs(HZ));
0197     if (err)
0198         dev_err(sfc->dev, "SFC reset never finished\n");
0199 
0200     /* Still need to clear the masked interrupt from RISR */
0201     writel_relaxed(0xFFFFFFFF, sfc->regbase + SFC_ICLR);
0202 
0203     dev_dbg(sfc->dev, "reset\n");
0204 
0205     return err;
0206 }
0207 
0208 static u16 rockchip_sfc_get_version(struct rockchip_sfc *sfc)
0209 {
0210     return  (u16)(readl(sfc->regbase + SFC_VER) & 0xffff);
0211 }
0212 
0213 static u32 rockchip_sfc_get_max_iosize(struct rockchip_sfc *sfc)
0214 {
0215     return SFC_MAX_IOSIZE_VER3;
0216 }
0217 
0218 static void rockchip_sfc_irq_unmask(struct rockchip_sfc *sfc, u32 mask)
0219 {
0220     u32 reg;
0221 
0222     /* Enable transfer complete interrupt */
0223     reg = readl(sfc->regbase + SFC_IMR);
0224     reg &= ~mask;
0225     writel(reg, sfc->regbase + SFC_IMR);
0226 }
0227 
0228 static void rockchip_sfc_irq_mask(struct rockchip_sfc *sfc, u32 mask)
0229 {
0230     u32 reg;
0231 
0232     /* Disable transfer finish interrupt */
0233     reg = readl(sfc->regbase + SFC_IMR);
0234     reg |= mask;
0235     writel(reg, sfc->regbase + SFC_IMR);
0236 }
0237 
0238 static int rockchip_sfc_init(struct rockchip_sfc *sfc)
0239 {
0240     writel(0, sfc->regbase + SFC_CTRL);
0241     writel(0xFFFFFFFF, sfc->regbase + SFC_ICLR);
0242     rockchip_sfc_irq_mask(sfc, 0xFFFFFFFF);
0243     if (rockchip_sfc_get_version(sfc) >= SFC_VER_4)
0244         writel(SFC_LEN_CTRL_TRB_SEL, sfc->regbase + SFC_LEN_CTRL);
0245 
0246     return 0;
0247 }
0248 
0249 static int rockchip_sfc_wait_txfifo_ready(struct rockchip_sfc *sfc, u32 timeout_us)
0250 {
0251     int ret = 0;
0252     u32 status;
0253 
0254     ret = readl_poll_timeout(sfc->regbase + SFC_FSR, status,
0255                  status & SFC_FSR_TXLV_MASK, 0,
0256                  timeout_us);
0257     if (ret) {
0258         dev_dbg(sfc->dev, "sfc wait tx fifo timeout\n");
0259 
0260         return -ETIMEDOUT;
0261     }
0262 
0263     return (status & SFC_FSR_TXLV_MASK) >> SFC_FSR_TXLV_SHIFT;
0264 }
0265 
0266 static int rockchip_sfc_wait_rxfifo_ready(struct rockchip_sfc *sfc, u32 timeout_us)
0267 {
0268     int ret = 0;
0269     u32 status;
0270 
0271     ret = readl_poll_timeout(sfc->regbase + SFC_FSR, status,
0272                  status & SFC_FSR_RXLV_MASK, 0,
0273                  timeout_us);
0274     if (ret) {
0275         dev_dbg(sfc->dev, "sfc wait rx fifo timeout\n");
0276 
0277         return -ETIMEDOUT;
0278     }
0279 
0280     return (status & SFC_FSR_RXLV_MASK) >> SFC_FSR_RXLV_SHIFT;
0281 }
0282 
0283 static void rockchip_sfc_adjust_op_work(struct spi_mem_op *op)
0284 {
0285     if (unlikely(op->dummy.nbytes && !op->addr.nbytes)) {
0286         /*
0287          * SFC not support output DUMMY cycles right after CMD cycles, so
0288          * treat it as ADDR cycles.
0289          */
0290         op->addr.nbytes = op->dummy.nbytes;
0291         op->addr.buswidth = op->dummy.buswidth;
0292         op->addr.val = 0xFFFFFFFFF;
0293 
0294         op->dummy.nbytes = 0;
0295     }
0296 }
0297 
0298 static int rockchip_sfc_xfer_setup(struct rockchip_sfc *sfc,
0299                    struct spi_mem *mem,
0300                    const struct spi_mem_op *op,
0301                    u32 len)
0302 {
0303     u32 ctrl = 0, cmd = 0;
0304 
0305     /* set CMD */
0306     cmd = op->cmd.opcode;
0307     ctrl |= ((op->cmd.buswidth >> 1) << SFC_CTRL_CMD_BITS_SHIFT);
0308 
0309     /* set ADDR */
0310     if (op->addr.nbytes) {
0311         if (op->addr.nbytes == 4) {
0312             cmd |= SFC_CMD_ADDR_32BITS << SFC_CMD_ADDR_SHIFT;
0313         } else if (op->addr.nbytes == 3) {
0314             cmd |= SFC_CMD_ADDR_24BITS << SFC_CMD_ADDR_SHIFT;
0315         } else {
0316             cmd |= SFC_CMD_ADDR_XBITS << SFC_CMD_ADDR_SHIFT;
0317             writel(op->addr.nbytes * 8 - 1, sfc->regbase + SFC_ABIT);
0318         }
0319 
0320         ctrl |= ((op->addr.buswidth >> 1) << SFC_CTRL_ADDR_BITS_SHIFT);
0321     }
0322 
0323     /* set DUMMY */
0324     if (op->dummy.nbytes) {
0325         if (op->dummy.buswidth == 4)
0326             cmd |= op->dummy.nbytes * 2 << SFC_CMD_DUMMY_SHIFT;
0327         else if (op->dummy.buswidth == 2)
0328             cmd |= op->dummy.nbytes * 4 << SFC_CMD_DUMMY_SHIFT;
0329         else
0330             cmd |= op->dummy.nbytes * 8 << SFC_CMD_DUMMY_SHIFT;
0331     }
0332 
0333     /* set DATA */
0334     if (sfc->version >= SFC_VER_4) /* Clear it if no data to transfer */
0335         writel(len, sfc->regbase + SFC_LEN_EXT);
0336     else
0337         cmd |= len << SFC_CMD_TRAN_BYTES_SHIFT;
0338     if (len) {
0339         if (op->data.dir == SPI_MEM_DATA_OUT)
0340             cmd |= SFC_CMD_DIR_WR << SFC_CMD_DIR_SHIFT;
0341 
0342         ctrl |= ((op->data.buswidth >> 1) << SFC_CTRL_DATA_BITS_SHIFT);
0343     }
0344     if (!len && op->addr.nbytes)
0345         cmd |= SFC_CMD_DIR_WR << SFC_CMD_DIR_SHIFT;
0346 
0347     /* set the Controller */
0348     ctrl |= SFC_CTRL_PHASE_SEL_NEGETIVE;
0349     cmd |= mem->spi->chip_select << SFC_CMD_CS_SHIFT;
0350 
0351     dev_dbg(sfc->dev, "sfc addr.nbytes=%x(x%d) dummy.nbytes=%x(x%d)\n",
0352         op->addr.nbytes, op->addr.buswidth,
0353         op->dummy.nbytes, op->dummy.buswidth);
0354     dev_dbg(sfc->dev, "sfc ctrl=%x cmd=%x addr=%llx len=%x\n",
0355         ctrl, cmd, op->addr.val, len);
0356 
0357     writel(ctrl, sfc->regbase + SFC_CTRL);
0358     writel(cmd, sfc->regbase + SFC_CMD);
0359     if (op->addr.nbytes)
0360         writel(op->addr.val, sfc->regbase + SFC_ADDR);
0361 
0362     return 0;
0363 }
0364 
0365 static int rockchip_sfc_write_fifo(struct rockchip_sfc *sfc, const u8 *buf, int len)
0366 {
0367     u8 bytes = len & 0x3;
0368     u32 dwords;
0369     int tx_level;
0370     u32 write_words;
0371     u32 tmp = 0;
0372 
0373     dwords = len >> 2;
0374     while (dwords) {
0375         tx_level = rockchip_sfc_wait_txfifo_ready(sfc, 1000);
0376         if (tx_level < 0)
0377             return tx_level;
0378         write_words = min_t(u32, tx_level, dwords);
0379         iowrite32_rep(sfc->regbase + SFC_DATA, buf, write_words);
0380         buf += write_words << 2;
0381         dwords -= write_words;
0382     }
0383 
0384     /* write the rest non word aligned bytes */
0385     if (bytes) {
0386         tx_level = rockchip_sfc_wait_txfifo_ready(sfc, 1000);
0387         if (tx_level < 0)
0388             return tx_level;
0389         memcpy(&tmp, buf, bytes);
0390         writel(tmp, sfc->regbase + SFC_DATA);
0391     }
0392 
0393     return len;
0394 }
0395 
0396 static int rockchip_sfc_read_fifo(struct rockchip_sfc *sfc, u8 *buf, int len)
0397 {
0398     u8 bytes = len & 0x3;
0399     u32 dwords;
0400     u8 read_words;
0401     int rx_level;
0402     int tmp;
0403 
0404     /* word aligned access only */
0405     dwords = len >> 2;
0406     while (dwords) {
0407         rx_level = rockchip_sfc_wait_rxfifo_ready(sfc, 1000);
0408         if (rx_level < 0)
0409             return rx_level;
0410         read_words = min_t(u32, rx_level, dwords);
0411         ioread32_rep(sfc->regbase + SFC_DATA, buf, read_words);
0412         buf += read_words << 2;
0413         dwords -= read_words;
0414     }
0415 
0416     /* read the rest non word aligned bytes */
0417     if (bytes) {
0418         rx_level = rockchip_sfc_wait_rxfifo_ready(sfc, 1000);
0419         if (rx_level < 0)
0420             return rx_level;
0421         tmp = readl(sfc->regbase + SFC_DATA);
0422         memcpy(buf, &tmp, bytes);
0423     }
0424 
0425     return len;
0426 }
0427 
0428 static int rockchip_sfc_fifo_transfer_dma(struct rockchip_sfc *sfc, dma_addr_t dma_buf, size_t len)
0429 {
0430     writel(0xFFFFFFFF, sfc->regbase + SFC_ICLR);
0431     writel((u32)dma_buf, sfc->regbase + SFC_DMA_ADDR);
0432     writel(SFC_DMA_TRIGGER_START, sfc->regbase + SFC_DMA_TRIGGER);
0433 
0434     return len;
0435 }
0436 
0437 static int rockchip_sfc_xfer_data_poll(struct rockchip_sfc *sfc,
0438                        const struct spi_mem_op *op, u32 len)
0439 {
0440     dev_dbg(sfc->dev, "sfc xfer_poll len=%x\n", len);
0441 
0442     if (op->data.dir == SPI_MEM_DATA_OUT)
0443         return rockchip_sfc_write_fifo(sfc, op->data.buf.out, len);
0444     else
0445         return rockchip_sfc_read_fifo(sfc, op->data.buf.in, len);
0446 }
0447 
0448 static int rockchip_sfc_xfer_data_dma(struct rockchip_sfc *sfc,
0449                       const struct spi_mem_op *op, u32 len)
0450 {
0451     int ret;
0452 
0453     dev_dbg(sfc->dev, "sfc xfer_dma len=%x\n", len);
0454 
0455     if (op->data.dir == SPI_MEM_DATA_OUT)
0456         memcpy(sfc->buffer, op->data.buf.out, len);
0457 
0458     ret = rockchip_sfc_fifo_transfer_dma(sfc, sfc->dma_buffer, len);
0459     if (!wait_for_completion_timeout(&sfc->cp, msecs_to_jiffies(2000))) {
0460         dev_err(sfc->dev, "DMA wait for transfer finish timeout\n");
0461         ret = -ETIMEDOUT;
0462     }
0463     rockchip_sfc_irq_mask(sfc, SFC_IMR_DMA);
0464     if (op->data.dir == SPI_MEM_DATA_IN)
0465         memcpy(op->data.buf.in, sfc->buffer, len);
0466 
0467     return ret;
0468 }
0469 
0470 static int rockchip_sfc_xfer_done(struct rockchip_sfc *sfc, u32 timeout_us)
0471 {
0472     int ret = 0;
0473     u32 status;
0474 
0475     ret = readl_poll_timeout(sfc->regbase + SFC_SR, status,
0476                  !(status & SFC_SR_IS_BUSY),
0477                  20, timeout_us);
0478     if (ret) {
0479         dev_err(sfc->dev, "wait sfc idle timeout\n");
0480         rockchip_sfc_reset(sfc);
0481 
0482         ret = -EIO;
0483     }
0484 
0485     return ret;
0486 }
0487 
0488 static int rockchip_sfc_exec_mem_op(struct spi_mem *mem, const struct spi_mem_op *op)
0489 {
0490     struct rockchip_sfc *sfc = spi_master_get_devdata(mem->spi->master);
0491     u32 len = op->data.nbytes;
0492     int ret;
0493 
0494     if (unlikely(mem->spi->max_speed_hz != sfc->frequency)) {
0495         ret = clk_set_rate(sfc->clk, mem->spi->max_speed_hz);
0496         if (ret)
0497             return ret;
0498         sfc->frequency = mem->spi->max_speed_hz;
0499         dev_dbg(sfc->dev, "set_freq=%dHz real_freq=%ldHz\n",
0500             sfc->frequency, clk_get_rate(sfc->clk));
0501     }
0502 
0503     rockchip_sfc_adjust_op_work((struct spi_mem_op *)op);
0504     rockchip_sfc_xfer_setup(sfc, mem, op, len);
0505     if (len) {
0506         if (likely(sfc->use_dma) && len >= SFC_DMA_TRANS_THRETHOLD) {
0507             init_completion(&sfc->cp);
0508             rockchip_sfc_irq_unmask(sfc, SFC_IMR_DMA);
0509             ret = rockchip_sfc_xfer_data_dma(sfc, op, len);
0510         } else {
0511             ret = rockchip_sfc_xfer_data_poll(sfc, op, len);
0512         }
0513 
0514         if (ret != len) {
0515             dev_err(sfc->dev, "xfer data failed ret %d dir %d\n", ret, op->data.dir);
0516 
0517             return -EIO;
0518         }
0519     }
0520 
0521     return rockchip_sfc_xfer_done(sfc, 100000);
0522 }
0523 
0524 static int rockchip_sfc_adjust_op_size(struct spi_mem *mem, struct spi_mem_op *op)
0525 {
0526     struct rockchip_sfc *sfc = spi_master_get_devdata(mem->spi->master);
0527 
0528     op->data.nbytes = min(op->data.nbytes, sfc->max_iosize);
0529 
0530     return 0;
0531 }
0532 
0533 static const struct spi_controller_mem_ops rockchip_sfc_mem_ops = {
0534     .exec_op = rockchip_sfc_exec_mem_op,
0535     .adjust_op_size = rockchip_sfc_adjust_op_size,
0536 };
0537 
0538 static irqreturn_t rockchip_sfc_irq_handler(int irq, void *dev_id)
0539 {
0540     struct rockchip_sfc *sfc = dev_id;
0541     u32 reg;
0542 
0543     reg = readl(sfc->regbase + SFC_RISR);
0544 
0545     /* Clear interrupt */
0546     writel_relaxed(reg, sfc->regbase + SFC_ICLR);
0547 
0548     if (reg & SFC_RISR_DMA) {
0549         complete(&sfc->cp);
0550 
0551         return IRQ_HANDLED;
0552     }
0553 
0554     return IRQ_NONE;
0555 }
0556 
0557 static int rockchip_sfc_probe(struct platform_device *pdev)
0558 {
0559     struct device *dev = &pdev->dev;
0560     struct spi_master *master;
0561     struct resource *res;
0562     struct rockchip_sfc *sfc;
0563     int ret;
0564 
0565     master = devm_spi_alloc_master(&pdev->dev, sizeof(*sfc));
0566     if (!master)
0567         return -ENOMEM;
0568 
0569     master->flags = SPI_MASTER_HALF_DUPLEX;
0570     master->mem_ops = &rockchip_sfc_mem_ops;
0571     master->dev.of_node = pdev->dev.of_node;
0572     master->mode_bits = SPI_TX_QUAD | SPI_TX_DUAL | SPI_RX_QUAD | SPI_RX_DUAL;
0573     master->max_speed_hz = SFC_MAX_SPEED;
0574     master->num_chipselect = SFC_MAX_CHIPSELECT_NUM;
0575 
0576     sfc = spi_master_get_devdata(master);
0577     sfc->dev = dev;
0578 
0579     res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
0580     sfc->regbase = devm_ioremap_resource(dev, res);
0581     if (IS_ERR(sfc->regbase))
0582         return PTR_ERR(sfc->regbase);
0583 
0584     sfc->clk = devm_clk_get(&pdev->dev, "clk_sfc");
0585     if (IS_ERR(sfc->clk)) {
0586         dev_err(&pdev->dev, "Failed to get sfc interface clk\n");
0587         return PTR_ERR(sfc->clk);
0588     }
0589 
0590     sfc->hclk = devm_clk_get(&pdev->dev, "hclk_sfc");
0591     if (IS_ERR(sfc->hclk)) {
0592         dev_err(&pdev->dev, "Failed to get sfc ahb clk\n");
0593         return PTR_ERR(sfc->hclk);
0594     }
0595 
0596     sfc->use_dma = !of_property_read_bool(sfc->dev->of_node,
0597                           "rockchip,sfc-no-dma");
0598 
0599     if (sfc->use_dma) {
0600         ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
0601         if (ret) {
0602             dev_warn(dev, "Unable to set dma mask\n");
0603             return ret;
0604         }
0605 
0606         sfc->buffer = dmam_alloc_coherent(dev, SFC_MAX_IOSIZE_VER3,
0607                           &sfc->dma_buffer,
0608                           GFP_KERNEL);
0609         if (!sfc->buffer)
0610             return -ENOMEM;
0611     }
0612 
0613     ret = clk_prepare_enable(sfc->hclk);
0614     if (ret) {
0615         dev_err(&pdev->dev, "Failed to enable ahb clk\n");
0616         goto err_hclk;
0617     }
0618 
0619     ret = clk_prepare_enable(sfc->clk);
0620     if (ret) {
0621         dev_err(&pdev->dev, "Failed to enable interface clk\n");
0622         goto err_clk;
0623     }
0624 
0625     /* Find the irq */
0626     ret = platform_get_irq(pdev, 0);
0627     if (ret < 0)
0628         goto err_irq;
0629 
0630     ret = devm_request_irq(dev, ret, rockchip_sfc_irq_handler,
0631                    0, pdev->name, sfc);
0632     if (ret) {
0633         dev_err(dev, "Failed to request irq\n");
0634 
0635         return ret;
0636     }
0637 
0638     ret = rockchip_sfc_init(sfc);
0639     if (ret)
0640         goto err_irq;
0641 
0642     sfc->max_iosize = rockchip_sfc_get_max_iosize(sfc);
0643     sfc->version = rockchip_sfc_get_version(sfc);
0644 
0645     ret = spi_register_master(master);
0646     if (ret)
0647         goto err_irq;
0648 
0649     return 0;
0650 
0651 err_irq:
0652     clk_disable_unprepare(sfc->clk);
0653 err_clk:
0654     clk_disable_unprepare(sfc->hclk);
0655 err_hclk:
0656     return ret;
0657 }
0658 
0659 static int rockchip_sfc_remove(struct platform_device *pdev)
0660 {
0661     struct spi_master *master = platform_get_drvdata(pdev);
0662     struct rockchip_sfc *sfc = platform_get_drvdata(pdev);
0663 
0664     spi_unregister_master(master);
0665 
0666     clk_disable_unprepare(sfc->clk);
0667     clk_disable_unprepare(sfc->hclk);
0668 
0669     return 0;
0670 }
0671 
0672 static const struct of_device_id rockchip_sfc_dt_ids[] = {
0673     { .compatible = "rockchip,sfc"},
0674     { /* sentinel */ }
0675 };
0676 MODULE_DEVICE_TABLE(of, rockchip_sfc_dt_ids);
0677 
0678 static struct platform_driver rockchip_sfc_driver = {
0679     .driver = {
0680         .name   = "rockchip-sfc",
0681         .of_match_table = rockchip_sfc_dt_ids,
0682     },
0683     .probe  = rockchip_sfc_probe,
0684     .remove = rockchip_sfc_remove,
0685 };
0686 module_platform_driver(rockchip_sfc_driver);
0687 
0688 MODULE_LICENSE("GPL v2");
0689 MODULE_DESCRIPTION("Rockchip Serial Flash Controller Driver");
0690 MODULE_AUTHOR("Shawn Lin <shawn.lin@rock-chips.com>");
0691 MODULE_AUTHOR("Chris Morgan <macromorgan@hotmail.com>");
0692 MODULE_AUTHOR("Jon Lin <Jon.lin@rock-chips.com>");
[ Source navigation ] [ Diff markup ] [ Identifier search ] [ general search ]

This page was automatically generated by the 2.1.0 LXR engine.

The LXR team
Valid CSS 2.1! Valid HTML 4.01!