drivers/spi/spi-realtek-rtl.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002
0003 #include <linux/module.h>
0004 #include <linux/platform_device.h>
0005 #include <linux/mod_devicetable.h>
0006 #include <linux/spi/spi.h>
0007
0008 struct rtspi {
0009     void __iomem *base;
0010 };
0011
0012 /* SPI Flash Configuration Register */
0013 #define RTL_SPI_SFCR            0x00
0014 #define RTL_SPI_SFCR_RBO        BIT(28)
0015 #define RTL_SPI_SFCR_WBO        BIT(27)
0016
0017 /* SPI Flash Control and Status Register */
0018 #define RTL_SPI_SFCSR           0x08
0019 #define RTL_SPI_SFCSR_CSB0      BIT(31)
0020 #define RTL_SPI_SFCSR_CSB1      BIT(30)
0021 #define RTL_SPI_SFCSR_RDY       BIT(27)
0022 #define RTL_SPI_SFCSR_CS        BIT(24)
0023 #define RTL_SPI_SFCSR_LEN_MASK      ~(0x03 << 28)
0024 #define RTL_SPI_SFCSR_LEN1      (0x00 << 28)
0025 #define RTL_SPI_SFCSR_LEN4      (0x03 << 28)
0026
0027 /* SPI Flash Data Register */
0028 #define RTL_SPI_SFDR            0x0c
0029
0030 #define REG(x)      (rtspi->base + x)
0031
0032
0033 static void rt_set_cs(struct spi_device *spi, bool active)
0034 {
0035     struct rtspi *rtspi = spi_controller_get_devdata(spi->controller);
0036     u32 value;
0037
0038     /* CS0 bit is active low */
0039     value = readl(REG(RTL_SPI_SFCSR));
0040     if (active)
0041         value |= RTL_SPI_SFCSR_CSB0;
0042     else
0043         value &= ~RTL_SPI_SFCSR_CSB0;
0044     writel(value, REG(RTL_SPI_SFCSR));
0045 }
0046
0047 static void set_size(struct rtspi *rtspi, int size)
0048 {
0049     u32 value;
0050
0051     value = readl(REG(RTL_SPI_SFCSR));
0052     value &= RTL_SPI_SFCSR_LEN_MASK;
0053     if (size == 4)
0054         value |= RTL_SPI_SFCSR_LEN4;
0055     else if (size == 1)
0056         value |= RTL_SPI_SFCSR_LEN1;
0057     writel(value, REG(RTL_SPI_SFCSR));
0058 }
0059
0060 static inline void wait_ready(struct rtspi *rtspi)
0061 {
0062     while (!(readl(REG(RTL_SPI_SFCSR)) & RTL_SPI_SFCSR_RDY))
0063         cpu_relax();
0064 }
0065 static void send4(struct rtspi *rtspi, const u32 *buf)
0066 {
0067     wait_ready(rtspi);
0068     set_size(rtspi, 4);
0069     writel(*buf, REG(RTL_SPI_SFDR));
0070 }
0071
0072 static void send1(struct rtspi *rtspi, const u8 *buf)
0073 {
0074     wait_ready(rtspi);
0075     set_size(rtspi, 1);
0076     writel(buf[0] << 24, REG(RTL_SPI_SFDR));
0077 }
0078
0079 static void rcv4(struct rtspi *rtspi, u32 *buf)
0080 {
0081     wait_ready(rtspi);
0082     set_size(rtspi, 4);
0083     *buf = readl(REG(RTL_SPI_SFDR));
0084 }
0085
0086 static void rcv1(struct rtspi *rtspi, u8 *buf)
0087 {
0088     wait_ready(rtspi);
0089     set_size(rtspi, 1);
0090     *buf = readl(REG(RTL_SPI_SFDR)) >> 24;
0091 }
0092
0093 static int transfer_one(struct spi_controller *ctrl, struct spi_device *spi,
0094             struct spi_transfer *xfer)
0095 {
0096     struct rtspi *rtspi = spi_controller_get_devdata(ctrl);
0097     void *rx_buf;
0098     const void *tx_buf;
0099     int cnt;
0100
0101     tx_buf = xfer->tx_buf;
0102     rx_buf = xfer->rx_buf;
0103     cnt = xfer->len;
0104     if (tx_buf) {
0105         while (cnt >= 4) {
0106             send4(rtspi, tx_buf);
0107             tx_buf += 4;
0108             cnt -= 4;
0109         }
0110         while (cnt) {
0111             send1(rtspi, tx_buf);
0112             tx_buf++;
0113             cnt--;
0114         }
0115     } else if (rx_buf) {
0116         while (cnt >= 4) {
0117             rcv4(rtspi, rx_buf);
0118             rx_buf += 4;
0119             cnt -= 4;
0120         }
0121         while (cnt) {
0122             rcv1(rtspi, rx_buf);
0123             rx_buf++;
0124             cnt--;
0125         }
0126     }
0127
0128     spi_finalize_current_transfer(ctrl);
0129
0130     return 0;
0131 }
0132
0133 static void init_hw(struct rtspi *rtspi)
0134 {
0135     u32 value;
0136
0137     /* Turn on big-endian byte ordering */
0138     value = readl(REG(RTL_SPI_SFCR));
0139     value |= RTL_SPI_SFCR_RBO | RTL_SPI_SFCR_WBO;
0140     writel(value, REG(RTL_SPI_SFCR));
0141
0142     value = readl(REG(RTL_SPI_SFCSR));
0143     /* Permanently disable CS1, since it's never used */
0144     value |= RTL_SPI_SFCSR_CSB1;
0145     /* Select CS0 for use */
0146     value &= RTL_SPI_SFCSR_CS;
0147     writel(value, REG(RTL_SPI_SFCSR));
0148 }
0149
0150 static int realtek_rtl_spi_probe(struct platform_device *pdev)
0151 {
0152     struct spi_controller *ctrl;
0153     struct rtspi *rtspi;
0154     int err;
0155
0156     ctrl = devm_spi_alloc_master(&pdev->dev, sizeof(*rtspi));
0157     if (!ctrl) {
0158         dev_err(&pdev->dev, "Error allocating SPI controller\n");
0159         return -ENOMEM;
0160     }
0161     platform_set_drvdata(pdev, ctrl);
0162     rtspi = spi_controller_get_devdata(ctrl);
0163
0164     rtspi->base = devm_platform_get_and_ioremap_resource(pdev, 0, NULL);
0165     if (IS_ERR(rtspi->base)) {
0166         dev_err(&pdev->dev, "Could not map SPI register address");
0167         return -ENOMEM;
0168     }
0169
0170     init_hw(rtspi);
0171
0172     ctrl->dev.of_node = pdev->dev.of_node;
0173     ctrl->flags = SPI_CONTROLLER_HALF_DUPLEX;
0174     ctrl->set_cs = rt_set_cs;
0175     ctrl->transfer_one = transfer_one;
0176
0177     err = devm_spi_register_controller(&pdev->dev, ctrl);
0178     if (err) {
0179         dev_err(&pdev->dev, "Could not register SPI controller\n");
0180         return -ENODEV;
0181     }
0182
0183     return 0;
0184 }
0185
0186
0187 static const struct of_device_id realtek_rtl_spi_of_ids[] = {
0188     { .compatible = "realtek,rtl8380-spi" },
0189     { .compatible = "realtek,rtl8382-spi" },
0190     { .compatible = "realtek,rtl8391-spi" },
0191     { .compatible = "realtek,rtl8392-spi" },
0192     { .compatible = "realtek,rtl8393-spi" },
0193     { /* sentinel */ }
0194 };
0195 MODULE_DEVICE_TABLE(of, realtek_rtl_spi_of_ids);
0196
0197 static struct platform_driver realtek_rtl_spi_driver = {
0198     .probe = realtek_rtl_spi_probe,
0199     .driver = {
0200         .name = "realtek-rtl-spi",
0201         .of_match_table = realtek_rtl_spi_of_ids,
0202     },
0203 };
0204
0205 module_platform_driver(realtek_rtl_spi_driver);
0206
0207 MODULE_LICENSE("GPL v2");
0208 MODULE_AUTHOR("Bert Vermeulen <bert@biot.com>");
0209 MODULE_DESCRIPTION("Realtek RTL SPI driver");