drivers/spi/spi-rb4xx.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * SPI controller driver for the Mikrotik RB4xx boards
0004  *
0005  * Copyright (C) 2010 Gabor Juhos <juhosg@openwrt.org>
0006  * Copyright (C) 2015 Bert Vermeulen <bert@biot.com>
0007  *
0008  * This file was based on the patches for Linux 2.6.27.39 published by
0009  * MikroTik for their RouterBoard 4xx series devices.
0010  */
0011
0012 #include <linux/kernel.h>
0013 #include <linux/module.h>
0014 #include <linux/platform_device.h>
0015 #include <linux/clk.h>
0016 #include <linux/spi/spi.h>
0017 #include <linux/of.h>
0018
0019 #include <asm/mach-ath79/ar71xx_regs.h>
0020
0021 struct rb4xx_spi {
0022     void __iomem *base;
0023     struct clk *clk;
0024 };
0025
0026 static inline u32 rb4xx_read(struct rb4xx_spi *rbspi, u32 reg)
0027 {
0028     return __raw_readl(rbspi->base + reg);
0029 }
0030
0031 static inline void rb4xx_write(struct rb4xx_spi *rbspi, u32 reg, u32 value)
0032 {
0033     __raw_writel(value, rbspi->base + reg);
0034 }
0035
0036 static inline void do_spi_clk(struct rb4xx_spi *rbspi, u32 spi_ioc, int value)
0037 {
0038     u32 regval;
0039
0040     regval = spi_ioc;
0041     if (value & BIT(0))
0042         regval |= AR71XX_SPI_IOC_DO;
0043
0044     rb4xx_write(rbspi, AR71XX_SPI_REG_IOC, regval);
0045     rb4xx_write(rbspi, AR71XX_SPI_REG_IOC, regval | AR71XX_SPI_IOC_CLK);
0046 }
0047
0048 static void do_spi_byte(struct rb4xx_spi *rbspi, u32 spi_ioc, u8 byte)
0049 {
0050     int i;
0051
0052     for (i = 7; i >= 0; i--)
0053         do_spi_clk(rbspi, spi_ioc, byte >> i);
0054 }
0055
0056 /* The CS2 pin is used to clock in a second bit per clock cycle. */
0057 static inline void do_spi_clk_two(struct rb4xx_spi *rbspi, u32 spi_ioc,
0058                    u8 value)
0059 {
0060     u32 regval;
0061
0062     regval = spi_ioc;
0063     if (value & BIT(1))
0064         regval |= AR71XX_SPI_IOC_DO;
0065     if (value & BIT(0))
0066         regval |= AR71XX_SPI_IOC_CS2;
0067
0068     rb4xx_write(rbspi, AR71XX_SPI_REG_IOC, regval);
0069     rb4xx_write(rbspi, AR71XX_SPI_REG_IOC, regval | AR71XX_SPI_IOC_CLK);
0070 }
0071
0072 /* Two bits at a time, msb first */
0073 static void do_spi_byte_two(struct rb4xx_spi *rbspi, u32 spi_ioc, u8 byte)
0074 {
0075     do_spi_clk_two(rbspi, spi_ioc, byte >> 6);
0076     do_spi_clk_two(rbspi, spi_ioc, byte >> 4);
0077     do_spi_clk_two(rbspi, spi_ioc, byte >> 2);
0078     do_spi_clk_two(rbspi, spi_ioc, byte >> 0);
0079 }
0080
0081 static void rb4xx_set_cs(struct spi_device *spi, bool enable)
0082 {
0083     struct rb4xx_spi *rbspi = spi_master_get_devdata(spi->master);
0084
0085     /*
0086      * Setting CS is done along with bitbanging the actual values,
0087      * since it's all on the same hardware register. However the
0088      * CPLD needs CS deselected after every command.
0089      */
0090     if (enable)
0091         rb4xx_write(rbspi, AR71XX_SPI_REG_IOC,
0092                 AR71XX_SPI_IOC_CS0 | AR71XX_SPI_IOC_CS1);
0093 }
0094
0095 static int rb4xx_transfer_one(struct spi_master *master,
0096                   struct spi_device *spi, struct spi_transfer *t)
0097 {
0098     struct rb4xx_spi *rbspi = spi_master_get_devdata(master);
0099     int i;
0100     u32 spi_ioc;
0101     u8 *rx_buf;
0102     const u8 *tx_buf;
0103
0104     /*
0105      * Prime the SPI register with the SPI device selected. The m25p80 boot
0106      * flash and CPLD share the CS0 pin. This works because the CPLD's
0107      * command set was designed to almost not clash with that of the
0108      * boot flash.
0109      */
0110     if (spi->chip_select == 2)
0111         /* MMC */
0112         spi_ioc = AR71XX_SPI_IOC_CS0;
0113     else
0114         /* Boot flash and CPLD */
0115         spi_ioc = AR71XX_SPI_IOC_CS1;
0116
0117     tx_buf = t->tx_buf;
0118     rx_buf = t->rx_buf;
0119     for (i = 0; i < t->len; ++i) {
0120         if (t->tx_nbits == SPI_NBITS_DUAL)
0121             /* CPLD can use two-wire transfers */
0122             do_spi_byte_two(rbspi, spi_ioc, tx_buf[i]);
0123         else
0124             do_spi_byte(rbspi, spi_ioc, tx_buf[i]);
0125         if (!rx_buf)
0126             continue;
0127         rx_buf[i] = rb4xx_read(rbspi, AR71XX_SPI_REG_RDS);
0128     }
0129     spi_finalize_current_transfer(master);
0130
0131     return 0;
0132 }
0133
0134 static int rb4xx_spi_probe(struct platform_device *pdev)
0135 {
0136     struct spi_master *master;
0137     struct clk *ahb_clk;
0138     struct rb4xx_spi *rbspi;
0139     int err;
0140     void __iomem *spi_base;
0141
0142     spi_base = devm_platform_ioremap_resource(pdev, 0);
0143     if (IS_ERR(spi_base))
0144         return PTR_ERR(spi_base);
0145
0146     master = devm_spi_alloc_master(&pdev->dev, sizeof(*rbspi));
0147     if (!master)
0148         return -ENOMEM;
0149
0150     ahb_clk = devm_clk_get(&pdev->dev, "ahb");
0151     if (IS_ERR(ahb_clk))
0152         return PTR_ERR(ahb_clk);
0153
0154     master->dev.of_node = pdev->dev.of_node;
0155     master->bus_num = 0;
0156     master->num_chipselect = 3;
0157     master->mode_bits = SPI_TX_DUAL;
0158     master->bits_per_word_mask = SPI_BPW_MASK(8);
0159     master->flags = SPI_MASTER_MUST_TX;
0160     master->transfer_one = rb4xx_transfer_one;
0161     master->set_cs = rb4xx_set_cs;
0162
0163     rbspi = spi_master_get_devdata(master);
0164     rbspi->base = spi_base;
0165     rbspi->clk = ahb_clk;
0166     platform_set_drvdata(pdev, rbspi);
0167
0168     err = devm_spi_register_master(&pdev->dev, master);
0169     if (err) {
0170         dev_err(&pdev->dev, "failed to register SPI master\n");
0171         return err;
0172     }
0173
0174     err = clk_prepare_enable(ahb_clk);
0175     if (err)
0176         return err;
0177
0178     /* Enable SPI */
0179     rb4xx_write(rbspi, AR71XX_SPI_REG_FS, AR71XX_SPI_FS_GPIO);
0180
0181     return 0;
0182 }
0183
0184 static int rb4xx_spi_remove(struct platform_device *pdev)
0185 {
0186     struct rb4xx_spi *rbspi = platform_get_drvdata(pdev);
0187
0188     clk_disable_unprepare(rbspi->clk);
0189
0190     return 0;
0191 }
0192
0193 static const struct of_device_id rb4xx_spi_dt_match[] = {
0194     { .compatible = "mikrotik,rb4xx-spi" },
0195     { },
0196 };
0197 MODULE_DEVICE_TABLE(of, rb4xx_spi_dt_match);
0198
0199 static struct platform_driver rb4xx_spi_drv = {
0200     .probe = rb4xx_spi_probe,
0201     .remove = rb4xx_spi_remove,
0202     .driver = {
0203         .name = "rb4xx-spi",
0204         .of_match_table = of_match_ptr(rb4xx_spi_dt_match),
0205     },
0206 };
0207
0208 module_platform_driver(rb4xx_spi_drv);
0209
0210 MODULE_DESCRIPTION("Mikrotik RB4xx SPI controller driver");
0211 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
0212 MODULE_AUTHOR("Bert Vermeulen <bert@biot.com>");
0213 MODULE_LICENSE("GPL v2");