drivers/spi/spi-pxa2xx.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs
0004  * Copyright (C) 2013, 2021 Intel Corporation
0005  */
0006
0007 #ifndef SPI_PXA2XX_H
0008 #define SPI_PXA2XX_H
0009
0010 #include <linux/interrupt.h>
0011 #include <linux/io.h>
0012 #include <linux/types.h>
0013 #include <linux/sizes.h>
0014
0015 #include <linux/pxa2xx_ssp.h>
0016
0017 struct gpio_desc;
0018 struct pxa2xx_spi_controller;
0019 struct spi_controller;
0020 struct spi_device;
0021 struct spi_transfer;
0022
0023 struct driver_data {
0024     /* SSP Info */
0025     struct ssp_device *ssp;
0026
0027     /* SPI framework hookup */
0028     enum pxa_ssp_type ssp_type;
0029     struct spi_controller *controller;
0030
0031     /* PXA hookup */
0032     struct pxa2xx_spi_controller *controller_info;
0033
0034     /* SSP masks*/
0035     u32 dma_cr1;
0036     u32 int_cr1;
0037     u32 clear_sr;
0038     u32 mask_sr;
0039
0040     /* DMA engine support */
0041     atomic_t dma_running;
0042
0043     /* Current transfer state info */
0044     void *tx;
0045     void *tx_end;
0046     void *rx;
0047     void *rx_end;
0048     u8 n_bytes;
0049     int (*write)(struct driver_data *drv_data);
0050     int (*read)(struct driver_data *drv_data);
0051     irqreturn_t (*transfer_handler)(struct driver_data *drv_data);
0052
0053     void __iomem *lpss_base;
0054
0055     /* Optional slave FIFO ready signal */
0056     struct gpio_desc *gpiod_ready;
0057 };
0058
0059 struct chip_data {
0060     u32 cr1;
0061     u32 dds_rate;
0062     u32 timeout;
0063     u8 enable_dma;
0064     u32 dma_burst_size;
0065     u32 dma_threshold;
0066     u32 threshold;
0067     u16 lpss_rx_threshold;
0068     u16 lpss_tx_threshold;
0069 };
0070
0071 static inline u32 pxa2xx_spi_read(const struct driver_data *drv_data, u32 reg)
0072 {
0073     return pxa_ssp_read_reg(drv_data->ssp, reg);
0074 }
0075
0076 static inline void pxa2xx_spi_write(const struct driver_data *drv_data, u32 reg, u32 val)
0077 {
0078     pxa_ssp_write_reg(drv_data->ssp, reg, val);
0079 }
0080
0081 #define DMA_ALIGNMENT       8
0082
0083 static inline int pxa25x_ssp_comp(const struct driver_data *drv_data)
0084 {
0085     switch (drv_data->ssp_type) {
0086     case PXA25x_SSP:
0087     case CE4100_SSP:
0088     case QUARK_X1000_SSP:
0089         return 1;
0090     default:
0091         return 0;
0092     }
0093 }
0094
0095 static inline void clear_SSCR1_bits(const struct driver_data *drv_data, u32 bits)
0096 {
0097     pxa2xx_spi_write(drv_data, SSCR1, pxa2xx_spi_read(drv_data, SSCR1) & ~bits);
0098 }
0099
0100 static inline u32 read_SSSR_bits(const struct driver_data *drv_data, u32 bits)
0101 {
0102     return pxa2xx_spi_read(drv_data, SSSR) & bits;
0103 }
0104
0105 static inline void write_SSSR_CS(const struct driver_data *drv_data, u32 val)
0106 {
0107     if (drv_data->ssp_type == CE4100_SSP ||
0108         drv_data->ssp_type == QUARK_X1000_SSP)
0109         val |= read_SSSR_bits(drv_data, SSSR_ALT_FRM_MASK);
0110
0111     pxa2xx_spi_write(drv_data, SSSR, val);
0112 }
0113
0114 extern int pxa2xx_spi_flush(struct driver_data *drv_data);
0115
0116 #define MAX_DMA_LEN     SZ_64K
0117 #define DEFAULT_DMA_CR1     (SSCR1_TSRE | SSCR1_RSRE | SSCR1_TRAIL)
0118
0119 extern irqreturn_t pxa2xx_spi_dma_transfer(struct driver_data *drv_data);
0120 extern int pxa2xx_spi_dma_prepare(struct driver_data *drv_data,
0121                   struct spi_transfer *xfer);
0122 extern void pxa2xx_spi_dma_start(struct driver_data *drv_data);
0123 extern void pxa2xx_spi_dma_stop(struct driver_data *drv_data);
0124 extern int pxa2xx_spi_dma_setup(struct driver_data *drv_data);
0125 extern void pxa2xx_spi_dma_release(struct driver_data *drv_data);
0126 extern int pxa2xx_spi_set_dma_burst_and_threshold(struct chip_data *chip,
0127                           struct spi_device *spi,
0128                           u8 bits_per_word,
0129                           u32 *burst_code,
0130                           u32 *threshold);
0131
0132 #endif /* SPI_PXA2XX_H */