drivers/spi/spi-ppc4xx.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * SPI_PPC4XX SPI controller driver.
0004  *
0005  * Copyright (C) 2007 Gary Jennejohn <garyj@denx.de>
0006  * Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering
0007  * Copyright 2009 Harris Corporation, Steven A. Falco <sfalco@harris.com>
0008  *
0009  * Based in part on drivers/spi/spi_s3c24xx.c
0010  *
0011  * Copyright (c) 2006 Ben Dooks
0012  * Copyright (c) 2006 Simtec Electronics
0013  *  Ben Dooks <ben@simtec.co.uk>
0014  */
0015
0016 /*
0017  * The PPC4xx SPI controller has no FIFO so each sent/received byte will
0018  * generate an interrupt to the CPU. This can cause high CPU utilization.
0019  * This driver allows platforms to reduce the interrupt load on the CPU
0020  * during SPI transfers by setting max_speed_hz via the device tree.
0021  */
0022
0023 #include <linux/module.h>
0024 #include <linux/sched.h>
0025 #include <linux/slab.h>
0026 #include <linux/errno.h>
0027 #include <linux/wait.h>
0028 #include <linux/of_address.h>
0029 #include <linux/of_irq.h>
0030 #include <linux/of_platform.h>
0031 #include <linux/interrupt.h>
0032 #include <linux/delay.h>
0033
0034 #include <linux/spi/spi.h>
0035 #include <linux/spi/spi_bitbang.h>
0036
0037 #include <linux/io.h>
0038 #include <asm/dcr.h>
0039 #include <asm/dcr-regs.h>
0040
0041 /* bits in mode register - bit 0 is MSb */
0042
0043 /*
0044  * SPI_PPC4XX_MODE_SCP = 0 means "data latched on trailing edge of clock"
0045  * SPI_PPC4XX_MODE_SCP = 1 means "data latched on leading edge of clock"
0046  * Note: This is the inverse of CPHA.
0047  */
0048 #define SPI_PPC4XX_MODE_SCP (0x80 >> 3)
0049
0050 /* SPI_PPC4XX_MODE_SPE = 1 means "port enabled" */
0051 #define SPI_PPC4XX_MODE_SPE (0x80 >> 4)
0052
0053 /*
0054  * SPI_PPC4XX_MODE_RD = 0 means "MSB first" - this is the normal mode
0055  * SPI_PPC4XX_MODE_RD = 1 means "LSB first" - this is bit-reversed mode
0056  * Note: This is identical to SPI_LSB_FIRST.
0057  */
0058 #define SPI_PPC4XX_MODE_RD  (0x80 >> 5)
0059
0060 /*
0061  * SPI_PPC4XX_MODE_CI = 0 means "clock idles low"
0062  * SPI_PPC4XX_MODE_CI = 1 means "clock idles high"
0063  * Note: This is identical to CPOL.
0064  */
0065 #define SPI_PPC4XX_MODE_CI  (0x80 >> 6)
0066
0067 /*
0068  * SPI_PPC4XX_MODE_IL = 0 means "loopback disable"
0069  * SPI_PPC4XX_MODE_IL = 1 means "loopback enable"
0070  */
0071 #define SPI_PPC4XX_MODE_IL  (0x80 >> 7)
0072
0073 /* bits in control register */
0074 /* starts a transfer when set */
0075 #define SPI_PPC4XX_CR_STR   (0x80 >> 7)
0076
0077 /* bits in status register */
0078 /* port is busy with a transfer */
0079 #define SPI_PPC4XX_SR_BSY   (0x80 >> 6)
0080 /* RxD ready */
0081 #define SPI_PPC4XX_SR_RBR   (0x80 >> 7)
0082
0083 /* clock settings (SCP and CI) for various SPI modes */
0084 #define SPI_CLK_MODE0   (SPI_PPC4XX_MODE_SCP | 0)
0085 #define SPI_CLK_MODE1   (0 | 0)
0086 #define SPI_CLK_MODE2   (SPI_PPC4XX_MODE_SCP | SPI_PPC4XX_MODE_CI)
0087 #define SPI_CLK_MODE3   (0 | SPI_PPC4XX_MODE_CI)
0088
0089 #define DRIVER_NAME "spi_ppc4xx_of"
0090
0091 struct spi_ppc4xx_regs {
0092     u8 mode;
0093     u8 rxd;
0094     u8 txd;
0095     u8 cr;
0096     u8 sr;
0097     u8 dummy;
0098     /*
0099      * Clock divisor modulus register
0100      * This uses the following formula:
0101      *    SCPClkOut = OPBCLK/(4(CDM + 1))
0102      * or
0103      *    CDM = (OPBCLK/4*SCPClkOut) - 1
0104      * bit 0 is the MSb!
0105      */
0106     u8 cdm;
0107 };
0108
0109 /* SPI Controller driver's private data. */
0110 struct ppc4xx_spi {
0111     /* bitbang has to be first */
0112     struct spi_bitbang bitbang;
0113     struct completion done;
0114
0115     u64 mapbase;
0116     u64 mapsize;
0117     int irqnum;
0118     /* need this to set the SPI clock */
0119     unsigned int opb_freq;
0120
0121     /* for transfers */
0122     int len;
0123     int count;
0124     /* data buffers */
0125     const unsigned char *tx;
0126     unsigned char *rx;
0127
0128     struct spi_ppc4xx_regs __iomem *regs; /* pointer to the registers */
0129     struct spi_master *master;
0130     struct device *dev;
0131 };
0132
0133 /* need this so we can set the clock in the chipselect routine */
0134 struct spi_ppc4xx_cs {
0135     u8 mode;
0136 };
0137
0138 static int spi_ppc4xx_txrx(struct spi_device *spi, struct spi_transfer *t)
0139 {
0140     struct ppc4xx_spi *hw;
0141     u8 data;
0142
0143     dev_dbg(&spi->dev, "txrx: tx %p, rx %p, len %d\n",
0144         t->tx_buf, t->rx_buf, t->len);
0145
0146     hw = spi_master_get_devdata(spi->master);
0147
0148     hw->tx = t->tx_buf;
0149     hw->rx = t->rx_buf;
0150     hw->len = t->len;
0151     hw->count = 0;
0152
0153     /* send the first byte */
0154     data = hw->tx ? hw->tx[0] : 0;
0155     out_8(&hw->regs->txd, data);
0156     out_8(&hw->regs->cr, SPI_PPC4XX_CR_STR);
0157     wait_for_completion(&hw->done);
0158
0159     return hw->count;
0160 }
0161
0162 static int spi_ppc4xx_setupxfer(struct spi_device *spi, struct spi_transfer *t)
0163 {
0164     struct ppc4xx_spi *hw = spi_master_get_devdata(spi->master);
0165     struct spi_ppc4xx_cs *cs = spi->controller_state;
0166     int scr;
0167     u8 cdm = 0;
0168     u32 speed;
0169     u8 bits_per_word;
0170
0171     /* Start with the generic configuration for this device. */
0172     bits_per_word = spi->bits_per_word;
0173     speed = spi->max_speed_hz;
0174
0175     /*
0176      * Modify the configuration if the transfer overrides it.  Do not allow
0177      * the transfer to overwrite the generic configuration with zeros.
0178      */
0179     if (t) {
0180         if (t->bits_per_word)
0181             bits_per_word = t->bits_per_word;
0182
0183         if (t->speed_hz)
0184             speed = min(t->speed_hz, spi->max_speed_hz);
0185     }
0186
0187     if (!speed || (speed > spi->max_speed_hz)) {
0188         dev_err(&spi->dev, "invalid speed_hz (%d)\n", speed);
0189         return -EINVAL;
0190     }
0191
0192     /* Write new configuration */
0193     out_8(&hw->regs->mode, cs->mode);
0194
0195     /* Set the clock */
0196     /* opb_freq was already divided by 4 */
0197     scr = (hw->opb_freq / speed) - 1;
0198     if (scr > 0)
0199         cdm = min(scr, 0xff);
0200
0201     dev_dbg(&spi->dev, "setting pre-scaler to %d (hz %d)\n", cdm, speed);
0202
0203     if (in_8(&hw->regs->cdm) != cdm)
0204         out_8(&hw->regs->cdm, cdm);
0205
0206     mutex_lock(&hw->bitbang.lock);
0207     if (!hw->bitbang.busy) {
0208         hw->bitbang.chipselect(spi, BITBANG_CS_INACTIVE);
0209         /* Need to ndelay here? */
0210     }
0211     mutex_unlock(&hw->bitbang.lock);
0212
0213     return 0;
0214 }
0215
0216 static int spi_ppc4xx_setup(struct spi_device *spi)
0217 {
0218     struct spi_ppc4xx_cs *cs = spi->controller_state;
0219
0220     if (!spi->max_speed_hz) {
0221         dev_err(&spi->dev, "invalid max_speed_hz (must be non-zero)\n");
0222         return -EINVAL;
0223     }
0224
0225     if (cs == NULL) {
0226         cs = kzalloc(sizeof(*cs), GFP_KERNEL);
0227         if (!cs)
0228             return -ENOMEM;
0229         spi->controller_state = cs;
0230     }
0231
0232     /*
0233      * We set all bits of the SPI0_MODE register, so,
0234      * no need to read-modify-write
0235      */
0236     cs->mode = SPI_PPC4XX_MODE_SPE;
0237
0238     switch (spi->mode & SPI_MODE_X_MASK) {
0239     case SPI_MODE_0:
0240         cs->mode |= SPI_CLK_MODE0;
0241         break;
0242     case SPI_MODE_1:
0243         cs->mode |= SPI_CLK_MODE1;
0244         break;
0245     case SPI_MODE_2:
0246         cs->mode |= SPI_CLK_MODE2;
0247         break;
0248     case SPI_MODE_3:
0249         cs->mode |= SPI_CLK_MODE3;
0250         break;
0251     }
0252
0253     if (spi->mode & SPI_LSB_FIRST)
0254         cs->mode |= SPI_PPC4XX_MODE_RD;
0255
0256     return 0;
0257 }
0258
0259 static irqreturn_t spi_ppc4xx_int(int irq, void *dev_id)
0260 {
0261     struct ppc4xx_spi *hw;
0262     u8 status;
0263     u8 data;
0264     unsigned int count;
0265
0266     hw = (struct ppc4xx_spi *)dev_id;
0267
0268     status = in_8(&hw->regs->sr);
0269     if (!status)
0270         return IRQ_NONE;
0271
0272     /*
0273      * BSY de-asserts one cycle after the transfer is complete.  The
0274      * interrupt is asserted after the transfer is complete.  The exact
0275      * relationship is not documented, hence this code.
0276      */
0277
0278     if (unlikely(status & SPI_PPC4XX_SR_BSY)) {
0279         u8 lstatus;
0280         int cnt = 0;
0281
0282         dev_dbg(hw->dev, "got interrupt but spi still busy?\n");
0283         do {
0284             ndelay(10);
0285             lstatus = in_8(&hw->regs->sr);
0286         } while (++cnt < 100 && lstatus & SPI_PPC4XX_SR_BSY);
0287
0288         if (cnt >= 100) {
0289             dev_err(hw->dev, "busywait: too many loops!\n");
0290             complete(&hw->done);
0291             return IRQ_HANDLED;
0292         } else {
0293             /* status is always 1 (RBR) here */
0294             status = in_8(&hw->regs->sr);
0295             dev_dbg(hw->dev, "loops %d status %x\n", cnt, status);
0296         }
0297     }
0298
0299     count = hw->count;
0300     hw->count++;
0301
0302     /* RBR triggered this interrupt.  Therefore, data must be ready. */
0303     data = in_8(&hw->regs->rxd);
0304     if (hw->rx)
0305         hw->rx[count] = data;
0306
0307     count++;
0308
0309     if (count < hw->len) {
0310         data = hw->tx ? hw->tx[count] : 0;
0311         out_8(&hw->regs->txd, data);
0312         out_8(&hw->regs->cr, SPI_PPC4XX_CR_STR);
0313     } else {
0314         complete(&hw->done);
0315     }
0316
0317     return IRQ_HANDLED;
0318 }
0319
0320 static void spi_ppc4xx_cleanup(struct spi_device *spi)
0321 {
0322     kfree(spi->controller_state);
0323 }
0324
0325 static void spi_ppc4xx_enable(struct ppc4xx_spi *hw)
0326 {
0327     /*
0328      * On all 4xx PPC's the SPI bus is shared/multiplexed with
0329      * the 2nd I2C bus. We need to enable the SPI bus before
0330      * using it.
0331      */
0332
0333     /* need to clear bit 14 to enable SPC */
0334     dcri_clrset(SDR0, SDR0_PFC1, 0x80000000 >> 14, 0);
0335 }
0336
0337 /*
0338  * platform_device layer stuff...
0339  */
0340 static int spi_ppc4xx_of_probe(struct platform_device *op)
0341 {
0342     struct ppc4xx_spi *hw;
0343     struct spi_master *master;
0344     struct spi_bitbang *bbp;
0345     struct resource resource;
0346     struct device_node *np = op->dev.of_node;
0347     struct device *dev = &op->dev;
0348     struct device_node *opbnp;
0349     int ret;
0350     const unsigned int *clk;
0351
0352     master = spi_alloc_master(dev, sizeof(*hw));
0353     if (master == NULL)
0354         return -ENOMEM;
0355     master->dev.of_node = np;
0356     platform_set_drvdata(op, master);
0357     hw = spi_master_get_devdata(master);
0358     hw->master = master;
0359     hw->dev = dev;
0360
0361     init_completion(&hw->done);
0362
0363     /* Setup the state for the bitbang driver */
0364     bbp = &hw->bitbang;
0365     bbp->master = hw->master;
0366     bbp->setup_transfer = spi_ppc4xx_setupxfer;
0367     bbp->txrx_bufs = spi_ppc4xx_txrx;
0368     bbp->use_dma = 0;
0369     bbp->master->setup = spi_ppc4xx_setup;
0370     bbp->master->cleanup = spi_ppc4xx_cleanup;
0371     bbp->master->bits_per_word_mask = SPI_BPW_MASK(8);
0372     bbp->master->use_gpio_descriptors = true;
0373     /*
0374      * The SPI core will count the number of GPIO descriptors to figure
0375      * out the number of chip selects available on the platform.
0376      */
0377     bbp->master->num_chipselect = 0;
0378
0379     /* the spi->mode bits understood by this driver: */
0380     bbp->master->mode_bits =
0381         SPI_CPHA | SPI_CPOL | SPI_CS_HIGH | SPI_LSB_FIRST;
0382
0383     /* Get the clock for the OPB */
0384     opbnp = of_find_compatible_node(NULL, NULL, "ibm,opb");
0385     if (opbnp == NULL) {
0386         dev_err(dev, "OPB: cannot find node\n");
0387         ret = -ENODEV;
0388         goto free_master;
0389     }
0390     /* Get the clock (Hz) for the OPB */
0391     clk = of_get_property(opbnp, "clock-frequency", NULL);
0392     if (clk == NULL) {
0393         dev_err(dev, "OPB: no clock-frequency property set\n");
0394         of_node_put(opbnp);
0395         ret = -ENODEV;
0396         goto free_master;
0397     }
0398     hw->opb_freq = *clk;
0399     hw->opb_freq >>= 2;
0400     of_node_put(opbnp);
0401
0402     ret = of_address_to_resource(np, 0, &resource);
0403     if (ret) {
0404         dev_err(dev, "error while parsing device node resource\n");
0405         goto free_master;
0406     }
0407     hw->mapbase = resource.start;
0408     hw->mapsize = resource_size(&resource);
0409
0410     /* Sanity check */
0411     if (hw->mapsize < sizeof(struct spi_ppc4xx_regs)) {
0412         dev_err(dev, "too small to map registers\n");
0413         ret = -EINVAL;
0414         goto free_master;
0415     }
0416
0417     /* Request IRQ */
0418     hw->irqnum = irq_of_parse_and_map(np, 0);
0419     ret = request_irq(hw->irqnum, spi_ppc4xx_int,
0420               0, "spi_ppc4xx_of", (void *)hw);
0421     if (ret) {
0422         dev_err(dev, "unable to allocate interrupt\n");
0423         goto free_master;
0424     }
0425
0426     if (!request_mem_region(hw->mapbase, hw->mapsize, DRIVER_NAME)) {
0427         dev_err(dev, "resource unavailable\n");
0428         ret = -EBUSY;
0429         goto request_mem_error;
0430     }
0431
0432     hw->regs = ioremap(hw->mapbase, sizeof(struct spi_ppc4xx_regs));
0433
0434     if (!hw->regs) {
0435         dev_err(dev, "unable to memory map registers\n");
0436         ret = -ENXIO;
0437         goto map_io_error;
0438     }
0439
0440     spi_ppc4xx_enable(hw);
0441
0442     /* Finally register our spi controller */
0443     dev->dma_mask = 0;
0444     ret = spi_bitbang_start(bbp);
0445     if (ret) {
0446         dev_err(dev, "failed to register SPI master\n");
0447         goto unmap_regs;
0448     }
0449
0450     dev_info(dev, "driver initialized\n");
0451
0452     return 0;
0453
0454 unmap_regs:
0455     iounmap(hw->regs);
0456 map_io_error:
0457     release_mem_region(hw->mapbase, hw->mapsize);
0458 request_mem_error:
0459     free_irq(hw->irqnum, hw);
0460 free_master:
0461     spi_master_put(master);
0462
0463     dev_err(dev, "initialization failed\n");
0464     return ret;
0465 }
0466
0467 static int spi_ppc4xx_of_remove(struct platform_device *op)
0468 {
0469     struct spi_master *master = platform_get_drvdata(op);
0470     struct ppc4xx_spi *hw = spi_master_get_devdata(master);
0471
0472     spi_bitbang_stop(&hw->bitbang);
0473     release_mem_region(hw->mapbase, hw->mapsize);
0474     free_irq(hw->irqnum, hw);
0475     iounmap(hw->regs);
0476     spi_master_put(master);
0477     return 0;
0478 }
0479
0480 static const struct of_device_id spi_ppc4xx_of_match[] = {
0481     { .compatible = "ibm,ppc4xx-spi", },
0482     {},
0483 };
0484
0485 MODULE_DEVICE_TABLE(of, spi_ppc4xx_of_match);
0486
0487 static struct platform_driver spi_ppc4xx_of_driver = {
0488     .probe = spi_ppc4xx_of_probe,
0489     .remove = spi_ppc4xx_of_remove,
0490     .driver = {
0491         .name = DRIVER_NAME,
0492         .of_match_table = spi_ppc4xx_of_match,
0493     },
0494 };
0495 module_platform_driver(spi_ppc4xx_of_driver);
0496
0497 MODULE_AUTHOR("Gary Jennejohn & Stefan Roese");
0498 MODULE_DESCRIPTION("Simple PPC4xx SPI Driver");
0499 MODULE_LICENSE("GPL");