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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Microchip PIC32 SPI controller driver.
0004  *
0005  * Purna Chandra Mandal <purna.mandal@microchip.com>
0006  * Copyright (c) 2016, Microchip Technology Inc.
0007  */
0008 
0009 #include <linux/clk.h>
0010 #include <linux/clkdev.h>
0011 #include <linux/delay.h>
0012 #include <linux/dmaengine.h>
0013 #include <linux/dma-mapping.h>
0014 #include <linux/highmem.h>
0015 #include <linux/module.h>
0016 #include <linux/io.h>
0017 #include <linux/interrupt.h>
0018 #include <linux/of.h>
0019 #include <linux/of_irq.h>
0020 #include <linux/of_gpio.h>
0021 #include <linux/of_address.h>
0022 #include <linux/platform_device.h>
0023 #include <linux/spi/spi.h>
0024 
0025 /* SPI controller registers */
0026 struct pic32_spi_regs {
0027     u32 ctrl;
0028     u32 ctrl_clr;
0029     u32 ctrl_set;
0030     u32 ctrl_inv;
0031     u32 status;
0032     u32 status_clr;
0033     u32 status_set;
0034     u32 status_inv;
0035     u32 buf;
0036     u32 dontuse[3];
0037     u32 baud;
0038     u32 dontuse2[3];
0039     u32 ctrl2;
0040     u32 ctrl2_clr;
0041     u32 ctrl2_set;
0042     u32 ctrl2_inv;
0043 };
0044 
0045 /* Bit fields of SPI Control Register */
0046 #define CTRL_RX_INT_SHIFT   0  /* Rx interrupt generation */
0047 #define  RX_FIFO_EMPTY      0
0048 #define  RX_FIFO_NOT_EMPTY  1 /* not empty */
0049 #define  RX_FIFO_HALF_FULL  2 /* full by half or more */
0050 #define  RX_FIFO_FULL       3 /* completely full */
0051 
0052 #define CTRL_TX_INT_SHIFT   2  /* TX interrupt generation */
0053 #define  TX_FIFO_ALL_EMPTY  0 /* completely empty */
0054 #define  TX_FIFO_EMPTY      1 /* empty */
0055 #define  TX_FIFO_HALF_EMPTY 2 /* empty by half or more */
0056 #define  TX_FIFO_NOT_FULL   3 /* atleast one empty */
0057 
0058 #define CTRL_MSTEN  BIT(5) /* enable master mode */
0059 #define CTRL_CKP    BIT(6) /* active low */
0060 #define CTRL_CKE    BIT(8) /* Tx on falling edge */
0061 #define CTRL_SMP    BIT(9) /* Rx at middle or end of tx */
0062 #define CTRL_BPW_MASK   0x03   /* bits per word/sample */
0063 #define CTRL_BPW_SHIFT  10
0064 #define  PIC32_BPW_8    0
0065 #define  PIC32_BPW_16   1
0066 #define  PIC32_BPW_32   2
0067 #define CTRL_SIDL   BIT(13) /* sleep when idle */
0068 #define CTRL_ON     BIT(15) /* enable macro */
0069 #define CTRL_ENHBUF BIT(16) /* enable enhanced buffering */
0070 #define CTRL_MCLKSEL    BIT(23) /* select clock source */
0071 #define CTRL_MSSEN  BIT(28) /* macro driven /SS */
0072 #define CTRL_FRMEN  BIT(31) /* enable framing mode */
0073 
0074 /* Bit fields of SPI Status Register */
0075 #define STAT_RF_EMPTY   BIT(5) /* RX Fifo empty */
0076 #define STAT_RX_OV  BIT(6) /* err, s/w needs to clear */
0077 #define STAT_TX_UR  BIT(8) /* UR in Framed SPI modes */
0078 #define STAT_FRM_ERR    BIT(12) /* Multiple Frame Sync pulse */
0079 #define STAT_TF_LVL_MASK    0x1F
0080 #define STAT_TF_LVL_SHIFT   16
0081 #define STAT_RF_LVL_MASK    0x1F
0082 #define STAT_RF_LVL_SHIFT   24
0083 
0084 /* Bit fields of SPI Baud Register */
0085 #define BAUD_MASK       0x1ff
0086 
0087 /* Bit fields of SPI Control2 Register */
0088 #define CTRL2_TX_UR_EN      BIT(10) /* Enable int on Tx under-run */
0089 #define CTRL2_RX_OV_EN      BIT(11) /* Enable int on Rx over-run */
0090 #define CTRL2_FRM_ERR_EN    BIT(12) /* Enable frame err int */
0091 
0092 /* Minimum DMA transfer size */
0093 #define PIC32_DMA_LEN_MIN   64
0094 
0095 struct pic32_spi {
0096     dma_addr_t      dma_base;
0097     struct pic32_spi_regs __iomem *regs;
0098     int         fault_irq;
0099     int         rx_irq;
0100     int         tx_irq;
0101     u32         fifo_n_byte; /* FIFO depth in bytes */
0102     struct clk      *clk;
0103     struct spi_master   *master;
0104     /* Current controller setting */
0105     u32         speed_hz; /* spi-clk rate */
0106     u32         mode;
0107     u32         bits_per_word;
0108     u32         fifo_n_elm; /* FIFO depth in words */
0109 #define PIC32F_DMA_PREP     0 /* DMA chnls configured */
0110     unsigned long       flags;
0111     /* Current transfer state */
0112     struct completion   xfer_done;
0113     /* PIO transfer specific */
0114     const void      *tx;
0115     const void      *tx_end;
0116     const void      *rx;
0117     const void      *rx_end;
0118     int         len;
0119     void (*rx_fifo)(struct pic32_spi *);
0120     void (*tx_fifo)(struct pic32_spi *);
0121 };
0122 
0123 static inline void pic32_spi_enable(struct pic32_spi *pic32s)
0124 {
0125     writel(CTRL_ON | CTRL_SIDL, &pic32s->regs->ctrl_set);
0126 }
0127 
0128 static inline void pic32_spi_disable(struct pic32_spi *pic32s)
0129 {
0130     writel(CTRL_ON | CTRL_SIDL, &pic32s->regs->ctrl_clr);
0131 
0132     /* avoid SPI registers read/write at immediate next CPU clock */
0133     ndelay(20);
0134 }
0135 
0136 static void pic32_spi_set_clk_rate(struct pic32_spi *pic32s, u32 spi_ck)
0137 {
0138     u32 div;
0139 
0140     /* div = (clk_in / 2 * spi_ck) - 1 */
0141     div = DIV_ROUND_CLOSEST(clk_get_rate(pic32s->clk), 2 * spi_ck) - 1;
0142 
0143     writel(div & BAUD_MASK, &pic32s->regs->baud);
0144 }
0145 
0146 static inline u32 pic32_rx_fifo_level(struct pic32_spi *pic32s)
0147 {
0148     u32 sr = readl(&pic32s->regs->status);
0149 
0150     return (sr >> STAT_RF_LVL_SHIFT) & STAT_RF_LVL_MASK;
0151 }
0152 
0153 static inline u32 pic32_tx_fifo_level(struct pic32_spi *pic32s)
0154 {
0155     u32 sr = readl(&pic32s->regs->status);
0156 
0157     return (sr >> STAT_TF_LVL_SHIFT) & STAT_TF_LVL_MASK;
0158 }
0159 
0160 /* Return the max entries we can fill into tx fifo */
0161 static u32 pic32_tx_max(struct pic32_spi *pic32s, int n_bytes)
0162 {
0163     u32 tx_left, tx_room, rxtx_gap;
0164 
0165     tx_left = (pic32s->tx_end - pic32s->tx) / n_bytes;
0166     tx_room = pic32s->fifo_n_elm - pic32_tx_fifo_level(pic32s);
0167 
0168     /*
0169      * Another concern is about the tx/rx mismatch, we
0170      * though to use (pic32s->fifo_n_byte - rxfl - txfl) as
0171      * one maximum value for tx, but it doesn't cover the
0172      * data which is out of tx/rx fifo and inside the
0173      * shift registers. So a ctrl from sw point of
0174      * view is taken.
0175      */
0176     rxtx_gap = ((pic32s->rx_end - pic32s->rx) -
0177             (pic32s->tx_end - pic32s->tx)) / n_bytes;
0178     return min3(tx_left, tx_room, (u32)(pic32s->fifo_n_elm - rxtx_gap));
0179 }
0180 
0181 /* Return the max entries we should read out of rx fifo */
0182 static u32 pic32_rx_max(struct pic32_spi *pic32s, int n_bytes)
0183 {
0184     u32 rx_left = (pic32s->rx_end - pic32s->rx) / n_bytes;
0185 
0186     return min_t(u32, rx_left, pic32_rx_fifo_level(pic32s));
0187 }
0188 
0189 #define BUILD_SPI_FIFO_RW(__name, __type, __bwl)        \
0190 static void pic32_spi_rx_##__name(struct pic32_spi *pic32s) \
0191 {                               \
0192     __type v;                       \
0193     u32 mx = pic32_rx_max(pic32s, sizeof(__type));      \
0194     for (; mx; mx--) {                  \
0195         v = read##__bwl(&pic32s->regs->buf);        \
0196         if (pic32s->rx_end - pic32s->len)       \
0197             *(__type *)(pic32s->rx) = v;        \
0198         pic32s->rx += sizeof(__type);           \
0199     }                           \
0200 }                               \
0201                                 \
0202 static void pic32_spi_tx_##__name(struct pic32_spi *pic32s) \
0203 {                               \
0204     __type v;                       \
0205     u32 mx = pic32_tx_max(pic32s, sizeof(__type));      \
0206     for (; mx ; mx--) {                 \
0207         v = (__type)~0U;                \
0208         if (pic32s->tx_end - pic32s->len)       \
0209             v = *(__type *)(pic32s->tx);        \
0210         write##__bwl(v, &pic32s->regs->buf);        \
0211         pic32s->tx += sizeof(__type);           \
0212     }                           \
0213 }
0214 
0215 BUILD_SPI_FIFO_RW(byte, u8, b);
0216 BUILD_SPI_FIFO_RW(word, u16, w);
0217 BUILD_SPI_FIFO_RW(dword, u32, l);
0218 
0219 static void pic32_err_stop(struct pic32_spi *pic32s, const char *msg)
0220 {
0221     /* disable all interrupts */
0222     disable_irq_nosync(pic32s->fault_irq);
0223     disable_irq_nosync(pic32s->rx_irq);
0224     disable_irq_nosync(pic32s->tx_irq);
0225 
0226     /* Show err message and abort xfer with err */
0227     dev_err(&pic32s->master->dev, "%s\n", msg);
0228     if (pic32s->master->cur_msg)
0229         pic32s->master->cur_msg->status = -EIO;
0230     complete(&pic32s->xfer_done);
0231 }
0232 
0233 static irqreturn_t pic32_spi_fault_irq(int irq, void *dev_id)
0234 {
0235     struct pic32_spi *pic32s = dev_id;
0236     u32 status;
0237 
0238     status = readl(&pic32s->regs->status);
0239 
0240     /* Error handling */
0241     if (status & (STAT_RX_OV | STAT_TX_UR)) {
0242         writel(STAT_RX_OV, &pic32s->regs->status_clr);
0243         writel(STAT_TX_UR, &pic32s->regs->status_clr);
0244         pic32_err_stop(pic32s, "err_irq: fifo ov/ur-run\n");
0245         return IRQ_HANDLED;
0246     }
0247 
0248     if (status & STAT_FRM_ERR) {
0249         pic32_err_stop(pic32s, "err_irq: frame error");
0250         return IRQ_HANDLED;
0251     }
0252 
0253     if (!pic32s->master->cur_msg) {
0254         pic32_err_stop(pic32s, "err_irq: no mesg");
0255         return IRQ_NONE;
0256     }
0257 
0258     return IRQ_NONE;
0259 }
0260 
0261 static irqreturn_t pic32_spi_rx_irq(int irq, void *dev_id)
0262 {
0263     struct pic32_spi *pic32s = dev_id;
0264 
0265     pic32s->rx_fifo(pic32s);
0266 
0267     /* rx complete ? */
0268     if (pic32s->rx_end == pic32s->rx) {
0269         /* disable all interrupts */
0270         disable_irq_nosync(pic32s->fault_irq);
0271         disable_irq_nosync(pic32s->rx_irq);
0272 
0273         /* complete current xfer */
0274         complete(&pic32s->xfer_done);
0275     }
0276 
0277     return IRQ_HANDLED;
0278 }
0279 
0280 static irqreturn_t pic32_spi_tx_irq(int irq, void *dev_id)
0281 {
0282     struct pic32_spi *pic32s = dev_id;
0283 
0284     pic32s->tx_fifo(pic32s);
0285 
0286     /* tx complete? disable tx interrupt */
0287     if (pic32s->tx_end == pic32s->tx)
0288         disable_irq_nosync(pic32s->tx_irq);
0289 
0290     return IRQ_HANDLED;
0291 }
0292 
0293 static void pic32_spi_dma_rx_notify(void *data)
0294 {
0295     struct pic32_spi *pic32s = data;
0296 
0297     complete(&pic32s->xfer_done);
0298 }
0299 
0300 static int pic32_spi_dma_transfer(struct pic32_spi *pic32s,
0301                   struct spi_transfer *xfer)
0302 {
0303     struct spi_master *master = pic32s->master;
0304     struct dma_async_tx_descriptor *desc_rx;
0305     struct dma_async_tx_descriptor *desc_tx;
0306     dma_cookie_t cookie;
0307     int ret;
0308 
0309     if (!master->dma_rx || !master->dma_tx)
0310         return -ENODEV;
0311 
0312     desc_rx = dmaengine_prep_slave_sg(master->dma_rx,
0313                       xfer->rx_sg.sgl,
0314                       xfer->rx_sg.nents,
0315                       DMA_DEV_TO_MEM,
0316                       DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
0317     if (!desc_rx) {
0318         ret = -EINVAL;
0319         goto err_dma;
0320     }
0321 
0322     desc_tx = dmaengine_prep_slave_sg(master->dma_tx,
0323                       xfer->tx_sg.sgl,
0324                       xfer->tx_sg.nents,
0325                       DMA_MEM_TO_DEV,
0326                       DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
0327     if (!desc_tx) {
0328         ret = -EINVAL;
0329         goto err_dma;
0330     }
0331 
0332     /* Put callback on the RX transfer, that should finish last */
0333     desc_rx->callback = pic32_spi_dma_rx_notify;
0334     desc_rx->callback_param = pic32s;
0335 
0336     cookie = dmaengine_submit(desc_rx);
0337     ret = dma_submit_error(cookie);
0338     if (ret)
0339         goto err_dma;
0340 
0341     cookie = dmaengine_submit(desc_tx);
0342     ret = dma_submit_error(cookie);
0343     if (ret)
0344         goto err_dma_tx;
0345 
0346     dma_async_issue_pending(master->dma_rx);
0347     dma_async_issue_pending(master->dma_tx);
0348 
0349     return 0;
0350 
0351 err_dma_tx:
0352     dmaengine_terminate_all(master->dma_rx);
0353 err_dma:
0354     return ret;
0355 }
0356 
0357 static int pic32_spi_dma_config(struct pic32_spi *pic32s, u32 dma_width)
0358 {
0359     int buf_offset = offsetof(struct pic32_spi_regs, buf);
0360     struct spi_master *master = pic32s->master;
0361     struct dma_slave_config cfg;
0362     int ret;
0363 
0364     memset(&cfg, 0, sizeof(cfg));
0365     cfg.device_fc = true;
0366     cfg.src_addr = pic32s->dma_base + buf_offset;
0367     cfg.dst_addr = pic32s->dma_base + buf_offset;
0368     cfg.src_maxburst = pic32s->fifo_n_elm / 2; /* fill one-half */
0369     cfg.dst_maxburst = pic32s->fifo_n_elm / 2; /* drain one-half */
0370     cfg.src_addr_width = dma_width;
0371     cfg.dst_addr_width = dma_width;
0372     /* tx channel */
0373     cfg.direction = DMA_MEM_TO_DEV;
0374     ret = dmaengine_slave_config(master->dma_tx, &cfg);
0375     if (ret) {
0376         dev_err(&master->dev, "tx channel setup failed\n");
0377         return ret;
0378     }
0379     /* rx channel */
0380     cfg.direction = DMA_DEV_TO_MEM;
0381     ret = dmaengine_slave_config(master->dma_rx, &cfg);
0382     if (ret)
0383         dev_err(&master->dev, "rx channel setup failed\n");
0384 
0385     return ret;
0386 }
0387 
0388 static int pic32_spi_set_word_size(struct pic32_spi *pic32s, u8 bits_per_word)
0389 {
0390     enum dma_slave_buswidth dmawidth;
0391     u32 buswidth, v;
0392 
0393     switch (bits_per_word) {
0394     case 8:
0395         pic32s->rx_fifo = pic32_spi_rx_byte;
0396         pic32s->tx_fifo = pic32_spi_tx_byte;
0397         buswidth = PIC32_BPW_8;
0398         dmawidth = DMA_SLAVE_BUSWIDTH_1_BYTE;
0399         break;
0400     case 16:
0401         pic32s->rx_fifo = pic32_spi_rx_word;
0402         pic32s->tx_fifo = pic32_spi_tx_word;
0403         buswidth = PIC32_BPW_16;
0404         dmawidth = DMA_SLAVE_BUSWIDTH_2_BYTES;
0405         break;
0406     case 32:
0407         pic32s->rx_fifo = pic32_spi_rx_dword;
0408         pic32s->tx_fifo = pic32_spi_tx_dword;
0409         buswidth = PIC32_BPW_32;
0410         dmawidth = DMA_SLAVE_BUSWIDTH_4_BYTES;
0411         break;
0412     default:
0413         /* not supported */
0414         return -EINVAL;
0415     }
0416 
0417     /* calculate maximum number of words fifos can hold */
0418     pic32s->fifo_n_elm = DIV_ROUND_UP(pic32s->fifo_n_byte,
0419                       bits_per_word / 8);
0420     /* set word size */
0421     v = readl(&pic32s->regs->ctrl);
0422     v &= ~(CTRL_BPW_MASK << CTRL_BPW_SHIFT);
0423     v |= buswidth << CTRL_BPW_SHIFT;
0424     writel(v, &pic32s->regs->ctrl);
0425 
0426     /* re-configure dma width, if required */
0427     if (test_bit(PIC32F_DMA_PREP, &pic32s->flags))
0428         pic32_spi_dma_config(pic32s, dmawidth);
0429 
0430     return 0;
0431 }
0432 
0433 static int pic32_spi_prepare_hardware(struct spi_master *master)
0434 {
0435     struct pic32_spi *pic32s = spi_master_get_devdata(master);
0436 
0437     pic32_spi_enable(pic32s);
0438 
0439     return 0;
0440 }
0441 
0442 static int pic32_spi_prepare_message(struct spi_master *master,
0443                      struct spi_message *msg)
0444 {
0445     struct pic32_spi *pic32s = spi_master_get_devdata(master);
0446     struct spi_device *spi = msg->spi;
0447     u32 val;
0448 
0449     /* set device specific bits_per_word */
0450     if (pic32s->bits_per_word != spi->bits_per_word) {
0451         pic32_spi_set_word_size(pic32s, spi->bits_per_word);
0452         pic32s->bits_per_word = spi->bits_per_word;
0453     }
0454 
0455     /* device specific speed change */
0456     if (pic32s->speed_hz != spi->max_speed_hz) {
0457         pic32_spi_set_clk_rate(pic32s, spi->max_speed_hz);
0458         pic32s->speed_hz = spi->max_speed_hz;
0459     }
0460 
0461     /* device specific mode change */
0462     if (pic32s->mode != spi->mode) {
0463         val = readl(&pic32s->regs->ctrl);
0464         /* active low */
0465         if (spi->mode & SPI_CPOL)
0466             val |= CTRL_CKP;
0467         else
0468             val &= ~CTRL_CKP;
0469         /* tx on rising edge */
0470         if (spi->mode & SPI_CPHA)
0471             val &= ~CTRL_CKE;
0472         else
0473             val |= CTRL_CKE;
0474 
0475         /* rx at end of tx */
0476         val |= CTRL_SMP;
0477         writel(val, &pic32s->regs->ctrl);
0478         pic32s->mode = spi->mode;
0479     }
0480 
0481     return 0;
0482 }
0483 
0484 static bool pic32_spi_can_dma(struct spi_master *master,
0485                   struct spi_device *spi,
0486                   struct spi_transfer *xfer)
0487 {
0488     struct pic32_spi *pic32s = spi_master_get_devdata(master);
0489 
0490     /* skip using DMA on small size transfer to avoid overhead.*/
0491     return (xfer->len >= PIC32_DMA_LEN_MIN) &&
0492            test_bit(PIC32F_DMA_PREP, &pic32s->flags);
0493 }
0494 
0495 static int pic32_spi_one_transfer(struct spi_master *master,
0496                   struct spi_device *spi,
0497                   struct spi_transfer *transfer)
0498 {
0499     struct pic32_spi *pic32s;
0500     bool dma_issued = false;
0501     unsigned long timeout;
0502     int ret;
0503 
0504     pic32s = spi_master_get_devdata(master);
0505 
0506     /* handle transfer specific word size change */
0507     if (transfer->bits_per_word &&
0508         (transfer->bits_per_word != pic32s->bits_per_word)) {
0509         ret = pic32_spi_set_word_size(pic32s, transfer->bits_per_word);
0510         if (ret)
0511             return ret;
0512         pic32s->bits_per_word = transfer->bits_per_word;
0513     }
0514 
0515     /* handle transfer specific speed change */
0516     if (transfer->speed_hz && (transfer->speed_hz != pic32s->speed_hz)) {
0517         pic32_spi_set_clk_rate(pic32s, transfer->speed_hz);
0518         pic32s->speed_hz = transfer->speed_hz;
0519     }
0520 
0521     reinit_completion(&pic32s->xfer_done);
0522 
0523     /* transact by DMA mode */
0524     if (transfer->rx_sg.nents && transfer->tx_sg.nents) {
0525         ret = pic32_spi_dma_transfer(pic32s, transfer);
0526         if (ret) {
0527             dev_err(&spi->dev, "dma submit error\n");
0528             return ret;
0529         }
0530 
0531         /* DMA issued */
0532         dma_issued = true;
0533     } else {
0534         /* set current transfer information */
0535         pic32s->tx = (const void *)transfer->tx_buf;
0536         pic32s->rx = (const void *)transfer->rx_buf;
0537         pic32s->tx_end = pic32s->tx + transfer->len;
0538         pic32s->rx_end = pic32s->rx + transfer->len;
0539         pic32s->len = transfer->len;
0540 
0541         /* transact by interrupt driven PIO */
0542         enable_irq(pic32s->fault_irq);
0543         enable_irq(pic32s->rx_irq);
0544         enable_irq(pic32s->tx_irq);
0545     }
0546 
0547     /* wait for completion */
0548     timeout = wait_for_completion_timeout(&pic32s->xfer_done, 2 * HZ);
0549     if (timeout == 0) {
0550         dev_err(&spi->dev, "wait error/timedout\n");
0551         if (dma_issued) {
0552             dmaengine_terminate_all(master->dma_rx);
0553             dmaengine_terminate_all(master->dma_tx);
0554         }
0555         ret = -ETIMEDOUT;
0556     } else {
0557         ret = 0;
0558     }
0559 
0560     return ret;
0561 }
0562 
0563 static int pic32_spi_unprepare_message(struct spi_master *master,
0564                        struct spi_message *msg)
0565 {
0566     /* nothing to do */
0567     return 0;
0568 }
0569 
0570 static int pic32_spi_unprepare_hardware(struct spi_master *master)
0571 {
0572     struct pic32_spi *pic32s = spi_master_get_devdata(master);
0573 
0574     pic32_spi_disable(pic32s);
0575 
0576     return 0;
0577 }
0578 
0579 /* This may be called multiple times by same spi dev */
0580 static int pic32_spi_setup(struct spi_device *spi)
0581 {
0582     if (!spi->max_speed_hz) {
0583         dev_err(&spi->dev, "No max speed HZ parameter\n");
0584         return -EINVAL;
0585     }
0586 
0587     /* PIC32 spi controller can drive /CS during transfer depending
0588      * on tx fifo fill-level. /CS will stay asserted as long as TX
0589      * fifo is non-empty, else will be deasserted indicating
0590      * completion of the ongoing transfer. This might result into
0591      * unreliable/erroneous SPI transactions.
0592      * To avoid that we will always handle /CS by toggling GPIO.
0593      */
0594     if (!spi->cs_gpiod)
0595         return -EINVAL;
0596 
0597     return 0;
0598 }
0599 
0600 static void pic32_spi_cleanup(struct spi_device *spi)
0601 {
0602     /* de-activate cs-gpio, gpiolib will handle inversion */
0603     gpiod_direction_output(spi->cs_gpiod, 0);
0604 }
0605 
0606 static int pic32_spi_dma_prep(struct pic32_spi *pic32s, struct device *dev)
0607 {
0608     struct spi_master *master = pic32s->master;
0609     int ret = 0;
0610 
0611     master->dma_rx = dma_request_chan(dev, "spi-rx");
0612     if (IS_ERR(master->dma_rx)) {
0613         if (PTR_ERR(master->dma_rx) == -EPROBE_DEFER)
0614             ret = -EPROBE_DEFER;
0615         else
0616             dev_warn(dev, "RX channel not found.\n");
0617 
0618         master->dma_rx = NULL;
0619         goto out_err;
0620     }
0621 
0622     master->dma_tx = dma_request_chan(dev, "spi-tx");
0623     if (IS_ERR(master->dma_tx)) {
0624         if (PTR_ERR(master->dma_tx) == -EPROBE_DEFER)
0625             ret = -EPROBE_DEFER;
0626         else
0627             dev_warn(dev, "TX channel not found.\n");
0628 
0629         master->dma_tx = NULL;
0630         goto out_err;
0631     }
0632 
0633     if (pic32_spi_dma_config(pic32s, DMA_SLAVE_BUSWIDTH_1_BYTE))
0634         goto out_err;
0635 
0636     /* DMA chnls allocated and prepared */
0637     set_bit(PIC32F_DMA_PREP, &pic32s->flags);
0638 
0639     return 0;
0640 
0641 out_err:
0642     if (master->dma_rx) {
0643         dma_release_channel(master->dma_rx);
0644         master->dma_rx = NULL;
0645     }
0646 
0647     if (master->dma_tx) {
0648         dma_release_channel(master->dma_tx);
0649         master->dma_tx = NULL;
0650     }
0651 
0652     return ret;
0653 }
0654 
0655 static void pic32_spi_dma_unprep(struct pic32_spi *pic32s)
0656 {
0657     if (!test_bit(PIC32F_DMA_PREP, &pic32s->flags))
0658         return;
0659 
0660     clear_bit(PIC32F_DMA_PREP, &pic32s->flags);
0661     if (pic32s->master->dma_rx)
0662         dma_release_channel(pic32s->master->dma_rx);
0663 
0664     if (pic32s->master->dma_tx)
0665         dma_release_channel(pic32s->master->dma_tx);
0666 }
0667 
0668 static void pic32_spi_hw_init(struct pic32_spi *pic32s)
0669 {
0670     u32 ctrl;
0671 
0672     /* disable hardware */
0673     pic32_spi_disable(pic32s);
0674 
0675     ctrl = readl(&pic32s->regs->ctrl);
0676     /* enable enhanced fifo of 128bit deep */
0677     ctrl |= CTRL_ENHBUF;
0678     pic32s->fifo_n_byte = 16;
0679 
0680     /* disable framing mode */
0681     ctrl &= ~CTRL_FRMEN;
0682 
0683     /* enable master mode while disabled */
0684     ctrl |= CTRL_MSTEN;
0685 
0686     /* set tx fifo threshold interrupt */
0687     ctrl &= ~(0x3 << CTRL_TX_INT_SHIFT);
0688     ctrl |= (TX_FIFO_HALF_EMPTY << CTRL_TX_INT_SHIFT);
0689 
0690     /* set rx fifo threshold interrupt */
0691     ctrl &= ~(0x3 << CTRL_RX_INT_SHIFT);
0692     ctrl |= (RX_FIFO_NOT_EMPTY << CTRL_RX_INT_SHIFT);
0693 
0694     /* select clk source */
0695     ctrl &= ~CTRL_MCLKSEL;
0696 
0697     /* set manual /CS mode */
0698     ctrl &= ~CTRL_MSSEN;
0699 
0700     writel(ctrl, &pic32s->regs->ctrl);
0701 
0702     /* enable error reporting */
0703     ctrl = CTRL2_TX_UR_EN | CTRL2_RX_OV_EN | CTRL2_FRM_ERR_EN;
0704     writel(ctrl, &pic32s->regs->ctrl2_set);
0705 }
0706 
0707 static int pic32_spi_hw_probe(struct platform_device *pdev,
0708                   struct pic32_spi *pic32s)
0709 {
0710     struct resource *mem;
0711     int ret;
0712 
0713     mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
0714     pic32s->regs = devm_ioremap_resource(&pdev->dev, mem);
0715     if (IS_ERR(pic32s->regs))
0716         return PTR_ERR(pic32s->regs);
0717 
0718     pic32s->dma_base = mem->start;
0719 
0720     /* get irq resources: err-irq, rx-irq, tx-irq */
0721     pic32s->fault_irq = platform_get_irq_byname(pdev, "fault");
0722     if (pic32s->fault_irq < 0)
0723         return pic32s->fault_irq;
0724 
0725     pic32s->rx_irq = platform_get_irq_byname(pdev, "rx");
0726     if (pic32s->rx_irq < 0)
0727         return pic32s->rx_irq;
0728 
0729     pic32s->tx_irq = platform_get_irq_byname(pdev, "tx");
0730     if (pic32s->tx_irq < 0)
0731         return pic32s->tx_irq;
0732 
0733     /* get clock */
0734     pic32s->clk = devm_clk_get(&pdev->dev, "mck0");
0735     if (IS_ERR(pic32s->clk)) {
0736         dev_err(&pdev->dev, "clk not found\n");
0737         ret = PTR_ERR(pic32s->clk);
0738         goto err_unmap_mem;
0739     }
0740 
0741     ret = clk_prepare_enable(pic32s->clk);
0742     if (ret)
0743         goto err_unmap_mem;
0744 
0745     pic32_spi_hw_init(pic32s);
0746 
0747     return 0;
0748 
0749 err_unmap_mem:
0750     dev_err(&pdev->dev, "%s failed, err %d\n", __func__, ret);
0751     return ret;
0752 }
0753 
0754 static int pic32_spi_probe(struct platform_device *pdev)
0755 {
0756     struct spi_master *master;
0757     struct pic32_spi *pic32s;
0758     int ret;
0759 
0760     master = spi_alloc_master(&pdev->dev, sizeof(*pic32s));
0761     if (!master)
0762         return -ENOMEM;
0763 
0764     pic32s = spi_master_get_devdata(master);
0765     pic32s->master = master;
0766 
0767     ret = pic32_spi_hw_probe(pdev, pic32s);
0768     if (ret)
0769         goto err_master;
0770 
0771     master->dev.of_node = pdev->dev.of_node;
0772     master->mode_bits   = SPI_MODE_3 | SPI_MODE_0 | SPI_CS_HIGH;
0773     master->num_chipselect  = 1; /* single chip-select */
0774     master->max_speed_hz    = clk_get_rate(pic32s->clk);
0775     master->setup       = pic32_spi_setup;
0776     master->cleanup     = pic32_spi_cleanup;
0777     master->flags       = SPI_MASTER_MUST_TX | SPI_MASTER_MUST_RX;
0778     master->bits_per_word_mask  = SPI_BPW_MASK(8) | SPI_BPW_MASK(16) |
0779                       SPI_BPW_MASK(32);
0780     master->transfer_one        = pic32_spi_one_transfer;
0781     master->prepare_message     = pic32_spi_prepare_message;
0782     master->unprepare_message   = pic32_spi_unprepare_message;
0783     master->prepare_transfer_hardware   = pic32_spi_prepare_hardware;
0784     master->unprepare_transfer_hardware = pic32_spi_unprepare_hardware;
0785     master->use_gpio_descriptors = true;
0786 
0787     /* optional DMA support */
0788     ret = pic32_spi_dma_prep(pic32s, &pdev->dev);
0789     if (ret)
0790         goto err_bailout;
0791 
0792     if (test_bit(PIC32F_DMA_PREP, &pic32s->flags))
0793         master->can_dma = pic32_spi_can_dma;
0794 
0795     init_completion(&pic32s->xfer_done);
0796     pic32s->mode = -1;
0797 
0798     /* install irq handlers (with irq-disabled) */
0799     irq_set_status_flags(pic32s->fault_irq, IRQ_NOAUTOEN);
0800     ret = devm_request_irq(&pdev->dev, pic32s->fault_irq,
0801                    pic32_spi_fault_irq, IRQF_NO_THREAD,
0802                    dev_name(&pdev->dev), pic32s);
0803     if (ret < 0) {
0804         dev_err(&pdev->dev, "request fault-irq %d\n", pic32s->rx_irq);
0805         goto err_bailout;
0806     }
0807 
0808     /* receive interrupt handler */
0809     irq_set_status_flags(pic32s->rx_irq, IRQ_NOAUTOEN);
0810     ret = devm_request_irq(&pdev->dev, pic32s->rx_irq,
0811                    pic32_spi_rx_irq, IRQF_NO_THREAD,
0812                    dev_name(&pdev->dev), pic32s);
0813     if (ret < 0) {
0814         dev_err(&pdev->dev, "request rx-irq %d\n", pic32s->rx_irq);
0815         goto err_bailout;
0816     }
0817 
0818     /* transmit interrupt handler */
0819     irq_set_status_flags(pic32s->tx_irq, IRQ_NOAUTOEN);
0820     ret = devm_request_irq(&pdev->dev, pic32s->tx_irq,
0821                    pic32_spi_tx_irq, IRQF_NO_THREAD,
0822                    dev_name(&pdev->dev), pic32s);
0823     if (ret < 0) {
0824         dev_err(&pdev->dev, "request tx-irq %d\n", pic32s->tx_irq);
0825         goto err_bailout;
0826     }
0827 
0828     /* register master */
0829     ret = devm_spi_register_master(&pdev->dev, master);
0830     if (ret) {
0831         dev_err(&master->dev, "failed registering spi master\n");
0832         goto err_bailout;
0833     }
0834 
0835     platform_set_drvdata(pdev, pic32s);
0836 
0837     return 0;
0838 
0839 err_bailout:
0840     pic32_spi_dma_unprep(pic32s);
0841     clk_disable_unprepare(pic32s->clk);
0842 err_master:
0843     spi_master_put(master);
0844     return ret;
0845 }
0846 
0847 static int pic32_spi_remove(struct platform_device *pdev)
0848 {
0849     struct pic32_spi *pic32s;
0850 
0851     pic32s = platform_get_drvdata(pdev);
0852     pic32_spi_disable(pic32s);
0853     clk_disable_unprepare(pic32s->clk);
0854     pic32_spi_dma_unprep(pic32s);
0855 
0856     return 0;
0857 }
0858 
0859 static const struct of_device_id pic32_spi_of_match[] = {
0860     {.compatible = "microchip,pic32mzda-spi",},
0861     {},
0862 };
0863 MODULE_DEVICE_TABLE(of, pic32_spi_of_match);
0864 
0865 static struct platform_driver pic32_spi_driver = {
0866     .driver = {
0867         .name = "spi-pic32",
0868         .of_match_table = of_match_ptr(pic32_spi_of_match),
0869     },
0870     .probe = pic32_spi_probe,
0871     .remove = pic32_spi_remove,
0872 };
0873 
0874 module_platform_driver(pic32_spi_driver);
0875 
0876 MODULE_AUTHOR("Purna Chandra Mandal <purna.mandal@microchip.com>");
0877 MODULE_DESCRIPTION("Microchip SPI driver for PIC32 SPI controller.");
0878 MODULE_LICENSE("GPL v2");
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