drivers/spi/spi-orion.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Marvell Orion SPI controller driver
0004  *
0005  * Author: Shadi Ammouri <shadi@marvell.com>
0006  * Copyright (C) 2007-2008 Marvell Ltd.
0007  */
0008
0009 #include <linux/interrupt.h>
0010 #include <linux/delay.h>
0011 #include <linux/platform_device.h>
0012 #include <linux/err.h>
0013 #include <linux/io.h>
0014 #include <linux/spi/spi.h>
0015 #include <linux/module.h>
0016 #include <linux/pm_runtime.h>
0017 #include <linux/of.h>
0018 #include <linux/of_address.h>
0019 #include <linux/of_device.h>
0020 #include <linux/clk.h>
0021 #include <linux/sizes.h>
0022 #include <asm/unaligned.h>
0023
0024 #define DRIVER_NAME         "orion_spi"
0025
0026 /* Runtime PM autosuspend timeout: PM is fairly light on this driver */
0027 #define SPI_AUTOSUSPEND_TIMEOUT     200
0028
0029 /* Some SoCs using this driver support up to 8 chip selects.
0030  * It is up to the implementer to only use the chip selects
0031  * that are available.
0032  */
0033 #define ORION_NUM_CHIPSELECTS       8
0034
0035 #define ORION_SPI_WAIT_RDY_MAX_LOOP 2000 /* in usec */
0036
0037 #define ORION_SPI_IF_CTRL_REG       0x00
0038 #define ORION_SPI_IF_CONFIG_REG     0x04
0039 #define ORION_SPI_IF_RXLSBF     BIT(14)
0040 #define ORION_SPI_IF_TXLSBF     BIT(13)
0041 #define ORION_SPI_DATA_OUT_REG      0x08
0042 #define ORION_SPI_DATA_IN_REG       0x0c
0043 #define ORION_SPI_INT_CAUSE_REG     0x10
0044 #define ORION_SPI_TIMING_PARAMS_REG 0x18
0045
0046 /* Register for the "Direct Mode" */
0047 #define SPI_DIRECT_WRITE_CONFIG_REG 0x20
0048
0049 #define ORION_SPI_TMISO_SAMPLE_MASK (0x3 << 6)
0050 #define ORION_SPI_TMISO_SAMPLE_1    (1 << 6)
0051 #define ORION_SPI_TMISO_SAMPLE_2    (2 << 6)
0052
0053 #define ORION_SPI_MODE_CPOL     (1 << 11)
0054 #define ORION_SPI_MODE_CPHA     (1 << 12)
0055 #define ORION_SPI_IF_8_16_BIT_MODE  (1 << 5)
0056 #define ORION_SPI_CLK_PRESCALE_MASK 0x1F
0057 #define ARMADA_SPI_CLK_PRESCALE_MASK    0xDF
0058 #define ORION_SPI_MODE_MASK     (ORION_SPI_MODE_CPOL | \
0059                      ORION_SPI_MODE_CPHA)
0060 #define ORION_SPI_CS_MASK   0x1C
0061 #define ORION_SPI_CS_SHIFT  2
0062 #define ORION_SPI_CS(cs)    ((cs << ORION_SPI_CS_SHIFT) & \
0063                     ORION_SPI_CS_MASK)
0064
0065 enum orion_spi_type {
0066     ORION_SPI,
0067     ARMADA_SPI,
0068 };
0069
0070 struct orion_spi_dev {
0071     enum orion_spi_type typ;
0072     /*
0073      * min_divisor and max_hz should be exclusive, the only we can
0074      * have both is for managing the armada-370-spi case with old
0075      * device tree
0076      */
0077     unsigned long       max_hz;
0078     unsigned int        min_divisor;
0079     unsigned int        max_divisor;
0080     u32         prescale_mask;
0081     bool            is_errata_50mhz_ac;
0082 };
0083
0084 struct orion_direct_acc {
0085     void __iomem        *vaddr;
0086     u32         size;
0087 };
0088
0089 struct orion_child_options {
0090     struct orion_direct_acc direct_access;
0091 };
0092
0093 struct orion_spi {
0094     struct spi_master   *master;
0095     void __iomem        *base;
0096     struct clk              *clk;
0097     struct clk              *axi_clk;
0098     const struct orion_spi_dev *devdata;
0099     struct device       *dev;
0100
0101     struct orion_child_options  child[ORION_NUM_CHIPSELECTS];
0102 };
0103
0104 #ifdef CONFIG_PM
0105 static int orion_spi_runtime_suspend(struct device *dev);
0106 static int orion_spi_runtime_resume(struct device *dev);
0107 #endif
0108
0109 static inline void __iomem *spi_reg(struct orion_spi *orion_spi, u32 reg)
0110 {
0111     return orion_spi->base + reg;
0112 }
0113
0114 static inline void
0115 orion_spi_setbits(struct orion_spi *orion_spi, u32 reg, u32 mask)
0116 {
0117     void __iomem *reg_addr = spi_reg(orion_spi, reg);
0118     u32 val;
0119
0120     val = readl(reg_addr);
0121     val |= mask;
0122     writel(val, reg_addr);
0123 }
0124
0125 static inline void
0126 orion_spi_clrbits(struct orion_spi *orion_spi, u32 reg, u32 mask)
0127 {
0128     void __iomem *reg_addr = spi_reg(orion_spi, reg);
0129     u32 val;
0130
0131     val = readl(reg_addr);
0132     val &= ~mask;
0133     writel(val, reg_addr);
0134 }
0135
0136 static int orion_spi_baudrate_set(struct spi_device *spi, unsigned int speed)
0137 {
0138     u32 tclk_hz;
0139     u32 rate;
0140     u32 prescale;
0141     u32 reg;
0142     struct orion_spi *orion_spi;
0143     const struct orion_spi_dev *devdata;
0144
0145     orion_spi = spi_master_get_devdata(spi->master);
0146     devdata = orion_spi->devdata;
0147
0148     tclk_hz = clk_get_rate(orion_spi->clk);
0149
0150     if (devdata->typ == ARMADA_SPI) {
0151         /*
0152          * Given the core_clk (tclk_hz) and the target rate (speed) we
0153          * determine the best values for SPR (in [0 .. 15]) and SPPR (in
0154          * [0..7]) such that
0155          *
0156          *  core_clk / (SPR * 2 ** SPPR)
0157          *
0158          * is as big as possible but not bigger than speed.
0159          */
0160
0161         /* best integer divider: */
0162         unsigned divider = DIV_ROUND_UP(tclk_hz, speed);
0163         unsigned spr, sppr;
0164
0165         if (divider < 16) {
0166             /* This is the easy case, divider is less than 16 */
0167             spr = divider;
0168             sppr = 0;
0169
0170         } else {
0171             unsigned two_pow_sppr;
0172             /*
0173              * Find the highest bit set in divider. This and the
0174              * three next bits define SPR (apart from rounding).
0175              * SPPR is then the number of zero bits that must be
0176              * appended:
0177              */
0178             sppr = fls(divider) - 4;
0179
0180             /*
0181              * As SPR only has 4 bits, we have to round divider up
0182              * to the next multiple of 2 ** sppr.
0183              */
0184             two_pow_sppr = 1 << sppr;
0185             divider = (divider + two_pow_sppr - 1) & -two_pow_sppr;
0186
0187             /*
0188              * recalculate sppr as rounding up divider might have
0189              * increased it enough to change the position of the
0190              * highest set bit. In this case the bit that now
0191              * doesn't make it into SPR is 0, so there is no need to
0192              * round again.
0193              */
0194             sppr = fls(divider) - 4;
0195             spr = divider >> sppr;
0196
0197             /*
0198              * Now do range checking. SPR is constructed to have a
0199              * width of 4 bits, so this is fine for sure. So we
0200              * still need to check for sppr to fit into 3 bits:
0201              */
0202             if (sppr > 7)
0203                 return -EINVAL;
0204         }
0205
0206         prescale = ((sppr & 0x6) << 5) | ((sppr & 0x1) << 4) | spr;
0207     } else {
0208         /*
0209          * the supported rates are: 4,6,8...30
0210          * round up as we look for equal or less speed
0211          */
0212         rate = DIV_ROUND_UP(tclk_hz, speed);
0213         rate = roundup(rate, 2);
0214
0215         /* check if requested speed is too small */
0216         if (rate > 30)
0217             return -EINVAL;
0218
0219         if (rate < 4)
0220             rate = 4;
0221
0222         /* Convert the rate to SPI clock divisor value. */
0223         prescale = 0x10 + rate/2;
0224     }
0225
0226     reg = readl(spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG));
0227     reg = ((reg & ~devdata->prescale_mask) | prescale);
0228     writel(reg, spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG));
0229
0230     return 0;
0231 }
0232
0233 static void
0234 orion_spi_mode_set(struct spi_device *spi)
0235 {
0236     u32 reg;
0237     struct orion_spi *orion_spi;
0238
0239     orion_spi = spi_master_get_devdata(spi->master);
0240
0241     reg = readl(spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG));
0242     reg &= ~ORION_SPI_MODE_MASK;
0243     if (spi->mode & SPI_CPOL)
0244         reg |= ORION_SPI_MODE_CPOL;
0245     if (spi->mode & SPI_CPHA)
0246         reg |= ORION_SPI_MODE_CPHA;
0247     if (spi->mode & SPI_LSB_FIRST)
0248         reg |= ORION_SPI_IF_RXLSBF | ORION_SPI_IF_TXLSBF;
0249     else
0250         reg &= ~(ORION_SPI_IF_RXLSBF | ORION_SPI_IF_TXLSBF);
0251
0252     writel(reg, spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG));
0253 }
0254
0255 static void
0256 orion_spi_50mhz_ac_timing_erratum(struct spi_device *spi, unsigned int speed)
0257 {
0258     u32 reg;
0259     struct orion_spi *orion_spi;
0260
0261     orion_spi = spi_master_get_devdata(spi->master);
0262
0263     /*
0264      * Erratum description: (Erratum NO. FE-9144572) The device
0265      * SPI interface supports frequencies of up to 50 MHz.
0266      * However, due to this erratum, when the device core clock is
0267      * 250 MHz and the SPI interfaces is configured for 50MHz SPI
0268      * clock and CPOL=CPHA=1 there might occur data corruption on
0269      * reads from the SPI device.
0270      * Erratum Workaround:
0271      * Work in one of the following configurations:
0272      * 1. Set CPOL=CPHA=0 in "SPI Interface Configuration
0273      * Register".
0274      * 2. Set TMISO_SAMPLE value to 0x2 in "SPI Timing Parameters 1
0275      * Register" before setting the interface.
0276      */
0277     reg = readl(spi_reg(orion_spi, ORION_SPI_TIMING_PARAMS_REG));
0278     reg &= ~ORION_SPI_TMISO_SAMPLE_MASK;
0279
0280     if (clk_get_rate(orion_spi->clk) == 250000000 &&
0281             speed == 50000000 && spi->mode & SPI_CPOL &&
0282             spi->mode & SPI_CPHA)
0283         reg |= ORION_SPI_TMISO_SAMPLE_2;
0284     else
0285         reg |= ORION_SPI_TMISO_SAMPLE_1; /* This is the default value */
0286
0287     writel(reg, spi_reg(orion_spi, ORION_SPI_TIMING_PARAMS_REG));
0288 }
0289
0290 /*
0291  * called only when no transfer is active on the bus
0292  */
0293 static int
0294 orion_spi_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
0295 {
0296     struct orion_spi *orion_spi;
0297     unsigned int speed = spi->max_speed_hz;
0298     unsigned int bits_per_word = spi->bits_per_word;
0299     int rc;
0300
0301     orion_spi = spi_master_get_devdata(spi->master);
0302
0303     if ((t != NULL) && t->speed_hz)
0304         speed = t->speed_hz;
0305
0306     if ((t != NULL) && t->bits_per_word)
0307         bits_per_word = t->bits_per_word;
0308
0309     orion_spi_mode_set(spi);
0310
0311     if (orion_spi->devdata->is_errata_50mhz_ac)
0312         orion_spi_50mhz_ac_timing_erratum(spi, speed);
0313
0314     rc = orion_spi_baudrate_set(spi, speed);
0315     if (rc)
0316         return rc;
0317
0318     if (bits_per_word == 16)
0319         orion_spi_setbits(orion_spi, ORION_SPI_IF_CONFIG_REG,
0320                   ORION_SPI_IF_8_16_BIT_MODE);
0321     else
0322         orion_spi_clrbits(orion_spi, ORION_SPI_IF_CONFIG_REG,
0323                   ORION_SPI_IF_8_16_BIT_MODE);
0324
0325     return 0;
0326 }
0327
0328 static void orion_spi_set_cs(struct spi_device *spi, bool enable)
0329 {
0330     struct orion_spi *orion_spi;
0331     void __iomem *ctrl_reg;
0332     u32 val;
0333
0334     orion_spi = spi_master_get_devdata(spi->master);
0335     ctrl_reg = spi_reg(orion_spi, ORION_SPI_IF_CTRL_REG);
0336
0337     val = readl(ctrl_reg);
0338
0339     /* Clear existing chip-select and assertion state */
0340     val &= ~(ORION_SPI_CS_MASK | 0x1);
0341
0342     /*
0343      * If this line is using a GPIO to control chip select, this internal
0344      * .set_cs() function will still be called, so we clear any previous
0345      * chip select. The CS we activate will not have any elecrical effect,
0346      * as it is handled by a GPIO, but that doesn't matter. What we need
0347      * is to deassert the old chip select and assert some other chip select.
0348      */
0349     val |= ORION_SPI_CS(spi->chip_select);
0350
0351     /*
0352      * Chip select logic is inverted from spi_set_cs(). For lines using a
0353      * GPIO to do chip select SPI_CS_HIGH is enforced and inversion happens
0354      * in the GPIO library, but we don't care about that, because in those
0355      * cases we are dealing with an unused native CS anyways so the polarity
0356      * doesn't matter.
0357      */
0358     if (!enable)
0359         val |= 0x1;
0360
0361     /*
0362      * To avoid toggling unwanted chip selects update the register
0363      * with a single write.
0364      */
0365     writel(val, ctrl_reg);
0366 }
0367
0368 static inline int orion_spi_wait_till_ready(struct orion_spi *orion_spi)
0369 {
0370     int i;
0371
0372     for (i = 0; i < ORION_SPI_WAIT_RDY_MAX_LOOP; i++) {
0373         if (readl(spi_reg(orion_spi, ORION_SPI_INT_CAUSE_REG)))
0374             return 1;
0375
0376         udelay(1);
0377     }
0378
0379     return -1;
0380 }
0381
0382 static inline int
0383 orion_spi_write_read_8bit(struct spi_device *spi,
0384               const u8 **tx_buf, u8 **rx_buf)
0385 {
0386     void __iomem *tx_reg, *rx_reg, *int_reg;
0387     struct orion_spi *orion_spi;
0388     bool cs_single_byte;
0389
0390     cs_single_byte = spi->mode & SPI_CS_WORD;
0391
0392     orion_spi = spi_master_get_devdata(spi->master);
0393
0394     if (cs_single_byte)
0395         orion_spi_set_cs(spi, 0);
0396
0397     tx_reg = spi_reg(orion_spi, ORION_SPI_DATA_OUT_REG);
0398     rx_reg = spi_reg(orion_spi, ORION_SPI_DATA_IN_REG);
0399     int_reg = spi_reg(orion_spi, ORION_SPI_INT_CAUSE_REG);
0400
0401     /* clear the interrupt cause register */
0402     writel(0x0, int_reg);
0403
0404     if (tx_buf && *tx_buf)
0405         writel(*(*tx_buf)++, tx_reg);
0406     else
0407         writel(0, tx_reg);
0408
0409     if (orion_spi_wait_till_ready(orion_spi) < 0) {
0410         if (cs_single_byte) {
0411             orion_spi_set_cs(spi, 1);
0412             /* Satisfy some SLIC devices requirements */
0413             udelay(4);
0414         }
0415         dev_err(&spi->dev, "TXS timed out\n");
0416         return -1;
0417     }
0418
0419     if (rx_buf && *rx_buf)
0420         *(*rx_buf)++ = readl(rx_reg);
0421
0422     if (cs_single_byte) {
0423         orion_spi_set_cs(spi, 1);
0424         /* Satisfy some SLIC devices requirements */
0425         udelay(4);
0426     }
0427
0428     return 1;
0429 }
0430
0431 static inline int
0432 orion_spi_write_read_16bit(struct spi_device *spi,
0433                const u16 **tx_buf, u16 **rx_buf)
0434 {
0435     void __iomem *tx_reg, *rx_reg, *int_reg;
0436     struct orion_spi *orion_spi;
0437
0438     if (spi->mode & SPI_CS_WORD) {
0439         dev_err(&spi->dev, "SPI_CS_WORD is only supported for 8 bit words\n");
0440         return -1;
0441     }
0442
0443     orion_spi = spi_master_get_devdata(spi->master);
0444     tx_reg = spi_reg(orion_spi, ORION_SPI_DATA_OUT_REG);
0445     rx_reg = spi_reg(orion_spi, ORION_SPI_DATA_IN_REG);
0446     int_reg = spi_reg(orion_spi, ORION_SPI_INT_CAUSE_REG);
0447
0448     /* clear the interrupt cause register */
0449     writel(0x0, int_reg);
0450
0451     if (tx_buf && *tx_buf)
0452         writel(__cpu_to_le16(get_unaligned((*tx_buf)++)), tx_reg);
0453     else
0454         writel(0, tx_reg);
0455
0456     if (orion_spi_wait_till_ready(orion_spi) < 0) {
0457         dev_err(&spi->dev, "TXS timed out\n");
0458         return -1;
0459     }
0460
0461     if (rx_buf && *rx_buf)
0462         put_unaligned(__le16_to_cpu(readl(rx_reg)), (*rx_buf)++);
0463
0464     return 1;
0465 }
0466
0467 static unsigned int
0468 orion_spi_write_read(struct spi_device *spi, struct spi_transfer *xfer)
0469 {
0470     unsigned int count;
0471     int word_len;
0472     struct orion_spi *orion_spi;
0473     int cs = spi->chip_select;
0474     void __iomem *vaddr;
0475
0476     word_len = spi->bits_per_word;
0477     count = xfer->len;
0478
0479     orion_spi = spi_master_get_devdata(spi->master);
0480
0481     /*
0482      * Use SPI direct write mode if base address is available
0483      * and SPI_CS_WORD flag is not set.
0484      * Otherwise fall back to PIO mode for this transfer.
0485      */
0486     vaddr = orion_spi->child[cs].direct_access.vaddr;
0487
0488     if (vaddr && xfer->tx_buf && word_len == 8 && (spi->mode & SPI_CS_WORD) == 0) {
0489         unsigned int cnt = count / 4;
0490         unsigned int rem = count % 4;
0491
0492         /*
0493          * Send the TX-data to the SPI device via the direct
0494          * mapped address window
0495          */
0496         iowrite32_rep(vaddr, xfer->tx_buf, cnt);
0497         if (rem) {
0498             u32 *buf = (u32 *)xfer->tx_buf;
0499
0500             iowrite8_rep(vaddr, &buf[cnt], rem);
0501         }
0502
0503         return count;
0504     }
0505
0506     if (word_len == 8) {
0507         const u8 *tx = xfer->tx_buf;
0508         u8 *rx = xfer->rx_buf;
0509
0510         do {
0511             if (orion_spi_write_read_8bit(spi, &tx, &rx) < 0)
0512                 goto out;
0513             count--;
0514             spi_delay_exec(&xfer->word_delay, xfer);
0515         } while (count);
0516     } else if (word_len == 16) {
0517         const u16 *tx = xfer->tx_buf;
0518         u16 *rx = xfer->rx_buf;
0519
0520         do {
0521             if (orion_spi_write_read_16bit(spi, &tx, &rx) < 0)
0522                 goto out;
0523             count -= 2;
0524             spi_delay_exec(&xfer->word_delay, xfer);
0525         } while (count);
0526     }
0527
0528 out:
0529     return xfer->len - count;
0530 }
0531
0532 static int orion_spi_transfer_one(struct spi_master *master,
0533                     struct spi_device *spi,
0534                     struct spi_transfer *t)
0535 {
0536     int status = 0;
0537
0538     status = orion_spi_setup_transfer(spi, t);
0539     if (status < 0)
0540         return status;
0541
0542     if (t->len)
0543         orion_spi_write_read(spi, t);
0544
0545     return status;
0546 }
0547
0548 static int orion_spi_setup(struct spi_device *spi)
0549 {
0550     int ret;
0551 #ifdef CONFIG_PM
0552     struct orion_spi *orion_spi = spi_master_get_devdata(spi->master);
0553     struct device *dev = orion_spi->dev;
0554
0555     orion_spi_runtime_resume(dev);
0556 #endif
0557
0558     ret = orion_spi_setup_transfer(spi, NULL);
0559
0560 #ifdef CONFIG_PM
0561     orion_spi_runtime_suspend(dev);
0562 #endif
0563
0564     return ret;
0565 }
0566
0567 static int orion_spi_reset(struct orion_spi *orion_spi)
0568 {
0569     /* Verify that the CS is deasserted */
0570     orion_spi_clrbits(orion_spi, ORION_SPI_IF_CTRL_REG, 0x1);
0571
0572     /* Don't deassert CS between the direct mapped SPI transfers */
0573     writel(0, spi_reg(orion_spi, SPI_DIRECT_WRITE_CONFIG_REG));
0574
0575     return 0;
0576 }
0577
0578 static const struct orion_spi_dev orion_spi_dev_data = {
0579     .typ = ORION_SPI,
0580     .min_divisor = 4,
0581     .max_divisor = 30,
0582     .prescale_mask = ORION_SPI_CLK_PRESCALE_MASK,
0583 };
0584
0585 static const struct orion_spi_dev armada_370_spi_dev_data = {
0586     .typ = ARMADA_SPI,
0587     .min_divisor = 4,
0588     .max_divisor = 1920,
0589     .max_hz = 50000000,
0590     .prescale_mask = ARMADA_SPI_CLK_PRESCALE_MASK,
0591 };
0592
0593 static const struct orion_spi_dev armada_xp_spi_dev_data = {
0594     .typ = ARMADA_SPI,
0595     .max_hz = 50000000,
0596     .max_divisor = 1920,
0597     .prescale_mask = ARMADA_SPI_CLK_PRESCALE_MASK,
0598 };
0599
0600 static const struct orion_spi_dev armada_375_spi_dev_data = {
0601     .typ = ARMADA_SPI,
0602     .min_divisor = 15,
0603     .max_divisor = 1920,
0604     .prescale_mask = ARMADA_SPI_CLK_PRESCALE_MASK,
0605 };
0606
0607 static const struct orion_spi_dev armada_380_spi_dev_data = {
0608     .typ = ARMADA_SPI,
0609     .max_hz = 50000000,
0610     .max_divisor = 1920,
0611     .prescale_mask = ARMADA_SPI_CLK_PRESCALE_MASK,
0612     .is_errata_50mhz_ac = true,
0613 };
0614
0615 static const struct of_device_id orion_spi_of_match_table[] = {
0616     {
0617         .compatible = "marvell,orion-spi",
0618         .data = &orion_spi_dev_data,
0619     },
0620     {
0621         .compatible = "marvell,armada-370-spi",
0622         .data = &armada_370_spi_dev_data,
0623     },
0624     {
0625         .compatible = "marvell,armada-375-spi",
0626         .data = &armada_375_spi_dev_data,
0627     },
0628     {
0629         .compatible = "marvell,armada-380-spi",
0630         .data = &armada_380_spi_dev_data,
0631     },
0632     {
0633         .compatible = "marvell,armada-390-spi",
0634         .data = &armada_xp_spi_dev_data,
0635     },
0636     {
0637         .compatible = "marvell,armada-xp-spi",
0638         .data = &armada_xp_spi_dev_data,
0639     },
0640
0641     {}
0642 };
0643 MODULE_DEVICE_TABLE(of, orion_spi_of_match_table);
0644
0645 static int orion_spi_probe(struct platform_device *pdev)
0646 {
0647     const struct orion_spi_dev *devdata;
0648     struct spi_master *master;
0649     struct orion_spi *spi;
0650     struct resource *r;
0651     unsigned long tclk_hz;
0652     int status = 0;
0653     struct device_node *np;
0654
0655     master = spi_alloc_master(&pdev->dev, sizeof(*spi));
0656     if (master == NULL) {
0657         dev_dbg(&pdev->dev, "master allocation failed\n");
0658         return -ENOMEM;
0659     }
0660
0661     if (pdev->id != -1)
0662         master->bus_num = pdev->id;
0663     if (pdev->dev.of_node) {
0664         u32 cell_index;
0665
0666         if (!of_property_read_u32(pdev->dev.of_node, "cell-index",
0667                       &cell_index))
0668             master->bus_num = cell_index;
0669     }
0670
0671     /* we support all 4 SPI modes and LSB first option */
0672     master->mode_bits = SPI_CPHA | SPI_CPOL | SPI_LSB_FIRST | SPI_CS_WORD;
0673     master->set_cs = orion_spi_set_cs;
0674     master->transfer_one = orion_spi_transfer_one;
0675     master->num_chipselect = ORION_NUM_CHIPSELECTS;
0676     master->setup = orion_spi_setup;
0677     master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16);
0678     master->auto_runtime_pm = true;
0679     master->use_gpio_descriptors = true;
0680     master->flags = SPI_MASTER_GPIO_SS;
0681
0682     platform_set_drvdata(pdev, master);
0683
0684     spi = spi_master_get_devdata(master);
0685     spi->master = master;
0686     spi->dev = &pdev->dev;
0687
0688     devdata = device_get_match_data(&pdev->dev);
0689     devdata = devdata ? devdata : &orion_spi_dev_data;
0690     spi->devdata = devdata;
0691
0692     spi->clk = devm_clk_get(&pdev->dev, NULL);
0693     if (IS_ERR(spi->clk)) {
0694         status = PTR_ERR(spi->clk);
0695         goto out;
0696     }
0697
0698     status = clk_prepare_enable(spi->clk);
0699     if (status)
0700         goto out;
0701
0702     /* The following clock is only used by some SoCs */
0703     spi->axi_clk = devm_clk_get(&pdev->dev, "axi");
0704     if (PTR_ERR(spi->axi_clk) == -EPROBE_DEFER) {
0705         status = -EPROBE_DEFER;
0706         goto out_rel_clk;
0707     }
0708     if (!IS_ERR(spi->axi_clk))
0709         clk_prepare_enable(spi->axi_clk);
0710
0711     tclk_hz = clk_get_rate(spi->clk);
0712
0713     /*
0714      * With old device tree, armada-370-spi could be used with
0715      * Armada XP, however for this SoC the maximum frequency is
0716      * 50MHz instead of tclk/4. On Armada 370, tclk cannot be
0717      * higher than 200MHz. So, in order to be able to handle both
0718      * SoCs, we can take the minimum of 50MHz and tclk/4.
0719      */
0720     if (of_device_is_compatible(pdev->dev.of_node,
0721                     "marvell,armada-370-spi"))
0722         master->max_speed_hz = min(devdata->max_hz,
0723                 DIV_ROUND_UP(tclk_hz, devdata->min_divisor));
0724     else if (devdata->min_divisor)
0725         master->max_speed_hz =
0726             DIV_ROUND_UP(tclk_hz, devdata->min_divisor);
0727     else
0728         master->max_speed_hz = devdata->max_hz;
0729     master->min_speed_hz = DIV_ROUND_UP(tclk_hz, devdata->max_divisor);
0730
0731     r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
0732     spi->base = devm_ioremap_resource(&pdev->dev, r);
0733     if (IS_ERR(spi->base)) {
0734         status = PTR_ERR(spi->base);
0735         goto out_rel_axi_clk;
0736     }
0737
0738     for_each_available_child_of_node(pdev->dev.of_node, np) {
0739         struct orion_direct_acc *dir_acc;
0740         u32 cs;
0741
0742         /* Get chip-select number from the "reg" property */
0743         status = of_property_read_u32(np, "reg", &cs);
0744         if (status) {
0745             dev_err(&pdev->dev,
0746                 "%pOF has no valid 'reg' property (%d)\n",
0747                 np, status);
0748             continue;
0749         }
0750
0751         /*
0752          * Check if an address is configured for this SPI device. If
0753          * not, the MBus mapping via the 'ranges' property in the 'soc'
0754          * node is not configured and this device should not use the
0755          * direct mode. In this case, just continue with the next
0756          * device.
0757          */
0758         status = of_address_to_resource(pdev->dev.of_node, cs + 1, r);
0759         if (status)
0760             continue;
0761
0762         /*
0763          * Only map one page for direct access. This is enough for the
0764          * simple TX transfer which only writes to the first word.
0765          * This needs to get extended for the direct SPI NOR / SPI NAND
0766          * support, once this gets implemented.
0767          */
0768         dir_acc = &spi->child[cs].direct_access;
0769         dir_acc->vaddr = devm_ioremap(&pdev->dev, r->start, PAGE_SIZE);
0770         if (!dir_acc->vaddr) {
0771             status = -ENOMEM;
0772             of_node_put(np);
0773             goto out_rel_axi_clk;
0774         }
0775         dir_acc->size = PAGE_SIZE;
0776
0777         dev_info(&pdev->dev, "CS%d configured for direct access\n", cs);
0778     }
0779
0780     pm_runtime_set_active(&pdev->dev);
0781     pm_runtime_use_autosuspend(&pdev->dev);
0782     pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT);
0783     pm_runtime_enable(&pdev->dev);
0784
0785     status = orion_spi_reset(spi);
0786     if (status < 0)
0787         goto out_rel_pm;
0788
0789     master->dev.of_node = pdev->dev.of_node;
0790     status = spi_register_master(master);
0791     if (status < 0)
0792         goto out_rel_pm;
0793
0794     return status;
0795
0796 out_rel_pm:
0797     pm_runtime_disable(&pdev->dev);
0798 out_rel_axi_clk:
0799     clk_disable_unprepare(spi->axi_clk);
0800 out_rel_clk:
0801     clk_disable_unprepare(spi->clk);
0802 out:
0803     spi_master_put(master);
0804     return status;
0805 }
0806
0807
0808 static int orion_spi_remove(struct platform_device *pdev)
0809 {
0810     struct spi_master *master = platform_get_drvdata(pdev);
0811     struct orion_spi *spi = spi_master_get_devdata(master);
0812
0813     pm_runtime_get_sync(&pdev->dev);
0814     clk_disable_unprepare(spi->axi_clk);
0815     clk_disable_unprepare(spi->clk);
0816
0817     spi_unregister_master(master);
0818     pm_runtime_disable(&pdev->dev);
0819
0820     return 0;
0821 }
0822
0823 MODULE_ALIAS("platform:" DRIVER_NAME);
0824
0825 #ifdef CONFIG_PM
0826 static int orion_spi_runtime_suspend(struct device *dev)
0827 {
0828     struct spi_master *master = dev_get_drvdata(dev);
0829     struct orion_spi *spi = spi_master_get_devdata(master);
0830
0831     clk_disable_unprepare(spi->axi_clk);
0832     clk_disable_unprepare(spi->clk);
0833     return 0;
0834 }
0835
0836 static int orion_spi_runtime_resume(struct device *dev)
0837 {
0838     struct spi_master *master = dev_get_drvdata(dev);
0839     struct orion_spi *spi = spi_master_get_devdata(master);
0840
0841     if (!IS_ERR(spi->axi_clk))
0842         clk_prepare_enable(spi->axi_clk);
0843     return clk_prepare_enable(spi->clk);
0844 }
0845 #endif
0846
0847 static const struct dev_pm_ops orion_spi_pm_ops = {
0848     SET_RUNTIME_PM_OPS(orion_spi_runtime_suspend,
0849                orion_spi_runtime_resume,
0850                NULL)
0851 };
0852
0853 static struct platform_driver orion_spi_driver = {
0854     .driver = {
0855         .name   = DRIVER_NAME,
0856         .pm = &orion_spi_pm_ops,
0857         .of_match_table = of_match_ptr(orion_spi_of_match_table),
0858     },
0859     .probe      = orion_spi_probe,
0860     .remove     = orion_spi_remove,
0861 };
0862
0863 module_platform_driver(orion_spi_driver);
0864
0865 MODULE_DESCRIPTION("Orion SPI driver");
0866 MODULE_AUTHOR("Shadi Ammouri <shadi@marvell.com>");
0867 MODULE_LICENSE("GPL");