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0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * OMAP2 McSPI controller driver
0004  *
0005  * Copyright (C) 2005, 2006 Nokia Corporation
0006  * Author:  Samuel Ortiz <samuel.ortiz@nokia.com> and
0007  *      Juha Yrjola <juha.yrjola@nokia.com>
0008  */
0009 
0010 #include <linux/kernel.h>
0011 #include <linux/interrupt.h>
0012 #include <linux/module.h>
0013 #include <linux/device.h>
0014 #include <linux/delay.h>
0015 #include <linux/dma-mapping.h>
0016 #include <linux/dmaengine.h>
0017 #include <linux/pinctrl/consumer.h>
0018 #include <linux/platform_device.h>
0019 #include <linux/err.h>
0020 #include <linux/clk.h>
0021 #include <linux/io.h>
0022 #include <linux/slab.h>
0023 #include <linux/pm_runtime.h>
0024 #include <linux/of.h>
0025 #include <linux/of_device.h>
0026 #include <linux/gcd.h>
0027 
0028 #include <linux/spi/spi.h>
0029 
0030 #include <linux/platform_data/spi-omap2-mcspi.h>
0031 
0032 #define OMAP2_MCSPI_MAX_FREQ        48000000
0033 #define OMAP2_MCSPI_MAX_DIVIDER     4096
0034 #define OMAP2_MCSPI_MAX_FIFODEPTH   64
0035 #define OMAP2_MCSPI_MAX_FIFOWCNT    0xFFFF
0036 #define SPI_AUTOSUSPEND_TIMEOUT     2000
0037 
0038 #define OMAP2_MCSPI_REVISION        0x00
0039 #define OMAP2_MCSPI_SYSSTATUS       0x14
0040 #define OMAP2_MCSPI_IRQSTATUS       0x18
0041 #define OMAP2_MCSPI_IRQENABLE       0x1c
0042 #define OMAP2_MCSPI_WAKEUPENABLE    0x20
0043 #define OMAP2_MCSPI_SYST        0x24
0044 #define OMAP2_MCSPI_MODULCTRL       0x28
0045 #define OMAP2_MCSPI_XFERLEVEL       0x7c
0046 
0047 /* per-channel banks, 0x14 bytes each, first is: */
0048 #define OMAP2_MCSPI_CHCONF0     0x2c
0049 #define OMAP2_MCSPI_CHSTAT0     0x30
0050 #define OMAP2_MCSPI_CHCTRL0     0x34
0051 #define OMAP2_MCSPI_TX0         0x38
0052 #define OMAP2_MCSPI_RX0         0x3c
0053 
0054 /* per-register bitmasks: */
0055 #define OMAP2_MCSPI_IRQSTATUS_EOW   BIT(17)
0056 
0057 #define OMAP2_MCSPI_MODULCTRL_SINGLE    BIT(0)
0058 #define OMAP2_MCSPI_MODULCTRL_MS    BIT(2)
0059 #define OMAP2_MCSPI_MODULCTRL_STEST BIT(3)
0060 
0061 #define OMAP2_MCSPI_CHCONF_PHA      BIT(0)
0062 #define OMAP2_MCSPI_CHCONF_POL      BIT(1)
0063 #define OMAP2_MCSPI_CHCONF_CLKD_MASK    (0x0f << 2)
0064 #define OMAP2_MCSPI_CHCONF_EPOL     BIT(6)
0065 #define OMAP2_MCSPI_CHCONF_WL_MASK  (0x1f << 7)
0066 #define OMAP2_MCSPI_CHCONF_TRM_RX_ONLY  BIT(12)
0067 #define OMAP2_MCSPI_CHCONF_TRM_TX_ONLY  BIT(13)
0068 #define OMAP2_MCSPI_CHCONF_TRM_MASK (0x03 << 12)
0069 #define OMAP2_MCSPI_CHCONF_DMAW     BIT(14)
0070 #define OMAP2_MCSPI_CHCONF_DMAR     BIT(15)
0071 #define OMAP2_MCSPI_CHCONF_DPE0     BIT(16)
0072 #define OMAP2_MCSPI_CHCONF_DPE1     BIT(17)
0073 #define OMAP2_MCSPI_CHCONF_IS       BIT(18)
0074 #define OMAP2_MCSPI_CHCONF_TURBO    BIT(19)
0075 #define OMAP2_MCSPI_CHCONF_FORCE    BIT(20)
0076 #define OMAP2_MCSPI_CHCONF_FFET     BIT(27)
0077 #define OMAP2_MCSPI_CHCONF_FFER     BIT(28)
0078 #define OMAP2_MCSPI_CHCONF_CLKG     BIT(29)
0079 
0080 #define OMAP2_MCSPI_CHSTAT_RXS      BIT(0)
0081 #define OMAP2_MCSPI_CHSTAT_TXS      BIT(1)
0082 #define OMAP2_MCSPI_CHSTAT_EOT      BIT(2)
0083 #define OMAP2_MCSPI_CHSTAT_TXFFE    BIT(3)
0084 
0085 #define OMAP2_MCSPI_CHCTRL_EN       BIT(0)
0086 #define OMAP2_MCSPI_CHCTRL_EXTCLK_MASK  (0xff << 8)
0087 
0088 #define OMAP2_MCSPI_WAKEUPENABLE_WKEN   BIT(0)
0089 
0090 /* We have 2 DMA channels per CS, one for RX and one for TX */
0091 struct omap2_mcspi_dma {
0092     struct dma_chan *dma_tx;
0093     struct dma_chan *dma_rx;
0094 
0095     struct completion dma_tx_completion;
0096     struct completion dma_rx_completion;
0097 
0098     char dma_rx_ch_name[14];
0099     char dma_tx_ch_name[14];
0100 };
0101 
0102 /* use PIO for small transfers, avoiding DMA setup/teardown overhead and
0103  * cache operations; better heuristics consider wordsize and bitrate.
0104  */
0105 #define DMA_MIN_BYTES           160
0106 
0107 
0108 /*
0109  * Used for context save and restore, structure members to be updated whenever
0110  * corresponding registers are modified.
0111  */
0112 struct omap2_mcspi_regs {
0113     u32 modulctrl;
0114     u32 wakeupenable;
0115     struct list_head cs;
0116 };
0117 
0118 struct omap2_mcspi {
0119     struct completion   txdone;
0120     struct spi_master   *master;
0121     /* Virtual base address of the controller */
0122     void __iomem        *base;
0123     unsigned long       phys;
0124     /* SPI1 has 4 channels, while SPI2 has 2 */
0125     struct omap2_mcspi_dma  *dma_channels;
0126     struct device       *dev;
0127     struct omap2_mcspi_regs ctx;
0128     int         fifo_depth;
0129     bool            slave_aborted;
0130     unsigned int        pin_dir:1;
0131     size_t          max_xfer_len;
0132 };
0133 
0134 struct omap2_mcspi_cs {
0135     void __iomem        *base;
0136     unsigned long       phys;
0137     int         word_len;
0138     u16         mode;
0139     struct list_head    node;
0140     /* Context save and restore shadow register */
0141     u32         chconf0, chctrl0;
0142 };
0143 
0144 static inline void mcspi_write_reg(struct spi_master *master,
0145         int idx, u32 val)
0146 {
0147     struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
0148 
0149     writel_relaxed(val, mcspi->base + idx);
0150 }
0151 
0152 static inline u32 mcspi_read_reg(struct spi_master *master, int idx)
0153 {
0154     struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
0155 
0156     return readl_relaxed(mcspi->base + idx);
0157 }
0158 
0159 static inline void mcspi_write_cs_reg(const struct spi_device *spi,
0160         int idx, u32 val)
0161 {
0162     struct omap2_mcspi_cs   *cs = spi->controller_state;
0163 
0164     writel_relaxed(val, cs->base +  idx);
0165 }
0166 
0167 static inline u32 mcspi_read_cs_reg(const struct spi_device *spi, int idx)
0168 {
0169     struct omap2_mcspi_cs   *cs = spi->controller_state;
0170 
0171     return readl_relaxed(cs->base + idx);
0172 }
0173 
0174 static inline u32 mcspi_cached_chconf0(const struct spi_device *spi)
0175 {
0176     struct omap2_mcspi_cs *cs = spi->controller_state;
0177 
0178     return cs->chconf0;
0179 }
0180 
0181 static inline void mcspi_write_chconf0(const struct spi_device *spi, u32 val)
0182 {
0183     struct omap2_mcspi_cs *cs = spi->controller_state;
0184 
0185     cs->chconf0 = val;
0186     mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCONF0, val);
0187     mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCONF0);
0188 }
0189 
0190 static inline int mcspi_bytes_per_word(int word_len)
0191 {
0192     if (word_len <= 8)
0193         return 1;
0194     else if (word_len <= 16)
0195         return 2;
0196     else /* word_len <= 32 */
0197         return 4;
0198 }
0199 
0200 static void omap2_mcspi_set_dma_req(const struct spi_device *spi,
0201         int is_read, int enable)
0202 {
0203     u32 l, rw;
0204 
0205     l = mcspi_cached_chconf0(spi);
0206 
0207     if (is_read) /* 1 is read, 0 write */
0208         rw = OMAP2_MCSPI_CHCONF_DMAR;
0209     else
0210         rw = OMAP2_MCSPI_CHCONF_DMAW;
0211 
0212     if (enable)
0213         l |= rw;
0214     else
0215         l &= ~rw;
0216 
0217     mcspi_write_chconf0(spi, l);
0218 }
0219 
0220 static void omap2_mcspi_set_enable(const struct spi_device *spi, int enable)
0221 {
0222     struct omap2_mcspi_cs *cs = spi->controller_state;
0223     u32 l;
0224 
0225     l = cs->chctrl0;
0226     if (enable)
0227         l |= OMAP2_MCSPI_CHCTRL_EN;
0228     else
0229         l &= ~OMAP2_MCSPI_CHCTRL_EN;
0230     cs->chctrl0 = l;
0231     mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCTRL0, cs->chctrl0);
0232     /* Flash post-writes */
0233     mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCTRL0);
0234 }
0235 
0236 static void omap2_mcspi_set_cs(struct spi_device *spi, bool enable)
0237 {
0238     struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master);
0239     u32 l;
0240 
0241     /* The controller handles the inverted chip selects
0242      * using the OMAP2_MCSPI_CHCONF_EPOL bit so revert
0243      * the inversion from the core spi_set_cs function.
0244      */
0245     if (spi->mode & SPI_CS_HIGH)
0246         enable = !enable;
0247 
0248     if (spi->controller_state) {
0249         int err = pm_runtime_resume_and_get(mcspi->dev);
0250         if (err < 0) {
0251             dev_err(mcspi->dev, "failed to get sync: %d\n", err);
0252             return;
0253         }
0254 
0255         l = mcspi_cached_chconf0(spi);
0256 
0257         if (enable)
0258             l &= ~OMAP2_MCSPI_CHCONF_FORCE;
0259         else
0260             l |= OMAP2_MCSPI_CHCONF_FORCE;
0261 
0262         mcspi_write_chconf0(spi, l);
0263 
0264         pm_runtime_mark_last_busy(mcspi->dev);
0265         pm_runtime_put_autosuspend(mcspi->dev);
0266     }
0267 }
0268 
0269 static void omap2_mcspi_set_mode(struct spi_master *master)
0270 {
0271     struct omap2_mcspi  *mcspi = spi_master_get_devdata(master);
0272     struct omap2_mcspi_regs *ctx = &mcspi->ctx;
0273     u32 l;
0274 
0275     /*
0276      * Choose master or slave mode
0277      */
0278     l = mcspi_read_reg(master, OMAP2_MCSPI_MODULCTRL);
0279     l &= ~(OMAP2_MCSPI_MODULCTRL_STEST);
0280     if (spi_controller_is_slave(master)) {
0281         l |= (OMAP2_MCSPI_MODULCTRL_MS);
0282     } else {
0283         l &= ~(OMAP2_MCSPI_MODULCTRL_MS);
0284         l |= OMAP2_MCSPI_MODULCTRL_SINGLE;
0285     }
0286     mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, l);
0287 
0288     ctx->modulctrl = l;
0289 }
0290 
0291 static void omap2_mcspi_set_fifo(const struct spi_device *spi,
0292                 struct spi_transfer *t, int enable)
0293 {
0294     struct spi_master *master = spi->master;
0295     struct omap2_mcspi_cs *cs = spi->controller_state;
0296     struct omap2_mcspi *mcspi;
0297     unsigned int wcnt;
0298     int max_fifo_depth, bytes_per_word;
0299     u32 chconf, xferlevel;
0300 
0301     mcspi = spi_master_get_devdata(master);
0302 
0303     chconf = mcspi_cached_chconf0(spi);
0304     if (enable) {
0305         bytes_per_word = mcspi_bytes_per_word(cs->word_len);
0306         if (t->len % bytes_per_word != 0)
0307             goto disable_fifo;
0308 
0309         if (t->rx_buf != NULL && t->tx_buf != NULL)
0310             max_fifo_depth = OMAP2_MCSPI_MAX_FIFODEPTH / 2;
0311         else
0312             max_fifo_depth = OMAP2_MCSPI_MAX_FIFODEPTH;
0313 
0314         wcnt = t->len / bytes_per_word;
0315         if (wcnt > OMAP2_MCSPI_MAX_FIFOWCNT)
0316             goto disable_fifo;
0317 
0318         xferlevel = wcnt << 16;
0319         if (t->rx_buf != NULL) {
0320             chconf |= OMAP2_MCSPI_CHCONF_FFER;
0321             xferlevel |= (bytes_per_word - 1) << 8;
0322         }
0323 
0324         if (t->tx_buf != NULL) {
0325             chconf |= OMAP2_MCSPI_CHCONF_FFET;
0326             xferlevel |= bytes_per_word - 1;
0327         }
0328 
0329         mcspi_write_reg(master, OMAP2_MCSPI_XFERLEVEL, xferlevel);
0330         mcspi_write_chconf0(spi, chconf);
0331         mcspi->fifo_depth = max_fifo_depth;
0332 
0333         return;
0334     }
0335 
0336 disable_fifo:
0337     if (t->rx_buf != NULL)
0338         chconf &= ~OMAP2_MCSPI_CHCONF_FFER;
0339 
0340     if (t->tx_buf != NULL)
0341         chconf &= ~OMAP2_MCSPI_CHCONF_FFET;
0342 
0343     mcspi_write_chconf0(spi, chconf);
0344     mcspi->fifo_depth = 0;
0345 }
0346 
0347 static int mcspi_wait_for_reg_bit(void __iomem *reg, unsigned long bit)
0348 {
0349     unsigned long timeout;
0350 
0351     timeout = jiffies + msecs_to_jiffies(1000);
0352     while (!(readl_relaxed(reg) & bit)) {
0353         if (time_after(jiffies, timeout)) {
0354             if (!(readl_relaxed(reg) & bit))
0355                 return -ETIMEDOUT;
0356             else
0357                 return 0;
0358         }
0359         cpu_relax();
0360     }
0361     return 0;
0362 }
0363 
0364 static int mcspi_wait_for_completion(struct  omap2_mcspi *mcspi,
0365                      struct completion *x)
0366 {
0367     if (spi_controller_is_slave(mcspi->master)) {
0368         if (wait_for_completion_interruptible(x) ||
0369             mcspi->slave_aborted)
0370             return -EINTR;
0371     } else {
0372         wait_for_completion(x);
0373     }
0374 
0375     return 0;
0376 }
0377 
0378 static void omap2_mcspi_rx_callback(void *data)
0379 {
0380     struct spi_device *spi = data;
0381     struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master);
0382     struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi->chip_select];
0383 
0384     /* We must disable the DMA RX request */
0385     omap2_mcspi_set_dma_req(spi, 1, 0);
0386 
0387     complete(&mcspi_dma->dma_rx_completion);
0388 }
0389 
0390 static void omap2_mcspi_tx_callback(void *data)
0391 {
0392     struct spi_device *spi = data;
0393     struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master);
0394     struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi->chip_select];
0395 
0396     /* We must disable the DMA TX request */
0397     omap2_mcspi_set_dma_req(spi, 0, 0);
0398 
0399     complete(&mcspi_dma->dma_tx_completion);
0400 }
0401 
0402 static void omap2_mcspi_tx_dma(struct spi_device *spi,
0403                 struct spi_transfer *xfer,
0404                 struct dma_slave_config cfg)
0405 {
0406     struct omap2_mcspi  *mcspi;
0407     struct omap2_mcspi_dma  *mcspi_dma;
0408     struct dma_async_tx_descriptor *tx;
0409 
0410     mcspi = spi_master_get_devdata(spi->master);
0411     mcspi_dma = &mcspi->dma_channels[spi->chip_select];
0412 
0413     dmaengine_slave_config(mcspi_dma->dma_tx, &cfg);
0414 
0415     tx = dmaengine_prep_slave_sg(mcspi_dma->dma_tx, xfer->tx_sg.sgl,
0416                      xfer->tx_sg.nents,
0417                      DMA_MEM_TO_DEV,
0418                      DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
0419     if (tx) {
0420         tx->callback = omap2_mcspi_tx_callback;
0421         tx->callback_param = spi;
0422         dmaengine_submit(tx);
0423     } else {
0424         /* FIXME: fall back to PIO? */
0425     }
0426     dma_async_issue_pending(mcspi_dma->dma_tx);
0427     omap2_mcspi_set_dma_req(spi, 0, 1);
0428 }
0429 
0430 static unsigned
0431 omap2_mcspi_rx_dma(struct spi_device *spi, struct spi_transfer *xfer,
0432                 struct dma_slave_config cfg,
0433                 unsigned es)
0434 {
0435     struct omap2_mcspi  *mcspi;
0436     struct omap2_mcspi_dma  *mcspi_dma;
0437     unsigned int        count, transfer_reduction = 0;
0438     struct scatterlist  *sg_out[2];
0439     int         nb_sizes = 0, out_mapped_nents[2], ret, x;
0440     size_t          sizes[2];
0441     u32         l;
0442     int         elements = 0;
0443     int         word_len, element_count;
0444     struct omap2_mcspi_cs   *cs = spi->controller_state;
0445     void __iomem        *chstat_reg = cs->base + OMAP2_MCSPI_CHSTAT0;
0446     struct dma_async_tx_descriptor *tx;
0447 
0448     mcspi = spi_master_get_devdata(spi->master);
0449     mcspi_dma = &mcspi->dma_channels[spi->chip_select];
0450     count = xfer->len;
0451 
0452     /*
0453      *  In the "End-of-Transfer Procedure" section for DMA RX in OMAP35x TRM
0454      *  it mentions reducing DMA transfer length by one element in master
0455      *  normal mode.
0456      */
0457     if (mcspi->fifo_depth == 0)
0458         transfer_reduction = es;
0459 
0460     word_len = cs->word_len;
0461     l = mcspi_cached_chconf0(spi);
0462 
0463     if (word_len <= 8)
0464         element_count = count;
0465     else if (word_len <= 16)
0466         element_count = count >> 1;
0467     else /* word_len <= 32 */
0468         element_count = count >> 2;
0469 
0470 
0471     dmaengine_slave_config(mcspi_dma->dma_rx, &cfg);
0472 
0473     /*
0474      *  Reduce DMA transfer length by one more if McSPI is
0475      *  configured in turbo mode.
0476      */
0477     if ((l & OMAP2_MCSPI_CHCONF_TURBO) && mcspi->fifo_depth == 0)
0478         transfer_reduction += es;
0479 
0480     if (transfer_reduction) {
0481         /* Split sgl into two. The second sgl won't be used. */
0482         sizes[0] = count - transfer_reduction;
0483         sizes[1] = transfer_reduction;
0484         nb_sizes = 2;
0485     } else {
0486         /*
0487          * Don't bother splitting the sgl. This essentially
0488          * clones the original sgl.
0489          */
0490         sizes[0] = count;
0491         nb_sizes = 1;
0492     }
0493 
0494     ret = sg_split(xfer->rx_sg.sgl, xfer->rx_sg.nents, 0, nb_sizes,
0495                sizes, sg_out, out_mapped_nents, GFP_KERNEL);
0496 
0497     if (ret < 0) {
0498         dev_err(&spi->dev, "sg_split failed\n");
0499         return 0;
0500     }
0501 
0502     tx = dmaengine_prep_slave_sg(mcspi_dma->dma_rx, sg_out[0],
0503                      out_mapped_nents[0], DMA_DEV_TO_MEM,
0504                      DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
0505     if (tx) {
0506         tx->callback = omap2_mcspi_rx_callback;
0507         tx->callback_param = spi;
0508         dmaengine_submit(tx);
0509     } else {
0510         /* FIXME: fall back to PIO? */
0511     }
0512 
0513     dma_async_issue_pending(mcspi_dma->dma_rx);
0514     omap2_mcspi_set_dma_req(spi, 1, 1);
0515 
0516     ret = mcspi_wait_for_completion(mcspi, &mcspi_dma->dma_rx_completion);
0517     if (ret || mcspi->slave_aborted) {
0518         dmaengine_terminate_sync(mcspi_dma->dma_rx);
0519         omap2_mcspi_set_dma_req(spi, 1, 0);
0520         return 0;
0521     }
0522 
0523     for (x = 0; x < nb_sizes; x++)
0524         kfree(sg_out[x]);
0525 
0526     if (mcspi->fifo_depth > 0)
0527         return count;
0528 
0529     /*
0530      *  Due to the DMA transfer length reduction the missing bytes must
0531      *  be read manually to receive all of the expected data.
0532      */
0533     omap2_mcspi_set_enable(spi, 0);
0534 
0535     elements = element_count - 1;
0536 
0537     if (l & OMAP2_MCSPI_CHCONF_TURBO) {
0538         elements--;
0539 
0540         if (!mcspi_wait_for_reg_bit(chstat_reg,
0541                         OMAP2_MCSPI_CHSTAT_RXS)) {
0542             u32 w;
0543 
0544             w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0);
0545             if (word_len <= 8)
0546                 ((u8 *)xfer->rx_buf)[elements++] = w;
0547             else if (word_len <= 16)
0548                 ((u16 *)xfer->rx_buf)[elements++] = w;
0549             else /* word_len <= 32 */
0550                 ((u32 *)xfer->rx_buf)[elements++] = w;
0551         } else {
0552             int bytes_per_word = mcspi_bytes_per_word(word_len);
0553             dev_err(&spi->dev, "DMA RX penultimate word empty\n");
0554             count -= (bytes_per_word << 1);
0555             omap2_mcspi_set_enable(spi, 1);
0556             return count;
0557         }
0558     }
0559     if (!mcspi_wait_for_reg_bit(chstat_reg, OMAP2_MCSPI_CHSTAT_RXS)) {
0560         u32 w;
0561 
0562         w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0);
0563         if (word_len <= 8)
0564             ((u8 *)xfer->rx_buf)[elements] = w;
0565         else if (word_len <= 16)
0566             ((u16 *)xfer->rx_buf)[elements] = w;
0567         else /* word_len <= 32 */
0568             ((u32 *)xfer->rx_buf)[elements] = w;
0569     } else {
0570         dev_err(&spi->dev, "DMA RX last word empty\n");
0571         count -= mcspi_bytes_per_word(word_len);
0572     }
0573     omap2_mcspi_set_enable(spi, 1);
0574     return count;
0575 }
0576 
0577 static unsigned
0578 omap2_mcspi_txrx_dma(struct spi_device *spi, struct spi_transfer *xfer)
0579 {
0580     struct omap2_mcspi  *mcspi;
0581     struct omap2_mcspi_cs   *cs = spi->controller_state;
0582     struct omap2_mcspi_dma  *mcspi_dma;
0583     unsigned int        count;
0584     u8          *rx;
0585     const u8        *tx;
0586     struct dma_slave_config cfg;
0587     enum dma_slave_buswidth width;
0588     unsigned es;
0589     void __iomem        *chstat_reg;
0590     void __iomem            *irqstat_reg;
0591     int         wait_res;
0592 
0593     mcspi = spi_master_get_devdata(spi->master);
0594     mcspi_dma = &mcspi->dma_channels[spi->chip_select];
0595 
0596     if (cs->word_len <= 8) {
0597         width = DMA_SLAVE_BUSWIDTH_1_BYTE;
0598         es = 1;
0599     } else if (cs->word_len <= 16) {
0600         width = DMA_SLAVE_BUSWIDTH_2_BYTES;
0601         es = 2;
0602     } else {
0603         width = DMA_SLAVE_BUSWIDTH_4_BYTES;
0604         es = 4;
0605     }
0606 
0607     count = xfer->len;
0608 
0609     memset(&cfg, 0, sizeof(cfg));
0610     cfg.src_addr = cs->phys + OMAP2_MCSPI_RX0;
0611     cfg.dst_addr = cs->phys + OMAP2_MCSPI_TX0;
0612     cfg.src_addr_width = width;
0613     cfg.dst_addr_width = width;
0614     cfg.src_maxburst = 1;
0615     cfg.dst_maxburst = 1;
0616 
0617     rx = xfer->rx_buf;
0618     tx = xfer->tx_buf;
0619 
0620     mcspi->slave_aborted = false;
0621     reinit_completion(&mcspi_dma->dma_tx_completion);
0622     reinit_completion(&mcspi_dma->dma_rx_completion);
0623     reinit_completion(&mcspi->txdone);
0624     if (tx) {
0625         /* Enable EOW IRQ to know end of tx in slave mode */
0626         if (spi_controller_is_slave(spi->master))
0627             mcspi_write_reg(spi->master,
0628                     OMAP2_MCSPI_IRQENABLE,
0629                     OMAP2_MCSPI_IRQSTATUS_EOW);
0630         omap2_mcspi_tx_dma(spi, xfer, cfg);
0631     }
0632 
0633     if (rx != NULL)
0634         count = omap2_mcspi_rx_dma(spi, xfer, cfg, es);
0635 
0636     if (tx != NULL) {
0637         int ret;
0638 
0639         ret = mcspi_wait_for_completion(mcspi, &mcspi_dma->dma_tx_completion);
0640         if (ret || mcspi->slave_aborted) {
0641             dmaengine_terminate_sync(mcspi_dma->dma_tx);
0642             omap2_mcspi_set_dma_req(spi, 0, 0);
0643             return 0;
0644         }
0645 
0646         if (spi_controller_is_slave(mcspi->master)) {
0647             ret = mcspi_wait_for_completion(mcspi, &mcspi->txdone);
0648             if (ret || mcspi->slave_aborted)
0649                 return 0;
0650         }
0651 
0652         if (mcspi->fifo_depth > 0) {
0653             irqstat_reg = mcspi->base + OMAP2_MCSPI_IRQSTATUS;
0654 
0655             if (mcspi_wait_for_reg_bit(irqstat_reg,
0656                         OMAP2_MCSPI_IRQSTATUS_EOW) < 0)
0657                 dev_err(&spi->dev, "EOW timed out\n");
0658 
0659             mcspi_write_reg(mcspi->master, OMAP2_MCSPI_IRQSTATUS,
0660                     OMAP2_MCSPI_IRQSTATUS_EOW);
0661         }
0662 
0663         /* for TX_ONLY mode, be sure all words have shifted out */
0664         if (rx == NULL) {
0665             chstat_reg = cs->base + OMAP2_MCSPI_CHSTAT0;
0666             if (mcspi->fifo_depth > 0) {
0667                 wait_res = mcspi_wait_for_reg_bit(chstat_reg,
0668                         OMAP2_MCSPI_CHSTAT_TXFFE);
0669                 if (wait_res < 0)
0670                     dev_err(&spi->dev, "TXFFE timed out\n");
0671             } else {
0672                 wait_res = mcspi_wait_for_reg_bit(chstat_reg,
0673                         OMAP2_MCSPI_CHSTAT_TXS);
0674                 if (wait_res < 0)
0675                     dev_err(&spi->dev, "TXS timed out\n");
0676             }
0677             if (wait_res >= 0 &&
0678                 (mcspi_wait_for_reg_bit(chstat_reg,
0679                     OMAP2_MCSPI_CHSTAT_EOT) < 0))
0680                 dev_err(&spi->dev, "EOT timed out\n");
0681         }
0682     }
0683     return count;
0684 }
0685 
0686 static unsigned
0687 omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
0688 {
0689     struct omap2_mcspi_cs   *cs = spi->controller_state;
0690     unsigned int        count, c;
0691     u32         l;
0692     void __iomem        *base = cs->base;
0693     void __iomem        *tx_reg;
0694     void __iomem        *rx_reg;
0695     void __iomem        *chstat_reg;
0696     int         word_len;
0697 
0698     count = xfer->len;
0699     c = count;
0700     word_len = cs->word_len;
0701 
0702     l = mcspi_cached_chconf0(spi);
0703 
0704     /* We store the pre-calculated register addresses on stack to speed
0705      * up the transfer loop. */
0706     tx_reg      = base + OMAP2_MCSPI_TX0;
0707     rx_reg      = base + OMAP2_MCSPI_RX0;
0708     chstat_reg  = base + OMAP2_MCSPI_CHSTAT0;
0709 
0710     if (c < (word_len>>3))
0711         return 0;
0712 
0713     if (word_len <= 8) {
0714         u8      *rx;
0715         const u8    *tx;
0716 
0717         rx = xfer->rx_buf;
0718         tx = xfer->tx_buf;
0719 
0720         do {
0721             c -= 1;
0722             if (tx != NULL) {
0723                 if (mcspi_wait_for_reg_bit(chstat_reg,
0724                         OMAP2_MCSPI_CHSTAT_TXS) < 0) {
0725                     dev_err(&spi->dev, "TXS timed out\n");
0726                     goto out;
0727                 }
0728                 dev_vdbg(&spi->dev, "write-%d %02x\n",
0729                         word_len, *tx);
0730                 writel_relaxed(*tx++, tx_reg);
0731             }
0732             if (rx != NULL) {
0733                 if (mcspi_wait_for_reg_bit(chstat_reg,
0734                         OMAP2_MCSPI_CHSTAT_RXS) < 0) {
0735                     dev_err(&spi->dev, "RXS timed out\n");
0736                     goto out;
0737                 }
0738 
0739                 if (c == 1 && tx == NULL &&
0740                     (l & OMAP2_MCSPI_CHCONF_TURBO)) {
0741                     omap2_mcspi_set_enable(spi, 0);
0742                     *rx++ = readl_relaxed(rx_reg);
0743                     dev_vdbg(&spi->dev, "read-%d %02x\n",
0744                             word_len, *(rx - 1));
0745                     if (mcspi_wait_for_reg_bit(chstat_reg,
0746                         OMAP2_MCSPI_CHSTAT_RXS) < 0) {
0747                         dev_err(&spi->dev,
0748                             "RXS timed out\n");
0749                         goto out;
0750                     }
0751                     c = 0;
0752                 } else if (c == 0 && tx == NULL) {
0753                     omap2_mcspi_set_enable(spi, 0);
0754                 }
0755 
0756                 *rx++ = readl_relaxed(rx_reg);
0757                 dev_vdbg(&spi->dev, "read-%d %02x\n",
0758                         word_len, *(rx - 1));
0759             }
0760             /* Add word delay between each word */
0761             spi_delay_exec(&xfer->word_delay, xfer);
0762         } while (c);
0763     } else if (word_len <= 16) {
0764         u16     *rx;
0765         const u16   *tx;
0766 
0767         rx = xfer->rx_buf;
0768         tx = xfer->tx_buf;
0769         do {
0770             c -= 2;
0771             if (tx != NULL) {
0772                 if (mcspi_wait_for_reg_bit(chstat_reg,
0773                         OMAP2_MCSPI_CHSTAT_TXS) < 0) {
0774                     dev_err(&spi->dev, "TXS timed out\n");
0775                     goto out;
0776                 }
0777                 dev_vdbg(&spi->dev, "write-%d %04x\n",
0778                         word_len, *tx);
0779                 writel_relaxed(*tx++, tx_reg);
0780             }
0781             if (rx != NULL) {
0782                 if (mcspi_wait_for_reg_bit(chstat_reg,
0783                         OMAP2_MCSPI_CHSTAT_RXS) < 0) {
0784                     dev_err(&spi->dev, "RXS timed out\n");
0785                     goto out;
0786                 }
0787 
0788                 if (c == 2 && tx == NULL &&
0789                     (l & OMAP2_MCSPI_CHCONF_TURBO)) {
0790                     omap2_mcspi_set_enable(spi, 0);
0791                     *rx++ = readl_relaxed(rx_reg);
0792                     dev_vdbg(&spi->dev, "read-%d %04x\n",
0793                             word_len, *(rx - 1));
0794                     if (mcspi_wait_for_reg_bit(chstat_reg,
0795                         OMAP2_MCSPI_CHSTAT_RXS) < 0) {
0796                         dev_err(&spi->dev,
0797                             "RXS timed out\n");
0798                         goto out;
0799                     }
0800                     c = 0;
0801                 } else if (c == 0 && tx == NULL) {
0802                     omap2_mcspi_set_enable(spi, 0);
0803                 }
0804 
0805                 *rx++ = readl_relaxed(rx_reg);
0806                 dev_vdbg(&spi->dev, "read-%d %04x\n",
0807                         word_len, *(rx - 1));
0808             }
0809             /* Add word delay between each word */
0810             spi_delay_exec(&xfer->word_delay, xfer);
0811         } while (c >= 2);
0812     } else if (word_len <= 32) {
0813         u32     *rx;
0814         const u32   *tx;
0815 
0816         rx = xfer->rx_buf;
0817         tx = xfer->tx_buf;
0818         do {
0819             c -= 4;
0820             if (tx != NULL) {
0821                 if (mcspi_wait_for_reg_bit(chstat_reg,
0822                         OMAP2_MCSPI_CHSTAT_TXS) < 0) {
0823                     dev_err(&spi->dev, "TXS timed out\n");
0824                     goto out;
0825                 }
0826                 dev_vdbg(&spi->dev, "write-%d %08x\n",
0827                         word_len, *tx);
0828                 writel_relaxed(*tx++, tx_reg);
0829             }
0830             if (rx != NULL) {
0831                 if (mcspi_wait_for_reg_bit(chstat_reg,
0832                         OMAP2_MCSPI_CHSTAT_RXS) < 0) {
0833                     dev_err(&spi->dev, "RXS timed out\n");
0834                     goto out;
0835                 }
0836 
0837                 if (c == 4 && tx == NULL &&
0838                     (l & OMAP2_MCSPI_CHCONF_TURBO)) {
0839                     omap2_mcspi_set_enable(spi, 0);
0840                     *rx++ = readl_relaxed(rx_reg);
0841                     dev_vdbg(&spi->dev, "read-%d %08x\n",
0842                             word_len, *(rx - 1));
0843                     if (mcspi_wait_for_reg_bit(chstat_reg,
0844                         OMAP2_MCSPI_CHSTAT_RXS) < 0) {
0845                         dev_err(&spi->dev,
0846                             "RXS timed out\n");
0847                         goto out;
0848                     }
0849                     c = 0;
0850                 } else if (c == 0 && tx == NULL) {
0851                     omap2_mcspi_set_enable(spi, 0);
0852                 }
0853 
0854                 *rx++ = readl_relaxed(rx_reg);
0855                 dev_vdbg(&spi->dev, "read-%d %08x\n",
0856                         word_len, *(rx - 1));
0857             }
0858             /* Add word delay between each word */
0859             spi_delay_exec(&xfer->word_delay, xfer);
0860         } while (c >= 4);
0861     }
0862 
0863     /* for TX_ONLY mode, be sure all words have shifted out */
0864     if (xfer->rx_buf == NULL) {
0865         if (mcspi_wait_for_reg_bit(chstat_reg,
0866                 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
0867             dev_err(&spi->dev, "TXS timed out\n");
0868         } else if (mcspi_wait_for_reg_bit(chstat_reg,
0869                 OMAP2_MCSPI_CHSTAT_EOT) < 0)
0870             dev_err(&spi->dev, "EOT timed out\n");
0871 
0872         /* disable chan to purge rx datas received in TX_ONLY transfer,
0873          * otherwise these rx datas will affect the direct following
0874          * RX_ONLY transfer.
0875          */
0876         omap2_mcspi_set_enable(spi, 0);
0877     }
0878 out:
0879     omap2_mcspi_set_enable(spi, 1);
0880     return count - c;
0881 }
0882 
0883 static u32 omap2_mcspi_calc_divisor(u32 speed_hz)
0884 {
0885     u32 div;
0886 
0887     for (div = 0; div < 15; div++)
0888         if (speed_hz >= (OMAP2_MCSPI_MAX_FREQ >> div))
0889             return div;
0890 
0891     return 15;
0892 }
0893 
0894 /* called only when no transfer is active to this device */
0895 static int omap2_mcspi_setup_transfer(struct spi_device *spi,
0896         struct spi_transfer *t)
0897 {
0898     struct omap2_mcspi_cs *cs = spi->controller_state;
0899     struct omap2_mcspi *mcspi;
0900     u32 l = 0, clkd = 0, div, extclk = 0, clkg = 0;
0901     u8 word_len = spi->bits_per_word;
0902     u32 speed_hz = spi->max_speed_hz;
0903 
0904     mcspi = spi_master_get_devdata(spi->master);
0905 
0906     if (t != NULL && t->bits_per_word)
0907         word_len = t->bits_per_word;
0908 
0909     cs->word_len = word_len;
0910 
0911     if (t && t->speed_hz)
0912         speed_hz = t->speed_hz;
0913 
0914     speed_hz = min_t(u32, speed_hz, OMAP2_MCSPI_MAX_FREQ);
0915     if (speed_hz < (OMAP2_MCSPI_MAX_FREQ / OMAP2_MCSPI_MAX_DIVIDER)) {
0916         clkd = omap2_mcspi_calc_divisor(speed_hz);
0917         speed_hz = OMAP2_MCSPI_MAX_FREQ >> clkd;
0918         clkg = 0;
0919     } else {
0920         div = (OMAP2_MCSPI_MAX_FREQ + speed_hz - 1) / speed_hz;
0921         speed_hz = OMAP2_MCSPI_MAX_FREQ / div;
0922         clkd = (div - 1) & 0xf;
0923         extclk = (div - 1) >> 4;
0924         clkg = OMAP2_MCSPI_CHCONF_CLKG;
0925     }
0926 
0927     l = mcspi_cached_chconf0(spi);
0928 
0929     /* standard 4-wire master mode:  SCK, MOSI/out, MISO/in, nCS
0930      * REVISIT: this controller could support SPI_3WIRE mode.
0931      */
0932     if (mcspi->pin_dir == MCSPI_PINDIR_D0_IN_D1_OUT) {
0933         l &= ~OMAP2_MCSPI_CHCONF_IS;
0934         l &= ~OMAP2_MCSPI_CHCONF_DPE1;
0935         l |= OMAP2_MCSPI_CHCONF_DPE0;
0936     } else {
0937         l |= OMAP2_MCSPI_CHCONF_IS;
0938         l |= OMAP2_MCSPI_CHCONF_DPE1;
0939         l &= ~OMAP2_MCSPI_CHCONF_DPE0;
0940     }
0941 
0942     /* wordlength */
0943     l &= ~OMAP2_MCSPI_CHCONF_WL_MASK;
0944     l |= (word_len - 1) << 7;
0945 
0946     /* set chipselect polarity; manage with FORCE */
0947     if (!(spi->mode & SPI_CS_HIGH))
0948         l |= OMAP2_MCSPI_CHCONF_EPOL;   /* active-low; normal */
0949     else
0950         l &= ~OMAP2_MCSPI_CHCONF_EPOL;
0951 
0952     /* set clock divisor */
0953     l &= ~OMAP2_MCSPI_CHCONF_CLKD_MASK;
0954     l |= clkd << 2;
0955 
0956     /* set clock granularity */
0957     l &= ~OMAP2_MCSPI_CHCONF_CLKG;
0958     l |= clkg;
0959     if (clkg) {
0960         cs->chctrl0 &= ~OMAP2_MCSPI_CHCTRL_EXTCLK_MASK;
0961         cs->chctrl0 |= extclk << 8;
0962         mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCTRL0, cs->chctrl0);
0963     }
0964 
0965     /* set SPI mode 0..3 */
0966     if (spi->mode & SPI_CPOL)
0967         l |= OMAP2_MCSPI_CHCONF_POL;
0968     else
0969         l &= ~OMAP2_MCSPI_CHCONF_POL;
0970     if (spi->mode & SPI_CPHA)
0971         l |= OMAP2_MCSPI_CHCONF_PHA;
0972     else
0973         l &= ~OMAP2_MCSPI_CHCONF_PHA;
0974 
0975     mcspi_write_chconf0(spi, l);
0976 
0977     cs->mode = spi->mode;
0978 
0979     dev_dbg(&spi->dev, "setup: speed %d, sample %s edge, clk %s\n",
0980             speed_hz,
0981             (spi->mode & SPI_CPHA) ? "trailing" : "leading",
0982             (spi->mode & SPI_CPOL) ? "inverted" : "normal");
0983 
0984     return 0;
0985 }
0986 
0987 /*
0988  * Note that we currently allow DMA only if we get a channel
0989  * for both rx and tx. Otherwise we'll do PIO for both rx and tx.
0990  */
0991 static int omap2_mcspi_request_dma(struct omap2_mcspi *mcspi,
0992                    struct omap2_mcspi_dma *mcspi_dma)
0993 {
0994     int ret = 0;
0995 
0996     mcspi_dma->dma_rx = dma_request_chan(mcspi->dev,
0997                          mcspi_dma->dma_rx_ch_name);
0998     if (IS_ERR(mcspi_dma->dma_rx)) {
0999         ret = PTR_ERR(mcspi_dma->dma_rx);
1000         mcspi_dma->dma_rx = NULL;
1001         goto no_dma;
1002     }
1003 
1004     mcspi_dma->dma_tx = dma_request_chan(mcspi->dev,
1005                          mcspi_dma->dma_tx_ch_name);
1006     if (IS_ERR(mcspi_dma->dma_tx)) {
1007         ret = PTR_ERR(mcspi_dma->dma_tx);
1008         mcspi_dma->dma_tx = NULL;
1009         dma_release_channel(mcspi_dma->dma_rx);
1010         mcspi_dma->dma_rx = NULL;
1011     }
1012 
1013     init_completion(&mcspi_dma->dma_rx_completion);
1014     init_completion(&mcspi_dma->dma_tx_completion);
1015 
1016 no_dma:
1017     return ret;
1018 }
1019 
1020 static void omap2_mcspi_release_dma(struct spi_master *master)
1021 {
1022     struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
1023     struct omap2_mcspi_dma  *mcspi_dma;
1024     int i;
1025 
1026     for (i = 0; i < master->num_chipselect; i++) {
1027         mcspi_dma = &mcspi->dma_channels[i];
1028 
1029         if (mcspi_dma->dma_rx) {
1030             dma_release_channel(mcspi_dma->dma_rx);
1031             mcspi_dma->dma_rx = NULL;
1032         }
1033         if (mcspi_dma->dma_tx) {
1034             dma_release_channel(mcspi_dma->dma_tx);
1035             mcspi_dma->dma_tx = NULL;
1036         }
1037     }
1038 }
1039 
1040 static void omap2_mcspi_cleanup(struct spi_device *spi)
1041 {
1042     struct omap2_mcspi_cs   *cs;
1043 
1044     if (spi->controller_state) {
1045         /* Unlink controller state from context save list */
1046         cs = spi->controller_state;
1047         list_del(&cs->node);
1048 
1049         kfree(cs);
1050     }
1051 }
1052 
1053 static int omap2_mcspi_setup(struct spi_device *spi)
1054 {
1055     bool            initial_setup = false;
1056     int         ret;
1057     struct omap2_mcspi  *mcspi = spi_master_get_devdata(spi->master);
1058     struct omap2_mcspi_regs *ctx = &mcspi->ctx;
1059     struct omap2_mcspi_cs   *cs = spi->controller_state;
1060 
1061     if (!cs) {
1062         cs = kzalloc(sizeof(*cs), GFP_KERNEL);
1063         if (!cs)
1064             return -ENOMEM;
1065         cs->base = mcspi->base + spi->chip_select * 0x14;
1066         cs->phys = mcspi->phys + spi->chip_select * 0x14;
1067         cs->mode = 0;
1068         cs->chconf0 = 0;
1069         cs->chctrl0 = 0;
1070         spi->controller_state = cs;
1071         /* Link this to context save list */
1072         list_add_tail(&cs->node, &ctx->cs);
1073         initial_setup = true;
1074     }
1075 
1076     ret = pm_runtime_resume_and_get(mcspi->dev);
1077     if (ret < 0) {
1078         if (initial_setup)
1079             omap2_mcspi_cleanup(spi);
1080 
1081         return ret;
1082     }
1083 
1084     ret = omap2_mcspi_setup_transfer(spi, NULL);
1085     if (ret && initial_setup)
1086         omap2_mcspi_cleanup(spi);
1087 
1088     pm_runtime_mark_last_busy(mcspi->dev);
1089     pm_runtime_put_autosuspend(mcspi->dev);
1090 
1091     return ret;
1092 }
1093 
1094 static irqreturn_t omap2_mcspi_irq_handler(int irq, void *data)
1095 {
1096     struct omap2_mcspi *mcspi = data;
1097     u32 irqstat;
1098 
1099     irqstat = mcspi_read_reg(mcspi->master, OMAP2_MCSPI_IRQSTATUS);
1100     if (!irqstat)
1101         return IRQ_NONE;
1102 
1103     /* Disable IRQ and wakeup slave xfer task */
1104     mcspi_write_reg(mcspi->master, OMAP2_MCSPI_IRQENABLE, 0);
1105     if (irqstat & OMAP2_MCSPI_IRQSTATUS_EOW)
1106         complete(&mcspi->txdone);
1107 
1108     return IRQ_HANDLED;
1109 }
1110 
1111 static int omap2_mcspi_slave_abort(struct spi_master *master)
1112 {
1113     struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
1114     struct omap2_mcspi_dma *mcspi_dma = mcspi->dma_channels;
1115 
1116     mcspi->slave_aborted = true;
1117     complete(&mcspi_dma->dma_rx_completion);
1118     complete(&mcspi_dma->dma_tx_completion);
1119     complete(&mcspi->txdone);
1120 
1121     return 0;
1122 }
1123 
1124 static int omap2_mcspi_transfer_one(struct spi_master *master,
1125                     struct spi_device *spi,
1126                     struct spi_transfer *t)
1127 {
1128 
1129     /* We only enable one channel at a time -- the one whose message is
1130      * -- although this controller would gladly
1131      * arbitrate among multiple channels.  This corresponds to "single
1132      * channel" master mode.  As a side effect, we need to manage the
1133      * chipselect with the FORCE bit ... CS != channel enable.
1134      */
1135 
1136     struct omap2_mcspi      *mcspi;
1137     struct omap2_mcspi_dma      *mcspi_dma;
1138     struct omap2_mcspi_cs       *cs;
1139     struct omap2_mcspi_device_config *cd;
1140     int             par_override = 0;
1141     int             status = 0;
1142     u32             chconf;
1143 
1144     mcspi = spi_master_get_devdata(master);
1145     mcspi_dma = mcspi->dma_channels + spi->chip_select;
1146     cs = spi->controller_state;
1147     cd = spi->controller_data;
1148 
1149     /*
1150      * The slave driver could have changed spi->mode in which case
1151      * it will be different from cs->mode (the current hardware setup).
1152      * If so, set par_override (even though its not a parity issue) so
1153      * omap2_mcspi_setup_transfer will be called to configure the hardware
1154      * with the correct mode on the first iteration of the loop below.
1155      */
1156     if (spi->mode != cs->mode)
1157         par_override = 1;
1158 
1159     omap2_mcspi_set_enable(spi, 0);
1160 
1161     if (spi->cs_gpiod)
1162         omap2_mcspi_set_cs(spi, spi->mode & SPI_CS_HIGH);
1163 
1164     if (par_override ||
1165         (t->speed_hz != spi->max_speed_hz) ||
1166         (t->bits_per_word != spi->bits_per_word)) {
1167         par_override = 1;
1168         status = omap2_mcspi_setup_transfer(spi, t);
1169         if (status < 0)
1170             goto out;
1171         if (t->speed_hz == spi->max_speed_hz &&
1172             t->bits_per_word == spi->bits_per_word)
1173             par_override = 0;
1174     }
1175     if (cd && cd->cs_per_word) {
1176         chconf = mcspi->ctx.modulctrl;
1177         chconf &= ~OMAP2_MCSPI_MODULCTRL_SINGLE;
1178         mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, chconf);
1179         mcspi->ctx.modulctrl =
1180             mcspi_read_cs_reg(spi, OMAP2_MCSPI_MODULCTRL);
1181     }
1182 
1183     chconf = mcspi_cached_chconf0(spi);
1184     chconf &= ~OMAP2_MCSPI_CHCONF_TRM_MASK;
1185     chconf &= ~OMAP2_MCSPI_CHCONF_TURBO;
1186 
1187     if (t->tx_buf == NULL)
1188         chconf |= OMAP2_MCSPI_CHCONF_TRM_RX_ONLY;
1189     else if (t->rx_buf == NULL)
1190         chconf |= OMAP2_MCSPI_CHCONF_TRM_TX_ONLY;
1191 
1192     if (cd && cd->turbo_mode && t->tx_buf == NULL) {
1193         /* Turbo mode is for more than one word */
1194         if (t->len > ((cs->word_len + 7) >> 3))
1195             chconf |= OMAP2_MCSPI_CHCONF_TURBO;
1196     }
1197 
1198     mcspi_write_chconf0(spi, chconf);
1199 
1200     if (t->len) {
1201         unsigned    count;
1202 
1203         if ((mcspi_dma->dma_rx && mcspi_dma->dma_tx) &&
1204             master->cur_msg_mapped &&
1205             master->can_dma(master, spi, t))
1206             omap2_mcspi_set_fifo(spi, t, 1);
1207 
1208         omap2_mcspi_set_enable(spi, 1);
1209 
1210         /* RX_ONLY mode needs dummy data in TX reg */
1211         if (t->tx_buf == NULL)
1212             writel_relaxed(0, cs->base
1213                     + OMAP2_MCSPI_TX0);
1214 
1215         if ((mcspi_dma->dma_rx && mcspi_dma->dma_tx) &&
1216             master->cur_msg_mapped &&
1217             master->can_dma(master, spi, t))
1218             count = omap2_mcspi_txrx_dma(spi, t);
1219         else
1220             count = omap2_mcspi_txrx_pio(spi, t);
1221 
1222         if (count != t->len) {
1223             status = -EIO;
1224             goto out;
1225         }
1226     }
1227 
1228     omap2_mcspi_set_enable(spi, 0);
1229 
1230     if (mcspi->fifo_depth > 0)
1231         omap2_mcspi_set_fifo(spi, t, 0);
1232 
1233 out:
1234     /* Restore defaults if they were overriden */
1235     if (par_override) {
1236         par_override = 0;
1237         status = omap2_mcspi_setup_transfer(spi, NULL);
1238     }
1239 
1240     if (cd && cd->cs_per_word) {
1241         chconf = mcspi->ctx.modulctrl;
1242         chconf |= OMAP2_MCSPI_MODULCTRL_SINGLE;
1243         mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, chconf);
1244         mcspi->ctx.modulctrl =
1245             mcspi_read_cs_reg(spi, OMAP2_MCSPI_MODULCTRL);
1246     }
1247 
1248     omap2_mcspi_set_enable(spi, 0);
1249 
1250     if (spi->cs_gpiod)
1251         omap2_mcspi_set_cs(spi, !(spi->mode & SPI_CS_HIGH));
1252 
1253     if (mcspi->fifo_depth > 0 && t)
1254         omap2_mcspi_set_fifo(spi, t, 0);
1255 
1256     return status;
1257 }
1258 
1259 static int omap2_mcspi_prepare_message(struct spi_master *master,
1260                        struct spi_message *msg)
1261 {
1262     struct omap2_mcspi  *mcspi = spi_master_get_devdata(master);
1263     struct omap2_mcspi_regs *ctx = &mcspi->ctx;
1264     struct omap2_mcspi_cs   *cs;
1265 
1266     /* Only a single channel can have the FORCE bit enabled
1267      * in its chconf0 register.
1268      * Scan all channels and disable them except the current one.
1269      * A FORCE can remain from a last transfer having cs_change enabled
1270      */
1271     list_for_each_entry(cs, &ctx->cs, node) {
1272         if (msg->spi->controller_state == cs)
1273             continue;
1274 
1275         if ((cs->chconf0 & OMAP2_MCSPI_CHCONF_FORCE)) {
1276             cs->chconf0 &= ~OMAP2_MCSPI_CHCONF_FORCE;
1277             writel_relaxed(cs->chconf0,
1278                     cs->base + OMAP2_MCSPI_CHCONF0);
1279             readl_relaxed(cs->base + OMAP2_MCSPI_CHCONF0);
1280         }
1281     }
1282 
1283     return 0;
1284 }
1285 
1286 static bool omap2_mcspi_can_dma(struct spi_master *master,
1287                 struct spi_device *spi,
1288                 struct spi_transfer *xfer)
1289 {
1290     struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master);
1291     struct omap2_mcspi_dma *mcspi_dma =
1292         &mcspi->dma_channels[spi->chip_select];
1293 
1294     if (!mcspi_dma->dma_rx || !mcspi_dma->dma_tx)
1295         return false;
1296 
1297     if (spi_controller_is_slave(master))
1298         return true;
1299 
1300     master->dma_rx = mcspi_dma->dma_rx;
1301     master->dma_tx = mcspi_dma->dma_tx;
1302 
1303     return (xfer->len >= DMA_MIN_BYTES);
1304 }
1305 
1306 static size_t omap2_mcspi_max_xfer_size(struct spi_device *spi)
1307 {
1308     struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master);
1309     struct omap2_mcspi_dma *mcspi_dma =
1310         &mcspi->dma_channels[spi->chip_select];
1311 
1312     if (mcspi->max_xfer_len && mcspi_dma->dma_rx)
1313         return mcspi->max_xfer_len;
1314 
1315     return SIZE_MAX;
1316 }
1317 
1318 static int omap2_mcspi_controller_setup(struct omap2_mcspi *mcspi)
1319 {
1320     struct spi_master   *master = mcspi->master;
1321     struct omap2_mcspi_regs *ctx = &mcspi->ctx;
1322     int         ret = 0;
1323 
1324     ret = pm_runtime_resume_and_get(mcspi->dev);
1325     if (ret < 0)
1326         return ret;
1327 
1328     mcspi_write_reg(master, OMAP2_MCSPI_WAKEUPENABLE,
1329             OMAP2_MCSPI_WAKEUPENABLE_WKEN);
1330     ctx->wakeupenable = OMAP2_MCSPI_WAKEUPENABLE_WKEN;
1331 
1332     omap2_mcspi_set_mode(master);
1333     pm_runtime_mark_last_busy(mcspi->dev);
1334     pm_runtime_put_autosuspend(mcspi->dev);
1335     return 0;
1336 }
1337 
1338 static int omap_mcspi_runtime_suspend(struct device *dev)
1339 {
1340     int error;
1341 
1342     error = pinctrl_pm_select_idle_state(dev);
1343     if (error)
1344         dev_warn(dev, "%s: failed to set pins: %i\n", __func__, error);
1345 
1346     return 0;
1347 }
1348 
1349 /*
1350  * When SPI wake up from off-mode, CS is in activate state. If it was in
1351  * inactive state when driver was suspend, then force it to inactive state at
1352  * wake up.
1353  */
1354 static int omap_mcspi_runtime_resume(struct device *dev)
1355 {
1356     struct spi_master *master = dev_get_drvdata(dev);
1357     struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
1358     struct omap2_mcspi_regs *ctx = &mcspi->ctx;
1359     struct omap2_mcspi_cs *cs;
1360     int error;
1361 
1362     error = pinctrl_pm_select_default_state(dev);
1363     if (error)
1364         dev_warn(dev, "%s: failed to set pins: %i\n", __func__, error);
1365 
1366     /* McSPI: context restore */
1367     mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, ctx->modulctrl);
1368     mcspi_write_reg(master, OMAP2_MCSPI_WAKEUPENABLE, ctx->wakeupenable);
1369 
1370     list_for_each_entry(cs, &ctx->cs, node) {
1371         /*
1372          * We need to toggle CS state for OMAP take this
1373          * change in account.
1374          */
1375         if ((cs->chconf0 & OMAP2_MCSPI_CHCONF_FORCE) == 0) {
1376             cs->chconf0 |= OMAP2_MCSPI_CHCONF_FORCE;
1377             writel_relaxed(cs->chconf0,
1378                        cs->base + OMAP2_MCSPI_CHCONF0);
1379             cs->chconf0 &= ~OMAP2_MCSPI_CHCONF_FORCE;
1380             writel_relaxed(cs->chconf0,
1381                        cs->base + OMAP2_MCSPI_CHCONF0);
1382         } else {
1383             writel_relaxed(cs->chconf0,
1384                        cs->base + OMAP2_MCSPI_CHCONF0);
1385         }
1386     }
1387 
1388     return 0;
1389 }
1390 
1391 static struct omap2_mcspi_platform_config omap2_pdata = {
1392     .regs_offset = 0,
1393 };
1394 
1395 static struct omap2_mcspi_platform_config omap4_pdata = {
1396     .regs_offset = OMAP4_MCSPI_REG_OFFSET,
1397 };
1398 
1399 static struct omap2_mcspi_platform_config am654_pdata = {
1400     .regs_offset = OMAP4_MCSPI_REG_OFFSET,
1401     .max_xfer_len = SZ_4K - 1,
1402 };
1403 
1404 static const struct of_device_id omap_mcspi_of_match[] = {
1405     {
1406         .compatible = "ti,omap2-mcspi",
1407         .data = &omap2_pdata,
1408     },
1409     {
1410         .compatible = "ti,omap4-mcspi",
1411         .data = &omap4_pdata,
1412     },
1413     {
1414         .compatible = "ti,am654-mcspi",
1415         .data = &am654_pdata,
1416     },
1417     { },
1418 };
1419 MODULE_DEVICE_TABLE(of, omap_mcspi_of_match);
1420 
1421 static int omap2_mcspi_probe(struct platform_device *pdev)
1422 {
1423     struct spi_master   *master;
1424     const struct omap2_mcspi_platform_config *pdata;
1425     struct omap2_mcspi  *mcspi;
1426     struct resource     *r;
1427     int         status = 0, i;
1428     u32         regs_offset = 0;
1429     struct device_node  *node = pdev->dev.of_node;
1430     const struct of_device_id *match;
1431 
1432     if (of_property_read_bool(node, "spi-slave"))
1433         master = spi_alloc_slave(&pdev->dev, sizeof(*mcspi));
1434     else
1435         master = spi_alloc_master(&pdev->dev, sizeof(*mcspi));
1436     if (!master)
1437         return -ENOMEM;
1438 
1439     /* the spi->mode bits understood by this driver: */
1440     master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1441     master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
1442     master->setup = omap2_mcspi_setup;
1443     master->auto_runtime_pm = true;
1444     master->prepare_message = omap2_mcspi_prepare_message;
1445     master->can_dma = omap2_mcspi_can_dma;
1446     master->transfer_one = omap2_mcspi_transfer_one;
1447     master->set_cs = omap2_mcspi_set_cs;
1448     master->cleanup = omap2_mcspi_cleanup;
1449     master->slave_abort = omap2_mcspi_slave_abort;
1450     master->dev.of_node = node;
1451     master->max_speed_hz = OMAP2_MCSPI_MAX_FREQ;
1452     master->min_speed_hz = OMAP2_MCSPI_MAX_FREQ >> 15;
1453     master->use_gpio_descriptors = true;
1454 
1455     platform_set_drvdata(pdev, master);
1456 
1457     mcspi = spi_master_get_devdata(master);
1458     mcspi->master = master;
1459 
1460     match = of_match_device(omap_mcspi_of_match, &pdev->dev);
1461     if (match) {
1462         u32 num_cs = 1; /* default number of chipselect */
1463         pdata = match->data;
1464 
1465         of_property_read_u32(node, "ti,spi-num-cs", &num_cs);
1466         master->num_chipselect = num_cs;
1467         if (of_get_property(node, "ti,pindir-d0-out-d1-in", NULL))
1468             mcspi->pin_dir = MCSPI_PINDIR_D0_OUT_D1_IN;
1469     } else {
1470         pdata = dev_get_platdata(&pdev->dev);
1471         master->num_chipselect = pdata->num_cs;
1472         mcspi->pin_dir = pdata->pin_dir;
1473     }
1474     regs_offset = pdata->regs_offset;
1475     if (pdata->max_xfer_len) {
1476         mcspi->max_xfer_len = pdata->max_xfer_len;
1477         master->max_transfer_size = omap2_mcspi_max_xfer_size;
1478     }
1479 
1480     r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1481     mcspi->base = devm_ioremap_resource(&pdev->dev, r);
1482     if (IS_ERR(mcspi->base)) {
1483         status = PTR_ERR(mcspi->base);
1484         goto free_master;
1485     }
1486     mcspi->phys = r->start + regs_offset;
1487     mcspi->base += regs_offset;
1488 
1489     mcspi->dev = &pdev->dev;
1490 
1491     INIT_LIST_HEAD(&mcspi->ctx.cs);
1492 
1493     mcspi->dma_channels = devm_kcalloc(&pdev->dev, master->num_chipselect,
1494                        sizeof(struct omap2_mcspi_dma),
1495                        GFP_KERNEL);
1496     if (mcspi->dma_channels == NULL) {
1497         status = -ENOMEM;
1498         goto free_master;
1499     }
1500 
1501     for (i = 0; i < master->num_chipselect; i++) {
1502         sprintf(mcspi->dma_channels[i].dma_rx_ch_name, "rx%d", i);
1503         sprintf(mcspi->dma_channels[i].dma_tx_ch_name, "tx%d", i);
1504 
1505         status = omap2_mcspi_request_dma(mcspi,
1506                          &mcspi->dma_channels[i]);
1507         if (status == -EPROBE_DEFER)
1508             goto free_master;
1509     }
1510 
1511     status = platform_get_irq(pdev, 0);
1512     if (status == -EPROBE_DEFER)
1513         goto free_master;
1514     if (status < 0) {
1515         dev_err(&pdev->dev, "no irq resource found\n");
1516         goto free_master;
1517     }
1518     init_completion(&mcspi->txdone);
1519     status = devm_request_irq(&pdev->dev, status,
1520                   omap2_mcspi_irq_handler, 0, pdev->name,
1521                   mcspi);
1522     if (status) {
1523         dev_err(&pdev->dev, "Cannot request IRQ");
1524         goto free_master;
1525     }
1526 
1527     pm_runtime_use_autosuspend(&pdev->dev);
1528     pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT);
1529     pm_runtime_enable(&pdev->dev);
1530 
1531     status = omap2_mcspi_controller_setup(mcspi);
1532     if (status < 0)
1533         goto disable_pm;
1534 
1535     status = devm_spi_register_controller(&pdev->dev, master);
1536     if (status < 0)
1537         goto disable_pm;
1538 
1539     return status;
1540 
1541 disable_pm:
1542     pm_runtime_dont_use_autosuspend(&pdev->dev);
1543     pm_runtime_put_sync(&pdev->dev);
1544     pm_runtime_disable(&pdev->dev);
1545 free_master:
1546     omap2_mcspi_release_dma(master);
1547     spi_master_put(master);
1548     return status;
1549 }
1550 
1551 static int omap2_mcspi_remove(struct platform_device *pdev)
1552 {
1553     struct spi_master *master = platform_get_drvdata(pdev);
1554     struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
1555 
1556     omap2_mcspi_release_dma(master);
1557 
1558     pm_runtime_dont_use_autosuspend(mcspi->dev);
1559     pm_runtime_put_sync(mcspi->dev);
1560     pm_runtime_disable(&pdev->dev);
1561 
1562     return 0;
1563 }
1564 
1565 /* work with hotplug and coldplug */
1566 MODULE_ALIAS("platform:omap2_mcspi");
1567 
1568 static int __maybe_unused omap2_mcspi_suspend(struct device *dev)
1569 {
1570     struct spi_master *master = dev_get_drvdata(dev);
1571     struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
1572     int error;
1573 
1574     error = pinctrl_pm_select_sleep_state(dev);
1575     if (error)
1576         dev_warn(mcspi->dev, "%s: failed to set pins: %i\n",
1577              __func__, error);
1578 
1579     error = spi_master_suspend(master);
1580     if (error)
1581         dev_warn(mcspi->dev, "%s: master suspend failed: %i\n",
1582              __func__, error);
1583 
1584     return pm_runtime_force_suspend(dev);
1585 }
1586 
1587 static int __maybe_unused omap2_mcspi_resume(struct device *dev)
1588 {
1589     struct spi_master *master = dev_get_drvdata(dev);
1590     struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
1591     int error;
1592 
1593     error = spi_master_resume(master);
1594     if (error)
1595         dev_warn(mcspi->dev, "%s: master resume failed: %i\n",
1596              __func__, error);
1597 
1598     return pm_runtime_force_resume(dev);
1599 }
1600 
1601 static const struct dev_pm_ops omap2_mcspi_pm_ops = {
1602     SET_SYSTEM_SLEEP_PM_OPS(omap2_mcspi_suspend,
1603                 omap2_mcspi_resume)
1604     .runtime_suspend    = omap_mcspi_runtime_suspend,
1605     .runtime_resume     = omap_mcspi_runtime_resume,
1606 };
1607 
1608 static struct platform_driver omap2_mcspi_driver = {
1609     .driver = {
1610         .name =     "omap2_mcspi",
1611         .pm =       &omap2_mcspi_pm_ops,
1612         .of_match_table = omap_mcspi_of_match,
1613     },
1614     .probe =    omap2_mcspi_probe,
1615     .remove =   omap2_mcspi_remove,
1616 };
1617 
1618 module_platform_driver(omap2_mcspi_driver);
1619 MODULE_LICENSE("GPL");
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