drivers/spi/spi-omap-uwire.c

0001 /*
0002  * MicroWire interface driver for OMAP
0003  *
0004  * Copyright 2003 MontaVista Software Inc. <source@mvista.com>
0005  *
0006  * Ported to 2.6 OMAP uwire interface.
0007  * Copyright (C) 2004 Texas Instruments.
0008  *
0009  * Generalization patches by Juha Yrjola <juha.yrjola@nokia.com>
0010  *
0011  * Copyright (C) 2005 David Brownell (ported to 2.6 SPI interface)
0012  * Copyright (C) 2006 Nokia
0013  *
0014  * Many updates by Imre Deak <imre.deak@nokia.com>
0015  *
0016  * This program is free software; you can redistribute it and/or modify it
0017  * under the terms of the GNU General Public License as published by the
0018  * Free Software Foundation; either version 2 of the License, or (at your
0019  * option) any later version.
0020  *
0021  * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
0022  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
0023  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
0024  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
0025  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
0026  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
0027  * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
0028  * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
0029  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
0030  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
0031  */
0032 #include <linux/kernel.h>
0033 #include <linux/init.h>
0034 #include <linux/delay.h>
0035 #include <linux/platform_device.h>
0036 #include <linux/interrupt.h>
0037 #include <linux/err.h>
0038 #include <linux/clk.h>
0039 #include <linux/slab.h>
0040 #include <linux/device.h>
0041
0042 #include <linux/spi/spi.h>
0043 #include <linux/spi/spi_bitbang.h>
0044 #include <linux/module.h>
0045 #include <linux/io.h>
0046
0047 #include <asm/mach-types.h>
0048 #include <linux/soc/ti/omap1-io.h>
0049 #include <linux/soc/ti/omap1-soc.h>
0050 #include <linux/soc/ti/omap1-mux.h>
0051
0052 /* FIXME address is now a platform device resource,
0053  * and irqs should show there too...
0054  */
0055 #define UWIRE_BASE_PHYS     0xFFFB3000
0056
0057 /* uWire Registers: */
0058 #define UWIRE_IO_SIZE 0x20
0059 #define UWIRE_TDR     0x00
0060 #define UWIRE_RDR     0x00
0061 #define UWIRE_CSR     0x01
0062 #define UWIRE_SR1     0x02
0063 #define UWIRE_SR2     0x03
0064 #define UWIRE_SR3     0x04
0065 #define UWIRE_SR4     0x05
0066 #define UWIRE_SR5     0x06
0067
0068 /* CSR bits */
0069 #define RDRB    (1 << 15)
0070 #define CSRB    (1 << 14)
0071 #define START   (1 << 13)
0072 #define CS_CMD  (1 << 12)
0073
0074 /* SR1 or SR2 bits */
0075 #define UWIRE_READ_FALLING_EDGE     0x0001
0076 #define UWIRE_READ_RISING_EDGE      0x0000
0077 #define UWIRE_WRITE_FALLING_EDGE    0x0000
0078 #define UWIRE_WRITE_RISING_EDGE     0x0002
0079 #define UWIRE_CS_ACTIVE_LOW     0x0000
0080 #define UWIRE_CS_ACTIVE_HIGH        0x0004
0081 #define UWIRE_FREQ_DIV_2        0x0000
0082 #define UWIRE_FREQ_DIV_4        0x0008
0083 #define UWIRE_FREQ_DIV_8        0x0010
0084 #define UWIRE_CHK_READY         0x0020
0085 #define UWIRE_CLK_INVERTED      0x0040
0086
0087
0088 struct uwire_spi {
0089     struct spi_bitbang  bitbang;
0090     struct clk      *ck;
0091 };
0092
0093 struct uwire_state {
0094     unsigned    div1_idx;
0095 };
0096
0097 /* REVISIT compile time constant for idx_shift? */
0098 /*
0099  * Or, put it in a structure which is used throughout the driver;
0100  * that avoids having to issue two loads for each bit of static data.
0101  */
0102 static unsigned int uwire_idx_shift;
0103 static void __iomem *uwire_base;
0104
0105 static inline void uwire_write_reg(int idx, u16 val)
0106 {
0107     __raw_writew(val, uwire_base + (idx << uwire_idx_shift));
0108 }
0109
0110 static inline u16 uwire_read_reg(int idx)
0111 {
0112     return __raw_readw(uwire_base + (idx << uwire_idx_shift));
0113 }
0114
0115 static inline void omap_uwire_configure_mode(u8 cs, unsigned long flags)
0116 {
0117     u16 w, val = 0;
0118     int shift, reg;
0119
0120     if (flags & UWIRE_CLK_INVERTED)
0121         val ^= 0x03;
0122     val = flags & 0x3f;
0123     if (cs & 1)
0124         shift = 6;
0125     else
0126         shift = 0;
0127     if (cs <= 1)
0128         reg = UWIRE_SR1;
0129     else
0130         reg = UWIRE_SR2;
0131
0132     w = uwire_read_reg(reg);
0133     w &= ~(0x3f << shift);
0134     w |= val << shift;
0135     uwire_write_reg(reg, w);
0136 }
0137
0138 static int wait_uwire_csr_flag(u16 mask, u16 val, int might_not_catch)
0139 {
0140     u16 w;
0141     int c = 0;
0142     unsigned long max_jiffies = jiffies + HZ;
0143
0144     for (;;) {
0145         w = uwire_read_reg(UWIRE_CSR);
0146         if ((w & mask) == val)
0147             break;
0148         if (time_after(jiffies, max_jiffies)) {
0149             printk(KERN_ERR "%s: timeout. reg=%#06x "
0150                     "mask=%#06x val=%#06x\n",
0151                    __func__, w, mask, val);
0152             return -1;
0153         }
0154         c++;
0155         if (might_not_catch && c > 64)
0156             break;
0157     }
0158     return 0;
0159 }
0160
0161 static void uwire_set_clk1_div(int div1_idx)
0162 {
0163     u16 w;
0164
0165     w = uwire_read_reg(UWIRE_SR3);
0166     w &= ~(0x03 << 1);
0167     w |= div1_idx << 1;
0168     uwire_write_reg(UWIRE_SR3, w);
0169 }
0170
0171 static void uwire_chipselect(struct spi_device *spi, int value)
0172 {
0173     struct  uwire_state *ust = spi->controller_state;
0174     u16 w;
0175     int old_cs;
0176
0177
0178     BUG_ON(wait_uwire_csr_flag(CSRB, 0, 0));
0179
0180     w = uwire_read_reg(UWIRE_CSR);
0181     old_cs = (w >> 10) & 0x03;
0182     if (value == BITBANG_CS_INACTIVE || old_cs != spi->chip_select) {
0183         /* Deselect this CS, or the previous CS */
0184         w &= ~CS_CMD;
0185         uwire_write_reg(UWIRE_CSR, w);
0186     }
0187     /* activate specfied chipselect */
0188     if (value == BITBANG_CS_ACTIVE) {
0189         uwire_set_clk1_div(ust->div1_idx);
0190         /* invert clock? */
0191         if (spi->mode & SPI_CPOL)
0192             uwire_write_reg(UWIRE_SR4, 1);
0193         else
0194             uwire_write_reg(UWIRE_SR4, 0);
0195
0196         w = spi->chip_select << 10;
0197         w |= CS_CMD;
0198         uwire_write_reg(UWIRE_CSR, w);
0199     }
0200 }
0201
0202 static int uwire_txrx(struct spi_device *spi, struct spi_transfer *t)
0203 {
0204     unsigned    len = t->len;
0205     unsigned    bits = t->bits_per_word;
0206     unsigned    bytes;
0207     u16     val, w;
0208     int     status = 0;
0209
0210     if (!t->tx_buf && !t->rx_buf)
0211         return 0;
0212
0213     w = spi->chip_select << 10;
0214     w |= CS_CMD;
0215
0216     if (t->tx_buf) {
0217         const u8    *buf = t->tx_buf;
0218
0219         /* NOTE:  DMA could be used for TX transfers */
0220
0221         /* write one or two bytes at a time */
0222         while (len >= 1) {
0223             /* tx bit 15 is first sent; we byteswap multibyte words
0224              * (msb-first) on the way out from memory.
0225              */
0226             val = *buf++;
0227             if (bits > 8) {
0228                 bytes = 2;
0229                 val |= *buf++ << 8;
0230             } else
0231                 bytes = 1;
0232             val <<= 16 - bits;
0233
0234 #ifdef  VERBOSE
0235             pr_debug("%s: write-%d =%04x\n",
0236                     dev_name(&spi->dev), bits, val);
0237 #endif
0238             if (wait_uwire_csr_flag(CSRB, 0, 0))
0239                 goto eio;
0240
0241             uwire_write_reg(UWIRE_TDR, val);
0242
0243             /* start write */
0244             val = START | w | (bits << 5);
0245
0246             uwire_write_reg(UWIRE_CSR, val);
0247             len -= bytes;
0248
0249             /* Wait till write actually starts.
0250              * This is needed with MPU clock 60+ MHz.
0251              * REVISIT: we may not have time to catch it...
0252              */
0253             if (wait_uwire_csr_flag(CSRB, CSRB, 1))
0254                 goto eio;
0255
0256             status += bytes;
0257         }
0258
0259         /* REVISIT:  save this for later to get more i/o overlap */
0260         if (wait_uwire_csr_flag(CSRB, 0, 0))
0261             goto eio;
0262
0263     } else if (t->rx_buf) {
0264         u8      *buf = t->rx_buf;
0265
0266         /* read one or two bytes at a time */
0267         while (len) {
0268             if (bits > 8) {
0269                 bytes = 2;
0270             } else
0271                 bytes = 1;
0272
0273             /* start read */
0274             val = START | w | (bits << 0);
0275             uwire_write_reg(UWIRE_CSR, val);
0276             len -= bytes;
0277
0278             /* Wait till read actually starts */
0279             (void) wait_uwire_csr_flag(CSRB, CSRB, 1);
0280
0281             if (wait_uwire_csr_flag(RDRB | CSRB,
0282                         RDRB, 0))
0283                 goto eio;
0284
0285             /* rx bit 0 is last received; multibyte words will
0286              * be properly byteswapped on the way to memory.
0287              */
0288             val = uwire_read_reg(UWIRE_RDR);
0289             val &= (1 << bits) - 1;
0290             *buf++ = (u8) val;
0291             if (bytes == 2)
0292                 *buf++ = val >> 8;
0293             status += bytes;
0294 #ifdef  VERBOSE
0295             pr_debug("%s: read-%d =%04x\n",
0296                     dev_name(&spi->dev), bits, val);
0297 #endif
0298
0299         }
0300     }
0301     return status;
0302 eio:
0303     return -EIO;
0304 }
0305
0306 static int uwire_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
0307 {
0308     struct uwire_state  *ust = spi->controller_state;
0309     struct uwire_spi    *uwire;
0310     unsigned        flags = 0;
0311     unsigned        hz;
0312     unsigned long       rate;
0313     int         div1_idx;
0314     int         div1;
0315     int         div2;
0316     int         status;
0317
0318     uwire = spi_master_get_devdata(spi->master);
0319
0320     /* mode 0..3, clock inverted separately;
0321      * standard nCS signaling;
0322      * don't treat DI=high as "not ready"
0323      */
0324     if (spi->mode & SPI_CS_HIGH)
0325         flags |= UWIRE_CS_ACTIVE_HIGH;
0326
0327     if (spi->mode & SPI_CPOL)
0328         flags |= UWIRE_CLK_INVERTED;
0329
0330     switch (spi->mode & SPI_MODE_X_MASK) {
0331     case SPI_MODE_0:
0332     case SPI_MODE_3:
0333         flags |= UWIRE_WRITE_FALLING_EDGE | UWIRE_READ_RISING_EDGE;
0334         break;
0335     case SPI_MODE_1:
0336     case SPI_MODE_2:
0337         flags |= UWIRE_WRITE_RISING_EDGE | UWIRE_READ_FALLING_EDGE;
0338         break;
0339     }
0340
0341     /* assume it's already enabled */
0342     rate = clk_get_rate(uwire->ck);
0343
0344     if (t != NULL)
0345         hz = t->speed_hz;
0346     else
0347         hz = spi->max_speed_hz;
0348
0349     if (!hz) {
0350         pr_debug("%s: zero speed?\n", dev_name(&spi->dev));
0351         status = -EINVAL;
0352         goto done;
0353     }
0354
0355     /* F_INT = mpu_xor_clk / DIV1 */
0356     for (div1_idx = 0; div1_idx < 4; div1_idx++) {
0357         switch (div1_idx) {
0358         case 0:
0359             div1 = 2;
0360             break;
0361         case 1:
0362             div1 = 4;
0363             break;
0364         case 2:
0365             div1 = 7;
0366             break;
0367         default:
0368         case 3:
0369             div1 = 10;
0370             break;
0371         }
0372         div2 = (rate / div1 + hz - 1) / hz;
0373         if (div2 <= 8)
0374             break;
0375     }
0376     if (div1_idx == 4) {
0377         pr_debug("%s: lowest clock %ld, need %d\n",
0378             dev_name(&spi->dev), rate / 10 / 8, hz);
0379         status = -EDOM;
0380         goto done;
0381     }
0382
0383     /* we have to cache this and reset in uwire_chipselect as this is a
0384      * global parameter and another uwire device can change it under
0385      * us */
0386     ust->div1_idx = div1_idx;
0387     uwire_set_clk1_div(div1_idx);
0388
0389     rate /= div1;
0390
0391     switch (div2) {
0392     case 0:
0393     case 1:
0394     case 2:
0395         flags |= UWIRE_FREQ_DIV_2;
0396         rate /= 2;
0397         break;
0398     case 3:
0399     case 4:
0400         flags |= UWIRE_FREQ_DIV_4;
0401         rate /= 4;
0402         break;
0403     case 5:
0404     case 6:
0405     case 7:
0406     case 8:
0407         flags |= UWIRE_FREQ_DIV_8;
0408         rate /= 8;
0409         break;
0410     }
0411     omap_uwire_configure_mode(spi->chip_select, flags);
0412     pr_debug("%s: uwire flags %02x, armxor %lu KHz, SCK %lu KHz\n",
0413             __func__, flags,
0414             clk_get_rate(uwire->ck) / 1000,
0415             rate / 1000);
0416     status = 0;
0417 done:
0418     return status;
0419 }
0420
0421 static int uwire_setup(struct spi_device *spi)
0422 {
0423     struct uwire_state *ust = spi->controller_state;
0424     bool initial_setup = false;
0425     int status;
0426
0427     if (ust == NULL) {
0428         ust = kzalloc(sizeof(*ust), GFP_KERNEL);
0429         if (ust == NULL)
0430             return -ENOMEM;
0431         spi->controller_state = ust;
0432         initial_setup = true;
0433     }
0434
0435     status = uwire_setup_transfer(spi, NULL);
0436     if (status && initial_setup)
0437         kfree(ust);
0438
0439     return status;
0440 }
0441
0442 static void uwire_cleanup(struct spi_device *spi)
0443 {
0444     kfree(spi->controller_state);
0445 }
0446
0447 static void uwire_off(struct uwire_spi *uwire)
0448 {
0449     uwire_write_reg(UWIRE_SR3, 0);
0450     clk_disable_unprepare(uwire->ck);
0451     spi_master_put(uwire->bitbang.master);
0452 }
0453
0454 static int uwire_probe(struct platform_device *pdev)
0455 {
0456     struct spi_master   *master;
0457     struct uwire_spi    *uwire;
0458     int         status;
0459
0460     master = spi_alloc_master(&pdev->dev, sizeof(*uwire));
0461     if (!master)
0462         return -ENODEV;
0463
0464     uwire = spi_master_get_devdata(master);
0465
0466     uwire_base = devm_ioremap(&pdev->dev, UWIRE_BASE_PHYS, UWIRE_IO_SIZE);
0467     if (!uwire_base) {
0468         dev_dbg(&pdev->dev, "can't ioremap UWIRE\n");
0469         spi_master_put(master);
0470         return -ENOMEM;
0471     }
0472
0473     platform_set_drvdata(pdev, uwire);
0474
0475     uwire->ck = devm_clk_get(&pdev->dev, "fck");
0476     if (IS_ERR(uwire->ck)) {
0477         status = PTR_ERR(uwire->ck);
0478         dev_dbg(&pdev->dev, "no functional clock?\n");
0479         spi_master_put(master);
0480         return status;
0481     }
0482     clk_prepare_enable(uwire->ck);
0483
0484     if (cpu_is_omap7xx())
0485         uwire_idx_shift = 1;
0486     else
0487         uwire_idx_shift = 2;
0488
0489     uwire_write_reg(UWIRE_SR3, 1);
0490
0491     /* the spi->mode bits understood by this driver: */
0492     master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
0493     master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 16);
0494     master->flags = SPI_MASTER_HALF_DUPLEX;
0495
0496     master->bus_num = 2;    /* "official" */
0497     master->num_chipselect = 4;
0498     master->setup = uwire_setup;
0499     master->cleanup = uwire_cleanup;
0500
0501     uwire->bitbang.master = master;
0502     uwire->bitbang.chipselect = uwire_chipselect;
0503     uwire->bitbang.setup_transfer = uwire_setup_transfer;
0504     uwire->bitbang.txrx_bufs = uwire_txrx;
0505
0506     status = spi_bitbang_start(&uwire->bitbang);
0507     if (status < 0) {
0508         uwire_off(uwire);
0509     }
0510     return status;
0511 }
0512
0513 static int uwire_remove(struct platform_device *pdev)
0514 {
0515     struct uwire_spi    *uwire = platform_get_drvdata(pdev);
0516
0517     // FIXME remove all child devices, somewhere ...
0518
0519     spi_bitbang_stop(&uwire->bitbang);
0520     uwire_off(uwire);
0521     return 0;
0522 }
0523
0524 /* work with hotplug and coldplug */
0525 MODULE_ALIAS("platform:omap_uwire");
0526
0527 static struct platform_driver uwire_driver = {
0528     .driver = {
0529         .name       = "omap_uwire",
0530     },
0531     .probe = uwire_probe,
0532     .remove = uwire_remove,
0533     // suspend ... unuse ck
0534     // resume ... use ck
0535 };
0536
0537 static int __init omap_uwire_init(void)
0538 {
0539     /* FIXME move these into the relevant board init code. also, include
0540      * H3 support; it uses tsc2101 like H2 (on a different chipselect).
0541      */
0542
0543     if (machine_is_omap_h2()) {
0544         /* defaults: W21 SDO, U18 SDI, V19 SCL */
0545         omap_cfg_reg(N14_1610_UWIRE_CS0);
0546         omap_cfg_reg(N15_1610_UWIRE_CS1);
0547     }
0548     return platform_driver_register(&uwire_driver);
0549 }
0550
0551 static void __exit omap_uwire_exit(void)
0552 {
0553     platform_driver_unregister(&uwire_driver);
0554 }
0555
0556 subsys_initcall(omap_uwire_init);
0557 module_exit(omap_uwire_exit);
0558
0559 MODULE_LICENSE("GPL");
0560