drivers/spi/spi-omap-100k.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * OMAP7xx SPI 100k controller driver
0004  * Author: Fabrice Crohas <fcrohas@gmail.com>
0005  * from original omap1_mcspi driver
0006  *
0007  * Copyright (C) 2005, 2006 Nokia Corporation
0008  * Author:      Samuel Ortiz <samuel.ortiz@nokia.com> and
0009  *              Juha Yrjola <juha.yrjola@nokia.com>
0010  */
0011 #include <linux/kernel.h>
0012 #include <linux/init.h>
0013 #include <linux/interrupt.h>
0014 #include <linux/module.h>
0015 #include <linux/device.h>
0016 #include <linux/delay.h>
0017 #include <linux/platform_device.h>
0018 #include <linux/pm_runtime.h>
0019 #include <linux/err.h>
0020 #include <linux/clk.h>
0021 #include <linux/io.h>
0022 #include <linux/slab.h>
0023
0024 #include <linux/spi/spi.h>
0025
0026 #define OMAP1_SPI100K_MAX_FREQ          48000000
0027
0028 #define ICR_SPITAS      (OMAP7XX_ICR_BASE + 0x12)
0029
0030 #define SPI_SETUP1      0x00
0031 #define SPI_SETUP2      0x02
0032 #define SPI_CTRL        0x04
0033 #define SPI_STATUS      0x06
0034 #define SPI_TX_LSB      0x08
0035 #define SPI_TX_MSB      0x0a
0036 #define SPI_RX_LSB      0x0c
0037 #define SPI_RX_MSB      0x0e
0038
0039 #define SPI_SETUP1_INT_READ_ENABLE      (1UL << 5)
0040 #define SPI_SETUP1_INT_WRITE_ENABLE     (1UL << 4)
0041 #define SPI_SETUP1_CLOCK_DIVISOR(x)     ((x) << 1)
0042 #define SPI_SETUP1_CLOCK_ENABLE         (1UL << 0)
0043
0044 #define SPI_SETUP2_ACTIVE_EDGE_FALLING  (0UL << 0)
0045 #define SPI_SETUP2_ACTIVE_EDGE_RISING   (1UL << 0)
0046 #define SPI_SETUP2_NEGATIVE_LEVEL       (0UL << 5)
0047 #define SPI_SETUP2_POSITIVE_LEVEL       (1UL << 5)
0048 #define SPI_SETUP2_LEVEL_TRIGGER        (0UL << 10)
0049 #define SPI_SETUP2_EDGE_TRIGGER         (1UL << 10)
0050
0051 #define SPI_CTRL_SEN(x)                 ((x) << 7)
0052 #define SPI_CTRL_WORD_SIZE(x)           (((x) - 1) << 2)
0053 #define SPI_CTRL_WR                     (1UL << 1)
0054 #define SPI_CTRL_RD                     (1UL << 0)
0055
0056 #define SPI_STATUS_WE                   (1UL << 1)
0057 #define SPI_STATUS_RD                   (1UL << 0)
0058
0059 /* use PIO for small transfers, avoiding DMA setup/teardown overhead and
0060  * cache operations; better heuristics consider wordsize and bitrate.
0061  */
0062 #define DMA_MIN_BYTES                   8
0063
0064 #define SPI_RUNNING 0
0065 #define SPI_SHUTDOWN    1
0066
0067 struct omap1_spi100k {
0068     struct clk              *ick;
0069     struct clk              *fck;
0070
0071     /* Virtual base address of the controller */
0072     void __iomem            *base;
0073 };
0074
0075 struct omap1_spi100k_cs {
0076     void __iomem            *base;
0077     int                     word_len;
0078 };
0079
0080 static void spi100k_enable_clock(struct spi_master *master)
0081 {
0082     unsigned int val;
0083     struct omap1_spi100k *spi100k = spi_master_get_devdata(master);
0084
0085     /* enable SPI */
0086     val = readw(spi100k->base + SPI_SETUP1);
0087     val |= SPI_SETUP1_CLOCK_ENABLE;
0088     writew(val, spi100k->base + SPI_SETUP1);
0089 }
0090
0091 static void spi100k_disable_clock(struct spi_master *master)
0092 {
0093     unsigned int val;
0094     struct omap1_spi100k *spi100k = spi_master_get_devdata(master);
0095
0096     /* disable SPI */
0097     val = readw(spi100k->base + SPI_SETUP1);
0098     val &= ~SPI_SETUP1_CLOCK_ENABLE;
0099     writew(val, spi100k->base + SPI_SETUP1);
0100 }
0101
0102 static void spi100k_write_data(struct spi_master *master, int len, int data)
0103 {
0104     struct omap1_spi100k *spi100k = spi_master_get_devdata(master);
0105
0106     /* write 16-bit word, shifting 8-bit data if necessary */
0107     if (len <= 8) {
0108         data <<= 8;
0109         len = 16;
0110     }
0111
0112     spi100k_enable_clock(master);
0113     writew(data, spi100k->base + SPI_TX_MSB);
0114
0115     writew(SPI_CTRL_SEN(0) |
0116            SPI_CTRL_WORD_SIZE(len) |
0117            SPI_CTRL_WR,
0118            spi100k->base + SPI_CTRL);
0119
0120     /* Wait for bit ack send change */
0121     while ((readw(spi100k->base + SPI_STATUS) & SPI_STATUS_WE) != SPI_STATUS_WE)
0122         ;
0123     udelay(1000);
0124
0125     spi100k_disable_clock(master);
0126 }
0127
0128 static int spi100k_read_data(struct spi_master *master, int len)
0129 {
0130     int dataL;
0131     struct omap1_spi100k *spi100k = spi_master_get_devdata(master);
0132
0133     /* Always do at least 16 bits */
0134     if (len <= 8)
0135         len = 16;
0136
0137     spi100k_enable_clock(master);
0138     writew(SPI_CTRL_SEN(0) |
0139            SPI_CTRL_WORD_SIZE(len) |
0140            SPI_CTRL_RD,
0141            spi100k->base + SPI_CTRL);
0142
0143     while ((readw(spi100k->base + SPI_STATUS) & SPI_STATUS_RD) != SPI_STATUS_RD)
0144         ;
0145     udelay(1000);
0146
0147     dataL = readw(spi100k->base + SPI_RX_LSB);
0148     readw(spi100k->base + SPI_RX_MSB);
0149     spi100k_disable_clock(master);
0150
0151     return dataL;
0152 }
0153
0154 static void spi100k_open(struct spi_master *master)
0155 {
0156     /* get control of SPI */
0157     struct omap1_spi100k *spi100k = spi_master_get_devdata(master);
0158
0159     writew(SPI_SETUP1_INT_READ_ENABLE |
0160            SPI_SETUP1_INT_WRITE_ENABLE |
0161            SPI_SETUP1_CLOCK_DIVISOR(0), spi100k->base + SPI_SETUP1);
0162
0163     /* configure clock and interrupts */
0164     writew(SPI_SETUP2_ACTIVE_EDGE_FALLING |
0165            SPI_SETUP2_NEGATIVE_LEVEL |
0166            SPI_SETUP2_LEVEL_TRIGGER, spi100k->base + SPI_SETUP2);
0167 }
0168
0169 static void omap1_spi100k_force_cs(struct omap1_spi100k *spi100k, int enable)
0170 {
0171     if (enable)
0172         writew(0x05fc, spi100k->base + SPI_CTRL);
0173     else
0174         writew(0x05fd, spi100k->base + SPI_CTRL);
0175 }
0176
0177 static unsigned
0178 omap1_spi100k_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
0179 {
0180     struct omap1_spi100k_cs *cs = spi->controller_state;
0181     unsigned int            count, c;
0182     int                     word_len;
0183
0184     count = xfer->len;
0185     c = count;
0186     word_len = cs->word_len;
0187
0188     if (word_len <= 8) {
0189         u8              *rx;
0190         const u8        *tx;
0191
0192         rx = xfer->rx_buf;
0193         tx = xfer->tx_buf;
0194         do {
0195             c -= 1;
0196             if (xfer->tx_buf != NULL)
0197                 spi100k_write_data(spi->master, word_len, *tx++);
0198             if (xfer->rx_buf != NULL)
0199                 *rx++ = spi100k_read_data(spi->master, word_len);
0200         } while (c);
0201     } else if (word_len <= 16) {
0202         u16             *rx;
0203         const u16       *tx;
0204
0205         rx = xfer->rx_buf;
0206         tx = xfer->tx_buf;
0207         do {
0208             c -= 2;
0209             if (xfer->tx_buf != NULL)
0210                 spi100k_write_data(spi->master, word_len, *tx++);
0211             if (xfer->rx_buf != NULL)
0212                 *rx++ = spi100k_read_data(spi->master, word_len);
0213         } while (c);
0214     } else if (word_len <= 32) {
0215         u32             *rx;
0216         const u32       *tx;
0217
0218         rx = xfer->rx_buf;
0219         tx = xfer->tx_buf;
0220         do {
0221             c -= 4;
0222             if (xfer->tx_buf != NULL)
0223                 spi100k_write_data(spi->master, word_len, *tx);
0224             if (xfer->rx_buf != NULL)
0225                 *rx = spi100k_read_data(spi->master, word_len);
0226         } while (c);
0227     }
0228     return count - c;
0229 }
0230
0231 /* called only when no transfer is active to this device */
0232 static int omap1_spi100k_setup_transfer(struct spi_device *spi,
0233         struct spi_transfer *t)
0234 {
0235     struct omap1_spi100k *spi100k = spi_master_get_devdata(spi->master);
0236     struct omap1_spi100k_cs *cs = spi->controller_state;
0237     u8 word_len;
0238
0239     if (t != NULL)
0240         word_len = t->bits_per_word;
0241     else
0242         word_len = spi->bits_per_word;
0243
0244     if (word_len > 32)
0245         return -EINVAL;
0246     cs->word_len = word_len;
0247
0248     /* SPI init before transfer */
0249     writew(0x3e, spi100k->base + SPI_SETUP1);
0250     writew(0x00, spi100k->base + SPI_STATUS);
0251     writew(0x3e, spi100k->base + SPI_CTRL);
0252
0253     return 0;
0254 }
0255
0256 /* the spi->mode bits understood by this driver: */
0257 #define MODEBITS (SPI_CPOL | SPI_CPHA | SPI_CS_HIGH)
0258
0259 static int omap1_spi100k_setup(struct spi_device *spi)
0260 {
0261     int                     ret;
0262     struct omap1_spi100k    *spi100k;
0263     struct omap1_spi100k_cs *cs = spi->controller_state;
0264
0265     spi100k = spi_master_get_devdata(spi->master);
0266
0267     if (!cs) {
0268         cs = devm_kzalloc(&spi->dev, sizeof(*cs), GFP_KERNEL);
0269         if (!cs)
0270             return -ENOMEM;
0271         cs->base = spi100k->base + spi->chip_select * 0x14;
0272         spi->controller_state = cs;
0273     }
0274
0275     spi100k_open(spi->master);
0276
0277     clk_prepare_enable(spi100k->ick);
0278     clk_prepare_enable(spi100k->fck);
0279
0280     ret = omap1_spi100k_setup_transfer(spi, NULL);
0281
0282     clk_disable_unprepare(spi100k->ick);
0283     clk_disable_unprepare(spi100k->fck);
0284
0285     return ret;
0286 }
0287
0288 static int omap1_spi100k_transfer_one_message(struct spi_master *master,
0289                           struct spi_message *m)
0290 {
0291     struct omap1_spi100k *spi100k = spi_master_get_devdata(master);
0292     struct spi_device *spi = m->spi;
0293     struct spi_transfer *t = NULL;
0294     int cs_active = 0;
0295     int status = 0;
0296
0297     list_for_each_entry(t, &m->transfers, transfer_list) {
0298         if (t->tx_buf == NULL && t->rx_buf == NULL && t->len) {
0299             break;
0300         }
0301         status = omap1_spi100k_setup_transfer(spi, t);
0302         if (status < 0)
0303             break;
0304
0305         if (!cs_active) {
0306             omap1_spi100k_force_cs(spi100k, 1);
0307             cs_active = 1;
0308         }
0309
0310         if (t->len) {
0311             unsigned count;
0312
0313             count = omap1_spi100k_txrx_pio(spi, t);
0314             m->actual_length += count;
0315
0316             if (count != t->len) {
0317                 break;
0318             }
0319         }
0320
0321         spi_transfer_delay_exec(t);
0322
0323         /* ignore the "leave it on after last xfer" hint */
0324
0325         if (t->cs_change) {
0326             omap1_spi100k_force_cs(spi100k, 0);
0327             cs_active = 0;
0328         }
0329     }
0330
0331     status = omap1_spi100k_setup_transfer(spi, NULL);
0332
0333     if (cs_active)
0334         omap1_spi100k_force_cs(spi100k, 0);
0335
0336     m->status = status;
0337
0338     spi_finalize_current_message(master);
0339
0340     return status;
0341 }
0342
0343 static int omap1_spi100k_probe(struct platform_device *pdev)
0344 {
0345     struct spi_master       *master;
0346     struct omap1_spi100k    *spi100k;
0347     int                     status = 0;
0348
0349     if (!pdev->id)
0350         return -EINVAL;
0351
0352     master = spi_alloc_master(&pdev->dev, sizeof(*spi100k));
0353     if (master == NULL) {
0354         dev_dbg(&pdev->dev, "master allocation failed\n");
0355         return -ENOMEM;
0356     }
0357
0358     if (pdev->id != -1)
0359         master->bus_num = pdev->id;
0360
0361     master->setup = omap1_spi100k_setup;
0362     master->transfer_one_message = omap1_spi100k_transfer_one_message;
0363     master->num_chipselect = 2;
0364     master->mode_bits = MODEBITS;
0365     master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
0366     master->min_speed_hz = OMAP1_SPI100K_MAX_FREQ/(1<<16);
0367     master->max_speed_hz = OMAP1_SPI100K_MAX_FREQ;
0368     master->auto_runtime_pm = true;
0369
0370     spi100k = spi_master_get_devdata(master);
0371
0372     /*
0373      * The memory region base address is taken as the platform_data.
0374      * You should allocate this with ioremap() before initializing
0375      * the SPI.
0376      */
0377     spi100k->base = (void __iomem *)dev_get_platdata(&pdev->dev);
0378
0379     spi100k->ick = devm_clk_get(&pdev->dev, "ick");
0380     if (IS_ERR(spi100k->ick)) {
0381         dev_dbg(&pdev->dev, "can't get spi100k_ick\n");
0382         status = PTR_ERR(spi100k->ick);
0383         goto err;
0384     }
0385
0386     spi100k->fck = devm_clk_get(&pdev->dev, "fck");
0387     if (IS_ERR(spi100k->fck)) {
0388         dev_dbg(&pdev->dev, "can't get spi100k_fck\n");
0389         status = PTR_ERR(spi100k->fck);
0390         goto err;
0391     }
0392
0393     status = clk_prepare_enable(spi100k->ick);
0394     if (status != 0) {
0395         dev_err(&pdev->dev, "failed to enable ick: %d\n", status);
0396         goto err;
0397     }
0398
0399     status = clk_prepare_enable(spi100k->fck);
0400     if (status != 0) {
0401         dev_err(&pdev->dev, "failed to enable fck: %d\n", status);
0402         goto err_ick;
0403     }
0404
0405     pm_runtime_enable(&pdev->dev);
0406     pm_runtime_set_active(&pdev->dev);
0407
0408     status = devm_spi_register_master(&pdev->dev, master);
0409     if (status < 0)
0410         goto err_fck;
0411
0412     return status;
0413
0414 err_fck:
0415     clk_disable_unprepare(spi100k->fck);
0416 err_ick:
0417     clk_disable_unprepare(spi100k->ick);
0418 err:
0419     spi_master_put(master);
0420     return status;
0421 }
0422
0423 static int omap1_spi100k_remove(struct platform_device *pdev)
0424 {
0425     struct spi_master *master = platform_get_drvdata(pdev);
0426     struct omap1_spi100k *spi100k = spi_master_get_devdata(master);
0427
0428     pm_runtime_disable(&pdev->dev);
0429
0430     clk_disable_unprepare(spi100k->fck);
0431     clk_disable_unprepare(spi100k->ick);
0432
0433     return 0;
0434 }
0435
0436 #ifdef CONFIG_PM
0437 static int omap1_spi100k_runtime_suspend(struct device *dev)
0438 {
0439     struct spi_master *master = dev_get_drvdata(dev);
0440     struct omap1_spi100k *spi100k = spi_master_get_devdata(master);
0441
0442     clk_disable_unprepare(spi100k->ick);
0443     clk_disable_unprepare(spi100k->fck);
0444
0445     return 0;
0446 }
0447
0448 static int omap1_spi100k_runtime_resume(struct device *dev)
0449 {
0450     struct spi_master *master = dev_get_drvdata(dev);
0451     struct omap1_spi100k *spi100k = spi_master_get_devdata(master);
0452     int ret;
0453
0454     ret = clk_prepare_enable(spi100k->ick);
0455     if (ret != 0) {
0456         dev_err(dev, "Failed to enable ick: %d\n", ret);
0457         return ret;
0458     }
0459
0460     ret = clk_prepare_enable(spi100k->fck);
0461     if (ret != 0) {
0462         dev_err(dev, "Failed to enable fck: %d\n", ret);
0463         clk_disable_unprepare(spi100k->ick);
0464         return ret;
0465     }
0466
0467     return 0;
0468 }
0469 #endif
0470
0471 static const struct dev_pm_ops omap1_spi100k_pm = {
0472     SET_RUNTIME_PM_OPS(omap1_spi100k_runtime_suspend,
0473                omap1_spi100k_runtime_resume, NULL)
0474 };
0475
0476 static struct platform_driver omap1_spi100k_driver = {
0477     .driver = {
0478         .name       = "omap1_spi100k",
0479         .pm     = &omap1_spi100k_pm,
0480     },
0481     .probe      = omap1_spi100k_probe,
0482     .remove     = omap1_spi100k_remove,
0483 };
0484
0485 module_platform_driver(omap1_spi100k_driver);
0486
0487 MODULE_DESCRIPTION("OMAP7xx SPI 100k controller driver");
0488 MODULE_AUTHOR("Fabrice Crohas <fcrohas@gmail.com>");
0489 MODULE_LICENSE("GPL");