drivers/spi/spi-npcm-pspi.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 // Copyright (c) 2018 Nuvoton Technology corporation.
0003
0004 #include <linux/kernel.h>
0005 #include <linux/bitfield.h>
0006 #include <linux/bitops.h>
0007 #include <linux/clk.h>
0008 #include <linux/interrupt.h>
0009 #include <linux/io.h>
0010 #include <linux/module.h>
0011 #include <linux/platform_device.h>
0012 #include <linux/spi/spi.h>
0013 #include <linux/reset.h>
0014
0015 #include <asm/unaligned.h>
0016
0017 #include <linux/regmap.h>
0018 #include <linux/mfd/syscon.h>
0019
0020 struct npcm_pspi {
0021     struct completion xfer_done;
0022     struct reset_control *reset;
0023     struct spi_master *master;
0024     unsigned int tx_bytes;
0025     unsigned int rx_bytes;
0026     void __iomem *base;
0027     bool is_save_param;
0028     u8 bits_per_word;
0029     const u8 *tx_buf;
0030     struct clk *clk;
0031     u32 speed_hz;
0032     u8 *rx_buf;
0033     u16 mode;
0034     u32 id;
0035 };
0036
0037 #define DRIVER_NAME "npcm-pspi"
0038
0039 #define NPCM_PSPI_DATA      0x00
0040 #define NPCM_PSPI_CTL1      0x02
0041 #define NPCM_PSPI_STAT      0x04
0042
0043 /* definitions for control and status register */
0044 #define NPCM_PSPI_CTL1_SPIEN    BIT(0)
0045 #define NPCM_PSPI_CTL1_MOD  BIT(2)
0046 #define NPCM_PSPI_CTL1_EIR  BIT(5)
0047 #define NPCM_PSPI_CTL1_EIW  BIT(6)
0048 #define NPCM_PSPI_CTL1_SCM  BIT(7)
0049 #define NPCM_PSPI_CTL1_SCIDL    BIT(8)
0050 #define NPCM_PSPI_CTL1_SCDV6_0  GENMASK(15, 9)
0051
0052 #define NPCM_PSPI_STAT_BSY  BIT(0)
0053 #define NPCM_PSPI_STAT_RBF  BIT(1)
0054
0055 /* general definitions */
0056 #define NPCM_PSPI_TIMEOUT_MS        2000
0057 #define NPCM_PSPI_MAX_CLK_DIVIDER   256
0058 #define NPCM_PSPI_MIN_CLK_DIVIDER   4
0059 #define NPCM_PSPI_DEFAULT_CLK       25000000
0060
0061 static inline unsigned int bytes_per_word(unsigned int bits)
0062 {
0063     return bits <= 8 ? 1 : 2;
0064 }
0065
0066 static inline void npcm_pspi_irq_enable(struct npcm_pspi *priv, u16 mask)
0067 {
0068     u16 val;
0069
0070     val = ioread16(priv->base + NPCM_PSPI_CTL1);
0071     val |= mask;
0072     iowrite16(val, priv->base + NPCM_PSPI_CTL1);
0073 }
0074
0075 static inline void npcm_pspi_irq_disable(struct npcm_pspi *priv, u16 mask)
0076 {
0077     u16 val;
0078
0079     val = ioread16(priv->base + NPCM_PSPI_CTL1);
0080     val &= ~mask;
0081     iowrite16(val, priv->base + NPCM_PSPI_CTL1);
0082 }
0083
0084 static inline void npcm_pspi_enable(struct npcm_pspi *priv)
0085 {
0086     u16 val;
0087
0088     val = ioread16(priv->base + NPCM_PSPI_CTL1);
0089     val |= NPCM_PSPI_CTL1_SPIEN;
0090     iowrite16(val, priv->base + NPCM_PSPI_CTL1);
0091 }
0092
0093 static inline void npcm_pspi_disable(struct npcm_pspi *priv)
0094 {
0095     u16 val;
0096
0097     val = ioread16(priv->base + NPCM_PSPI_CTL1);
0098     val &= ~NPCM_PSPI_CTL1_SPIEN;
0099     iowrite16(val, priv->base + NPCM_PSPI_CTL1);
0100 }
0101
0102 static void npcm_pspi_set_mode(struct spi_device *spi)
0103 {
0104     struct npcm_pspi *priv = spi_master_get_devdata(spi->master);
0105     u16 regtemp;
0106     u16 mode_val;
0107
0108     switch (spi->mode & SPI_MODE_X_MASK) {
0109     case SPI_MODE_0:
0110         mode_val = 0;
0111         break;
0112     case SPI_MODE_1:
0113         mode_val = NPCM_PSPI_CTL1_SCIDL;
0114         break;
0115     case SPI_MODE_2:
0116         mode_val = NPCM_PSPI_CTL1_SCM;
0117         break;
0118     case SPI_MODE_3:
0119         mode_val = NPCM_PSPI_CTL1_SCIDL | NPCM_PSPI_CTL1_SCM;
0120         break;
0121     }
0122
0123     regtemp = ioread16(priv->base + NPCM_PSPI_CTL1);
0124     regtemp &= ~(NPCM_PSPI_CTL1_SCM | NPCM_PSPI_CTL1_SCIDL);
0125     iowrite16(regtemp | mode_val, priv->base + NPCM_PSPI_CTL1);
0126 }
0127
0128 static void npcm_pspi_set_transfer_size(struct npcm_pspi *priv, int size)
0129 {
0130     u16 regtemp;
0131
0132     regtemp = ioread16(NPCM_PSPI_CTL1 + priv->base);
0133
0134     switch (size) {
0135     case 8:
0136         regtemp &= ~NPCM_PSPI_CTL1_MOD;
0137         break;
0138     case 16:
0139         regtemp |= NPCM_PSPI_CTL1_MOD;
0140         break;
0141     }
0142
0143     iowrite16(regtemp, NPCM_PSPI_CTL1 + priv->base);
0144 }
0145
0146 static void npcm_pspi_set_baudrate(struct npcm_pspi *priv, unsigned int speed)
0147 {
0148     u32 ckdiv;
0149     u16 regtemp;
0150
0151     /* the supported rates are numbers from 4 to 256. */
0152     ckdiv = DIV_ROUND_CLOSEST(clk_get_rate(priv->clk), (2 * speed)) - 1;
0153
0154     regtemp = ioread16(NPCM_PSPI_CTL1 + priv->base);
0155     regtemp &= ~NPCM_PSPI_CTL1_SCDV6_0;
0156     iowrite16(regtemp | (ckdiv << 9), NPCM_PSPI_CTL1 + priv->base);
0157 }
0158
0159 static void npcm_pspi_setup_transfer(struct spi_device *spi,
0160                      struct spi_transfer *t)
0161 {
0162     struct npcm_pspi *priv = spi_master_get_devdata(spi->master);
0163
0164     priv->tx_buf = t->tx_buf;
0165     priv->rx_buf = t->rx_buf;
0166     priv->tx_bytes = t->len;
0167     priv->rx_bytes = t->len;
0168
0169     if (!priv->is_save_param || priv->mode != spi->mode) {
0170         npcm_pspi_set_mode(spi);
0171         priv->mode = spi->mode;
0172     }
0173
0174     /*
0175      * If transfer is even length, and 8 bits per word transfer,
0176      * then implement 16 bits-per-word transfer.
0177      */
0178     if (priv->bits_per_word == 8 && !(t->len & 0x1))
0179         t->bits_per_word = 16;
0180
0181     if (!priv->is_save_param || priv->bits_per_word != t->bits_per_word) {
0182         npcm_pspi_set_transfer_size(priv, t->bits_per_word);
0183         priv->bits_per_word = t->bits_per_word;
0184     }
0185
0186     if (!priv->is_save_param || priv->speed_hz != t->speed_hz) {
0187         npcm_pspi_set_baudrate(priv, t->speed_hz);
0188         priv->speed_hz = t->speed_hz;
0189     }
0190
0191     if (!priv->is_save_param)
0192         priv->is_save_param = true;
0193 }
0194
0195 static void npcm_pspi_send(struct npcm_pspi *priv)
0196 {
0197     int wsize;
0198     u16 val;
0199
0200     wsize = min(bytes_per_word(priv->bits_per_word), priv->tx_bytes);
0201     priv->tx_bytes -= wsize;
0202
0203     if (!priv->tx_buf)
0204         return;
0205
0206     switch (wsize) {
0207     case 1:
0208         val = *priv->tx_buf++;
0209         iowrite8(val, NPCM_PSPI_DATA + priv->base);
0210         break;
0211     case 2:
0212         val = *priv->tx_buf++;
0213         val = *priv->tx_buf++ | (val << 8);
0214         iowrite16(val, NPCM_PSPI_DATA + priv->base);
0215         break;
0216     default:
0217         WARN_ON_ONCE(1);
0218         return;
0219     }
0220 }
0221
0222 static void npcm_pspi_recv(struct npcm_pspi *priv)
0223 {
0224     int rsize;
0225     u16 val;
0226
0227     rsize = min(bytes_per_word(priv->bits_per_word), priv->rx_bytes);
0228     priv->rx_bytes -= rsize;
0229
0230     if (!priv->rx_buf)
0231         return;
0232
0233     switch (rsize) {
0234     case 1:
0235         *priv->rx_buf++ = ioread8(priv->base + NPCM_PSPI_DATA);
0236         break;
0237     case 2:
0238         val = ioread16(priv->base + NPCM_PSPI_DATA);
0239         *priv->rx_buf++ = (val >> 8);
0240         *priv->rx_buf++ = val & 0xff;
0241         break;
0242     default:
0243         WARN_ON_ONCE(1);
0244         return;
0245     }
0246 }
0247
0248 static int npcm_pspi_transfer_one(struct spi_master *master,
0249                   struct spi_device *spi,
0250                   struct spi_transfer *t)
0251 {
0252     struct npcm_pspi *priv = spi_master_get_devdata(master);
0253     int status;
0254
0255     npcm_pspi_setup_transfer(spi, t);
0256     reinit_completion(&priv->xfer_done);
0257     npcm_pspi_enable(priv);
0258     status = wait_for_completion_timeout(&priv->xfer_done,
0259                          msecs_to_jiffies
0260                          (NPCM_PSPI_TIMEOUT_MS));
0261     if (status == 0) {
0262         npcm_pspi_disable(priv);
0263         return -ETIMEDOUT;
0264     }
0265
0266     return 0;
0267 }
0268
0269 static int npcm_pspi_prepare_transfer_hardware(struct spi_master *master)
0270 {
0271     struct npcm_pspi *priv = spi_master_get_devdata(master);
0272
0273     npcm_pspi_irq_enable(priv, NPCM_PSPI_CTL1_EIR | NPCM_PSPI_CTL1_EIW);
0274
0275     return 0;
0276 }
0277
0278 static int npcm_pspi_unprepare_transfer_hardware(struct spi_master *master)
0279 {
0280     struct npcm_pspi *priv = spi_master_get_devdata(master);
0281
0282     npcm_pspi_irq_disable(priv, NPCM_PSPI_CTL1_EIR | NPCM_PSPI_CTL1_EIW);
0283
0284     return 0;
0285 }
0286
0287 static void npcm_pspi_reset_hw(struct npcm_pspi *priv)
0288 {
0289     reset_control_assert(priv->reset);
0290     udelay(5);
0291     reset_control_deassert(priv->reset);
0292 }
0293
0294 static irqreturn_t npcm_pspi_handler(int irq, void *dev_id)
0295 {
0296     struct npcm_pspi *priv = dev_id;
0297     u8 stat;
0298
0299     stat = ioread8(priv->base + NPCM_PSPI_STAT);
0300
0301     if (!priv->tx_buf && !priv->rx_buf)
0302         return IRQ_NONE;
0303
0304     if (priv->tx_buf) {
0305         if (stat & NPCM_PSPI_STAT_RBF) {
0306             ioread8(NPCM_PSPI_DATA + priv->base);
0307             if (priv->tx_bytes == 0) {
0308                 npcm_pspi_disable(priv);
0309                 complete(&priv->xfer_done);
0310                 return IRQ_HANDLED;
0311             }
0312         }
0313
0314         if ((stat & NPCM_PSPI_STAT_BSY) == 0)
0315             if (priv->tx_bytes)
0316                 npcm_pspi_send(priv);
0317     }
0318
0319     if (priv->rx_buf) {
0320         if (stat & NPCM_PSPI_STAT_RBF) {
0321             if (!priv->rx_bytes)
0322                 return IRQ_NONE;
0323
0324             npcm_pspi_recv(priv);
0325
0326             if (!priv->rx_bytes) {
0327                 npcm_pspi_disable(priv);
0328                 complete(&priv->xfer_done);
0329                 return IRQ_HANDLED;
0330             }
0331         }
0332
0333         if (((stat & NPCM_PSPI_STAT_BSY) == 0) && !priv->tx_buf)
0334             iowrite8(0x0, NPCM_PSPI_DATA + priv->base);
0335     }
0336
0337     return IRQ_HANDLED;
0338 }
0339
0340 static int npcm_pspi_probe(struct platform_device *pdev)
0341 {
0342     struct npcm_pspi *priv;
0343     struct spi_master *master;
0344     unsigned long clk_hz;
0345     int irq;
0346     int ret;
0347
0348     master = spi_alloc_master(&pdev->dev, sizeof(*priv));
0349     if (!master)
0350         return -ENOMEM;
0351
0352     platform_set_drvdata(pdev, master);
0353
0354     priv = spi_master_get_devdata(master);
0355     priv->master = master;
0356     priv->is_save_param = false;
0357
0358     priv->base = devm_platform_ioremap_resource(pdev, 0);
0359     if (IS_ERR(priv->base)) {
0360         ret = PTR_ERR(priv->base);
0361         goto out_master_put;
0362     }
0363
0364     priv->clk = devm_clk_get(&pdev->dev, NULL);
0365     if (IS_ERR(priv->clk)) {
0366         dev_err(&pdev->dev, "failed to get clock\n");
0367         ret = PTR_ERR(priv->clk);
0368         goto out_master_put;
0369     }
0370
0371     ret = clk_prepare_enable(priv->clk);
0372     if (ret)
0373         goto out_master_put;
0374
0375     irq = platform_get_irq(pdev, 0);
0376     if (irq < 0) {
0377         ret = irq;
0378         goto out_disable_clk;
0379     }
0380
0381     priv->reset = devm_reset_control_get(&pdev->dev, NULL);
0382     if (IS_ERR(priv->reset)) {
0383         ret = PTR_ERR(priv->reset);
0384         goto out_disable_clk;
0385     }
0386
0387     /* reset SPI-HW block */
0388     npcm_pspi_reset_hw(priv);
0389
0390     ret = devm_request_irq(&pdev->dev, irq, npcm_pspi_handler, 0,
0391                    "npcm-pspi", priv);
0392     if (ret) {
0393         dev_err(&pdev->dev, "failed to request IRQ\n");
0394         goto out_disable_clk;
0395     }
0396
0397     init_completion(&priv->xfer_done);
0398
0399     clk_hz = clk_get_rate(priv->clk);
0400
0401     master->max_speed_hz = DIV_ROUND_UP(clk_hz, NPCM_PSPI_MIN_CLK_DIVIDER);
0402     master->min_speed_hz = DIV_ROUND_UP(clk_hz, NPCM_PSPI_MAX_CLK_DIVIDER);
0403     master->mode_bits = SPI_CPHA | SPI_CPOL;
0404     master->dev.of_node = pdev->dev.of_node;
0405     master->bus_num = -1;
0406     master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16);
0407     master->transfer_one = npcm_pspi_transfer_one;
0408     master->prepare_transfer_hardware =
0409         npcm_pspi_prepare_transfer_hardware;
0410     master->unprepare_transfer_hardware =
0411         npcm_pspi_unprepare_transfer_hardware;
0412     master->use_gpio_descriptors = true;
0413
0414     /* set to default clock rate */
0415     npcm_pspi_set_baudrate(priv, NPCM_PSPI_DEFAULT_CLK);
0416
0417     ret = devm_spi_register_master(&pdev->dev, master);
0418     if (ret)
0419         goto out_disable_clk;
0420
0421     pr_info("NPCM Peripheral SPI %d probed\n", master->bus_num);
0422
0423     return 0;
0424
0425 out_disable_clk:
0426     clk_disable_unprepare(priv->clk);
0427
0428 out_master_put:
0429     spi_master_put(master);
0430     return ret;
0431 }
0432
0433 static int npcm_pspi_remove(struct platform_device *pdev)
0434 {
0435     struct spi_master *master = platform_get_drvdata(pdev);
0436     struct npcm_pspi *priv = spi_master_get_devdata(master);
0437
0438     npcm_pspi_reset_hw(priv);
0439     clk_disable_unprepare(priv->clk);
0440
0441     return 0;
0442 }
0443
0444 static const struct of_device_id npcm_pspi_match[] = {
0445     { .compatible = "nuvoton,npcm750-pspi", .data = NULL },
0446     {}
0447 };
0448 MODULE_DEVICE_TABLE(of, npcm_pspi_match);
0449
0450 static struct platform_driver npcm_pspi_driver = {
0451     .driver     = {
0452         .name       = DRIVER_NAME,
0453         .of_match_table = npcm_pspi_match,
0454     },
0455     .probe      = npcm_pspi_probe,
0456     .remove     = npcm_pspi_remove,
0457 };
0458 module_platform_driver(npcm_pspi_driver);
0459
0460 MODULE_DESCRIPTION("NPCM peripheral SPI Controller driver");
0461 MODULE_AUTHOR("Tomer Maimon <tomer.maimon@nuvoton.com>");
0462 MODULE_LICENSE("GPL v2");
0463