drivers/spi/spi-mxic.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 //
0003 // Copyright (C) 2018 Macronix International Co., Ltd.
0004 //
0005 // Authors:
0006 //  Mason Yang <masonccyang@mxic.com.tw>
0007 //  zhengxunli <zhengxunli@mxic.com.tw>
0008 //  Boris Brezillon <boris.brezillon@bootlin.com>
0009 //
0010
0011 #include <linux/clk.h>
0012 #include <linux/io.h>
0013 #include <linux/iopoll.h>
0014 #include <linux/module.h>
0015 #include <linux/mtd/nand.h>
0016 #include <linux/mtd/nand-ecc-mxic.h>
0017 #include <linux/platform_device.h>
0018 #include <linux/pm_runtime.h>
0019 #include <linux/spi/spi.h>
0020 #include <linux/spi/spi-mem.h>
0021
0022 #define HC_CFG          0x0
0023 #define HC_CFG_IF_CFG(x)    ((x) << 27)
0024 #define HC_CFG_DUAL_SLAVE   BIT(31)
0025 #define HC_CFG_INDIVIDUAL   BIT(30)
0026 #define HC_CFG_NIO(x)       (((x) / 4) << 27)
0027 #define HC_CFG_TYPE(s, t)   ((t) << (23 + ((s) * 2)))
0028 #define HC_CFG_TYPE_SPI_NOR 0
0029 #define HC_CFG_TYPE_SPI_NAND    1
0030 #define HC_CFG_TYPE_SPI_RAM 2
0031 #define HC_CFG_TYPE_RAW_NAND    3
0032 #define HC_CFG_SLV_ACT(x)   ((x) << 21)
0033 #define HC_CFG_CLK_PH_EN    BIT(20)
0034 #define HC_CFG_CLK_POL_INV  BIT(19)
0035 #define HC_CFG_BIG_ENDIAN   BIT(18)
0036 #define HC_CFG_DATA_PASS    BIT(17)
0037 #define HC_CFG_IDLE_SIO_LVL(x)  ((x) << 16)
0038 #define HC_CFG_MAN_START_EN BIT(3)
0039 #define HC_CFG_MAN_START    BIT(2)
0040 #define HC_CFG_MAN_CS_EN    BIT(1)
0041 #define HC_CFG_MAN_CS_ASSERT    BIT(0)
0042
0043 #define INT_STS         0x4
0044 #define INT_STS_EN      0x8
0045 #define INT_SIG_EN      0xc
0046 #define INT_STS_ALL     GENMASK(31, 0)
0047 #define INT_RDY_PIN     BIT(26)
0048 #define INT_RDY_SR      BIT(25)
0049 #define INT_LNR_SUSP        BIT(24)
0050 #define INT_ECC_ERR     BIT(17)
0051 #define INT_CRC_ERR     BIT(16)
0052 #define INT_LWR_DIS     BIT(12)
0053 #define INT_LRD_DIS     BIT(11)
0054 #define INT_SDMA_INT        BIT(10)
0055 #define INT_DMA_FINISH      BIT(9)
0056 #define INT_RX_NOT_FULL     BIT(3)
0057 #define INT_RX_NOT_EMPTY    BIT(2)
0058 #define INT_TX_NOT_FULL     BIT(1)
0059 #define INT_TX_EMPTY        BIT(0)
0060
0061 #define HC_EN           0x10
0062 #define HC_EN_BIT       BIT(0)
0063
0064 #define TXD(x)          (0x14 + ((x) * 4))
0065 #define RXD         0x24
0066
0067 #define SS_CTRL(s)      (0x30 + ((s) * 4))
0068 #define LRD_CFG         0x44
0069 #define LWR_CFG         0x80
0070 #define RWW_CFG         0x70
0071 #define OP_READ         BIT(23)
0072 #define OP_DUMMY_CYC(x)     ((x) << 17)
0073 #define OP_ADDR_BYTES(x)    ((x) << 14)
0074 #define OP_CMD_BYTES(x)     (((x) - 1) << 13)
0075 #define OP_OCTA_CRC_EN      BIT(12)
0076 #define OP_DQS_EN       BIT(11)
0077 #define OP_ENHC_EN      BIT(10)
0078 #define OP_PREAMBLE_EN      BIT(9)
0079 #define OP_DATA_DDR     BIT(8)
0080 #define OP_DATA_BUSW(x)     ((x) << 6)
0081 #define OP_ADDR_DDR     BIT(5)
0082 #define OP_ADDR_BUSW(x)     ((x) << 3)
0083 #define OP_CMD_DDR      BIT(2)
0084 #define OP_CMD_BUSW(x)      (x)
0085 #define OP_BUSW_1       0
0086 #define OP_BUSW_2       1
0087 #define OP_BUSW_4       2
0088 #define OP_BUSW_8       3
0089
0090 #define OCTA_CRC        0x38
0091 #define OCTA_CRC_IN_EN(s)   BIT(3 + ((s) * 16))
0092 #define OCTA_CRC_CHUNK(s, x)    ((fls((x) / 32)) << (1 + ((s) * 16)))
0093 #define OCTA_CRC_OUT_EN(s)  BIT(0 + ((s) * 16))
0094
0095 #define ONFI_DIN_CNT(s)     (0x3c + (s))
0096
0097 #define LRD_CTRL        0x48
0098 #define RWW_CTRL        0x74
0099 #define LWR_CTRL        0x84
0100 #define LMODE_EN        BIT(31)
0101 #define LMODE_SLV_ACT(x)    ((x) << 21)
0102 #define LMODE_CMD1(x)       ((x) << 8)
0103 #define LMODE_CMD0(x)       (x)
0104
0105 #define LRD_ADDR        0x4c
0106 #define LWR_ADDR        0x88
0107 #define LRD_RANGE       0x50
0108 #define LWR_RANGE       0x8c
0109
0110 #define AXI_SLV_ADDR        0x54
0111
0112 #define DMAC_RD_CFG     0x58
0113 #define DMAC_WR_CFG     0x94
0114 #define DMAC_CFG_PERIPH_EN  BIT(31)
0115 #define DMAC_CFG_ALLFLUSH_EN    BIT(30)
0116 #define DMAC_CFG_LASTFLUSH_EN   BIT(29)
0117 #define DMAC_CFG_QE(x)      (((x) + 1) << 16)
0118 #define DMAC_CFG_BURST_LEN(x)   (((x) + 1) << 12)
0119 #define DMAC_CFG_BURST_SZ(x)    ((x) << 8)
0120 #define DMAC_CFG_DIR_READ   BIT(1)
0121 #define DMAC_CFG_START      BIT(0)
0122
0123 #define DMAC_RD_CNT     0x5c
0124 #define DMAC_WR_CNT     0x98
0125
0126 #define SDMA_ADDR       0x60
0127
0128 #define DMAM_CFG        0x64
0129 #define DMAM_CFG_START      BIT(31)
0130 #define DMAM_CFG_CONT       BIT(30)
0131 #define DMAM_CFG_SDMA_GAP(x)    (fls((x) / 8192) << 2)
0132 #define DMAM_CFG_DIR_READ   BIT(1)
0133 #define DMAM_CFG_EN     BIT(0)
0134
0135 #define DMAM_CNT        0x68
0136
0137 #define LNR_TIMER_TH        0x6c
0138
0139 #define RDM_CFG0        0x78
0140 #define RDM_CFG0_POLY(x)    (x)
0141
0142 #define RDM_CFG1        0x7c
0143 #define RDM_CFG1_RDM_EN     BIT(31)
0144 #define RDM_CFG1_SEED(x)    (x)
0145
0146 #define LWR_SUSP_CTRL       0x90
0147 #define LWR_SUSP_CTRL_EN    BIT(31)
0148
0149 #define DMAS_CTRL       0x9c
0150 #define DMAS_CTRL_EN        BIT(31)
0151 #define DMAS_CTRL_DIR_READ  BIT(30)
0152
0153 #define DATA_STROB      0xa0
0154 #define DATA_STROB_EDO_EN   BIT(2)
0155 #define DATA_STROB_INV_POL  BIT(1)
0156 #define DATA_STROB_DELAY_2CYC   BIT(0)
0157
0158 #define IDLY_CODE(x)        (0xa4 + ((x) * 4))
0159 #define IDLY_CODE_VAL(x, v) ((v) << (((x) % 4) * 8))
0160
0161 #define GPIO            0xc4
0162 #define GPIO_PT(x)      BIT(3 + ((x) * 16))
0163 #define GPIO_RESET(x)       BIT(2 + ((x) * 16))
0164 #define GPIO_HOLDB(x)       BIT(1 + ((x) * 16))
0165 #define GPIO_WPB(x)     BIT((x) * 16)
0166
0167 #define HC_VER          0xd0
0168
0169 #define HW_TEST(x)      (0xe0 + ((x) * 4))
0170
0171 struct mxic_spi {
0172     struct device *dev;
0173     struct clk *ps_clk;
0174     struct clk *send_clk;
0175     struct clk *send_dly_clk;
0176     void __iomem *regs;
0177     u32 cur_speed_hz;
0178     struct {
0179         void __iomem *map;
0180         dma_addr_t dma;
0181         size_t size;
0182     } linear;
0183
0184     struct {
0185         bool use_pipelined_conf;
0186         struct nand_ecc_engine *pipelined_engine;
0187         void *ctx;
0188     } ecc;
0189 };
0190
0191 static int mxic_spi_clk_enable(struct mxic_spi *mxic)
0192 {
0193     int ret;
0194
0195     ret = clk_prepare_enable(mxic->send_clk);
0196     if (ret)
0197         return ret;
0198
0199     ret = clk_prepare_enable(mxic->send_dly_clk);
0200     if (ret)
0201         goto err_send_dly_clk;
0202
0203     return ret;
0204
0205 err_send_dly_clk:
0206     clk_disable_unprepare(mxic->send_clk);
0207
0208     return ret;
0209 }
0210
0211 static void mxic_spi_clk_disable(struct mxic_spi *mxic)
0212 {
0213     clk_disable_unprepare(mxic->send_clk);
0214     clk_disable_unprepare(mxic->send_dly_clk);
0215 }
0216
0217 static void mxic_spi_set_input_delay_dqs(struct mxic_spi *mxic, u8 idly_code)
0218 {
0219     writel(IDLY_CODE_VAL(0, idly_code) |
0220            IDLY_CODE_VAL(1, idly_code) |
0221            IDLY_CODE_VAL(2, idly_code) |
0222            IDLY_CODE_VAL(3, idly_code),
0223            mxic->regs + IDLY_CODE(0));
0224     writel(IDLY_CODE_VAL(4, idly_code) |
0225            IDLY_CODE_VAL(5, idly_code) |
0226            IDLY_CODE_VAL(6, idly_code) |
0227            IDLY_CODE_VAL(7, idly_code),
0228            mxic->regs + IDLY_CODE(1));
0229 }
0230
0231 static int mxic_spi_clk_setup(struct mxic_spi *mxic, unsigned long freq)
0232 {
0233     int ret;
0234
0235     ret = clk_set_rate(mxic->send_clk, freq);
0236     if (ret)
0237         return ret;
0238
0239     ret = clk_set_rate(mxic->send_dly_clk, freq);
0240     if (ret)
0241         return ret;
0242
0243     /*
0244      * A constant delay range from 0x0 ~ 0x1F for input delay,
0245      * the unit is 78 ps, the max input delay is 2.418 ns.
0246      */
0247     mxic_spi_set_input_delay_dqs(mxic, 0xf);
0248
0249     /*
0250      * Phase degree = 360 * freq * output-delay
0251      * where output-delay is a constant value 1 ns in FPGA.
0252      *
0253      * Get Phase degree = 360 * freq * 1 ns
0254      *                  = 360 * freq * 1 sec / 1000000000
0255      *                  = 9 * freq / 25000000
0256      */
0257     ret = clk_set_phase(mxic->send_dly_clk, 9 * freq / 25000000);
0258     if (ret)
0259         return ret;
0260
0261     return 0;
0262 }
0263
0264 static int mxic_spi_set_freq(struct mxic_spi *mxic, unsigned long freq)
0265 {
0266     int ret;
0267
0268     if (mxic->cur_speed_hz == freq)
0269         return 0;
0270
0271     mxic_spi_clk_disable(mxic);
0272     ret = mxic_spi_clk_setup(mxic, freq);
0273     if (ret)
0274         return ret;
0275
0276     ret = mxic_spi_clk_enable(mxic);
0277     if (ret)
0278         return ret;
0279
0280     mxic->cur_speed_hz = freq;
0281
0282     return 0;
0283 }
0284
0285 static void mxic_spi_hw_init(struct mxic_spi *mxic)
0286 {
0287     writel(0, mxic->regs + DATA_STROB);
0288     writel(INT_STS_ALL, mxic->regs + INT_STS_EN);
0289     writel(0, mxic->regs + HC_EN);
0290     writel(0, mxic->regs + LRD_CFG);
0291     writel(0, mxic->regs + LRD_CTRL);
0292     writel(HC_CFG_NIO(1) | HC_CFG_TYPE(0, HC_CFG_TYPE_SPI_NOR) |
0293            HC_CFG_SLV_ACT(0) | HC_CFG_MAN_CS_EN | HC_CFG_IDLE_SIO_LVL(1),
0294            mxic->regs + HC_CFG);
0295 }
0296
0297 static u32 mxic_spi_prep_hc_cfg(struct spi_device *spi, u32 flags)
0298 {
0299     int nio = 1;
0300
0301     if (spi->mode & (SPI_TX_OCTAL | SPI_RX_OCTAL))
0302         nio = 8;
0303     else if (spi->mode & (SPI_TX_QUAD | SPI_RX_QUAD))
0304         nio = 4;
0305     else if (spi->mode & (SPI_TX_DUAL | SPI_RX_DUAL))
0306         nio = 2;
0307
0308     return flags | HC_CFG_NIO(nio) |
0309            HC_CFG_TYPE(spi->chip_select, HC_CFG_TYPE_SPI_NOR) |
0310            HC_CFG_SLV_ACT(spi->chip_select) | HC_CFG_IDLE_SIO_LVL(1);
0311 }
0312
0313 static u32 mxic_spi_mem_prep_op_cfg(const struct spi_mem_op *op,
0314                     unsigned int data_len)
0315 {
0316     u32 cfg = OP_CMD_BYTES(op->cmd.nbytes) |
0317           OP_CMD_BUSW(fls(op->cmd.buswidth) - 1) |
0318           (op->cmd.dtr ? OP_CMD_DDR : 0);
0319
0320     if (op->addr.nbytes)
0321         cfg |= OP_ADDR_BYTES(op->addr.nbytes) |
0322                OP_ADDR_BUSW(fls(op->addr.buswidth) - 1) |
0323                (op->addr.dtr ? OP_ADDR_DDR : 0);
0324
0325     if (op->dummy.nbytes)
0326         cfg |= OP_DUMMY_CYC(op->dummy.nbytes);
0327
0328     /* Direct mapping data.nbytes field is not populated */
0329     if (data_len) {
0330         cfg |= OP_DATA_BUSW(fls(op->data.buswidth) - 1) |
0331                (op->data.dtr ? OP_DATA_DDR : 0);
0332         if (op->data.dir == SPI_MEM_DATA_IN) {
0333             cfg |= OP_READ;
0334             if (op->data.dtr)
0335                 cfg |= OP_DQS_EN;
0336         }
0337     }
0338
0339     return cfg;
0340 }
0341
0342 static int mxic_spi_data_xfer(struct mxic_spi *mxic, const void *txbuf,
0343                   void *rxbuf, unsigned int len)
0344 {
0345     unsigned int pos = 0;
0346
0347     while (pos < len) {
0348         unsigned int nbytes = len - pos;
0349         u32 data = 0xffffffff;
0350         u32 sts;
0351         int ret;
0352
0353         if (nbytes > 4)
0354             nbytes = 4;
0355
0356         if (txbuf)
0357             memcpy(&data, txbuf + pos, nbytes);
0358
0359         ret = readl_poll_timeout(mxic->regs + INT_STS, sts,
0360                      sts & INT_TX_EMPTY, 0, USEC_PER_SEC);
0361         if (ret)
0362             return ret;
0363
0364         writel(data, mxic->regs + TXD(nbytes % 4));
0365
0366         ret = readl_poll_timeout(mxic->regs + INT_STS, sts,
0367                      sts & INT_TX_EMPTY, 0, USEC_PER_SEC);
0368         if (ret)
0369             return ret;
0370
0371         ret = readl_poll_timeout(mxic->regs + INT_STS, sts,
0372                      sts & INT_RX_NOT_EMPTY, 0,
0373                      USEC_PER_SEC);
0374         if (ret)
0375             return ret;
0376
0377         data = readl(mxic->regs + RXD);
0378         if (rxbuf) {
0379             data >>= (8 * (4 - nbytes));
0380             memcpy(rxbuf + pos, &data, nbytes);
0381         }
0382         WARN_ON(readl(mxic->regs + INT_STS) & INT_RX_NOT_EMPTY);
0383
0384         pos += nbytes;
0385     }
0386
0387     return 0;
0388 }
0389
0390 static ssize_t mxic_spi_mem_dirmap_read(struct spi_mem_dirmap_desc *desc,
0391                     u64 offs, size_t len, void *buf)
0392 {
0393     struct mxic_spi *mxic = spi_master_get_devdata(desc->mem->spi->master);
0394     int ret;
0395     u32 sts;
0396
0397     if (WARN_ON(offs + desc->info.offset + len > U32_MAX))
0398         return -EINVAL;
0399
0400     writel(mxic_spi_prep_hc_cfg(desc->mem->spi, 0), mxic->regs + HC_CFG);
0401
0402     writel(mxic_spi_mem_prep_op_cfg(&desc->info.op_tmpl, len),
0403            mxic->regs + LRD_CFG);
0404     writel(desc->info.offset + offs, mxic->regs + LRD_ADDR);
0405     len = min_t(size_t, len, mxic->linear.size);
0406     writel(len, mxic->regs + LRD_RANGE);
0407     writel(LMODE_CMD0(desc->info.op_tmpl.cmd.opcode) |
0408            LMODE_SLV_ACT(desc->mem->spi->chip_select) |
0409            LMODE_EN,
0410            mxic->regs + LRD_CTRL);
0411
0412     if (mxic->ecc.use_pipelined_conf && desc->info.op_tmpl.data.ecc) {
0413         ret = mxic_ecc_process_data_pipelined(mxic->ecc.pipelined_engine,
0414                               NAND_PAGE_READ,
0415                               mxic->linear.dma + offs);
0416         if (ret)
0417             return ret;
0418     } else {
0419         memcpy_fromio(buf, mxic->linear.map, len);
0420     }
0421
0422     writel(INT_LRD_DIS, mxic->regs + INT_STS);
0423     writel(0, mxic->regs + LRD_CTRL);
0424
0425     ret = readl_poll_timeout(mxic->regs + INT_STS, sts,
0426                  sts & INT_LRD_DIS, 0, USEC_PER_SEC);
0427     if (ret)
0428         return ret;
0429
0430     return len;
0431 }
0432
0433 static ssize_t mxic_spi_mem_dirmap_write(struct spi_mem_dirmap_desc *desc,
0434                      u64 offs, size_t len,
0435                      const void *buf)
0436 {
0437     struct mxic_spi *mxic = spi_master_get_devdata(desc->mem->spi->master);
0438     u32 sts;
0439     int ret;
0440
0441     if (WARN_ON(offs + desc->info.offset + len > U32_MAX))
0442         return -EINVAL;
0443
0444     writel(mxic_spi_prep_hc_cfg(desc->mem->spi, 0), mxic->regs + HC_CFG);
0445
0446     writel(mxic_spi_mem_prep_op_cfg(&desc->info.op_tmpl, len),
0447            mxic->regs + LWR_CFG);
0448     writel(desc->info.offset + offs, mxic->regs + LWR_ADDR);
0449     len = min_t(size_t, len, mxic->linear.size);
0450     writel(len, mxic->regs + LWR_RANGE);
0451     writel(LMODE_CMD0(desc->info.op_tmpl.cmd.opcode) |
0452            LMODE_SLV_ACT(desc->mem->spi->chip_select) |
0453            LMODE_EN,
0454            mxic->regs + LWR_CTRL);
0455
0456     if (mxic->ecc.use_pipelined_conf && desc->info.op_tmpl.data.ecc) {
0457         ret = mxic_ecc_process_data_pipelined(mxic->ecc.pipelined_engine,
0458                               NAND_PAGE_WRITE,
0459                               mxic->linear.dma + offs);
0460         if (ret)
0461             return ret;
0462     } else {
0463         memcpy_toio(mxic->linear.map, buf, len);
0464     }
0465
0466     writel(INT_LWR_DIS, mxic->regs + INT_STS);
0467     writel(0, mxic->regs + LWR_CTRL);
0468
0469     ret = readl_poll_timeout(mxic->regs + INT_STS, sts,
0470                  sts & INT_LWR_DIS, 0, USEC_PER_SEC);
0471     if (ret)
0472         return ret;
0473
0474     return len;
0475 }
0476
0477 static bool mxic_spi_mem_supports_op(struct spi_mem *mem,
0478                      const struct spi_mem_op *op)
0479 {
0480     if (op->data.buswidth > 8 || op->addr.buswidth > 8 ||
0481         op->dummy.buswidth > 8 || op->cmd.buswidth > 8)
0482         return false;
0483
0484     if (op->data.nbytes && op->dummy.nbytes &&
0485         op->data.buswidth != op->dummy.buswidth)
0486         return false;
0487
0488     if (op->addr.nbytes > 7)
0489         return false;
0490
0491     return spi_mem_default_supports_op(mem, op);
0492 }
0493
0494 static int mxic_spi_mem_dirmap_create(struct spi_mem_dirmap_desc *desc)
0495 {
0496     struct mxic_spi *mxic = spi_master_get_devdata(desc->mem->spi->master);
0497
0498     if (!mxic->linear.map)
0499         return -EINVAL;
0500
0501     if (desc->info.offset + desc->info.length > U32_MAX)
0502         return -EINVAL;
0503
0504     if (!mxic_spi_mem_supports_op(desc->mem, &desc->info.op_tmpl))
0505         return -EOPNOTSUPP;
0506
0507     return 0;
0508 }
0509
0510 static int mxic_spi_mem_exec_op(struct spi_mem *mem,
0511                 const struct spi_mem_op *op)
0512 {
0513     struct mxic_spi *mxic = spi_master_get_devdata(mem->spi->master);
0514     int i, ret;
0515     u8 addr[8], cmd[2];
0516
0517     ret = mxic_spi_set_freq(mxic, mem->spi->max_speed_hz);
0518     if (ret)
0519         return ret;
0520
0521     writel(mxic_spi_prep_hc_cfg(mem->spi, HC_CFG_MAN_CS_EN),
0522            mxic->regs + HC_CFG);
0523
0524     writel(HC_EN_BIT, mxic->regs + HC_EN);
0525
0526     writel(mxic_spi_mem_prep_op_cfg(op, op->data.nbytes),
0527            mxic->regs + SS_CTRL(mem->spi->chip_select));
0528
0529     writel(readl(mxic->regs + HC_CFG) | HC_CFG_MAN_CS_ASSERT,
0530            mxic->regs + HC_CFG);
0531
0532     for (i = 0; i < op->cmd.nbytes; i++)
0533         cmd[i] = op->cmd.opcode >> (8 * (op->cmd.nbytes - i - 1));
0534
0535     ret = mxic_spi_data_xfer(mxic, cmd, NULL, op->cmd.nbytes);
0536     if (ret)
0537         goto out;
0538
0539     for (i = 0; i < op->addr.nbytes; i++)
0540         addr[i] = op->addr.val >> (8 * (op->addr.nbytes - i - 1));
0541
0542     ret = mxic_spi_data_xfer(mxic, addr, NULL, op->addr.nbytes);
0543     if (ret)
0544         goto out;
0545
0546     ret = mxic_spi_data_xfer(mxic, NULL, NULL, op->dummy.nbytes);
0547     if (ret)
0548         goto out;
0549
0550     ret = mxic_spi_data_xfer(mxic,
0551                  op->data.dir == SPI_MEM_DATA_OUT ?
0552                  op->data.buf.out : NULL,
0553                  op->data.dir == SPI_MEM_DATA_IN ?
0554                  op->data.buf.in : NULL,
0555                  op->data.nbytes);
0556
0557 out:
0558     writel(readl(mxic->regs + HC_CFG) & ~HC_CFG_MAN_CS_ASSERT,
0559            mxic->regs + HC_CFG);
0560     writel(0, mxic->regs + HC_EN);
0561
0562     return ret;
0563 }
0564
0565 static const struct spi_controller_mem_ops mxic_spi_mem_ops = {
0566     .supports_op = mxic_spi_mem_supports_op,
0567     .exec_op = mxic_spi_mem_exec_op,
0568     .dirmap_create = mxic_spi_mem_dirmap_create,
0569     .dirmap_read = mxic_spi_mem_dirmap_read,
0570     .dirmap_write = mxic_spi_mem_dirmap_write,
0571 };
0572
0573 static const struct spi_controller_mem_caps mxic_spi_mem_caps = {
0574     .dtr = true,
0575     .ecc = true,
0576 };
0577
0578 static void mxic_spi_set_cs(struct spi_device *spi, bool lvl)
0579 {
0580     struct mxic_spi *mxic = spi_master_get_devdata(spi->master);
0581
0582     if (!lvl) {
0583         writel(readl(mxic->regs + HC_CFG) | HC_CFG_MAN_CS_EN,
0584                mxic->regs + HC_CFG);
0585         writel(HC_EN_BIT, mxic->regs + HC_EN);
0586         writel(readl(mxic->regs + HC_CFG) | HC_CFG_MAN_CS_ASSERT,
0587                mxic->regs + HC_CFG);
0588     } else {
0589         writel(readl(mxic->regs + HC_CFG) & ~HC_CFG_MAN_CS_ASSERT,
0590                mxic->regs + HC_CFG);
0591         writel(0, mxic->regs + HC_EN);
0592     }
0593 }
0594
0595 static int mxic_spi_transfer_one(struct spi_master *master,
0596                  struct spi_device *spi,
0597                  struct spi_transfer *t)
0598 {
0599     struct mxic_spi *mxic = spi_master_get_devdata(master);
0600     unsigned int busw = OP_BUSW_1;
0601     int ret;
0602
0603     if (t->rx_buf && t->tx_buf) {
0604         if (((spi->mode & SPI_TX_QUAD) &&
0605              !(spi->mode & SPI_RX_QUAD)) ||
0606             ((spi->mode & SPI_TX_DUAL) &&
0607              !(spi->mode & SPI_RX_DUAL)))
0608             return -ENOTSUPP;
0609     }
0610
0611     ret = mxic_spi_set_freq(mxic, t->speed_hz);
0612     if (ret)
0613         return ret;
0614
0615     if (t->tx_buf) {
0616         if (spi->mode & SPI_TX_QUAD)
0617             busw = OP_BUSW_4;
0618         else if (spi->mode & SPI_TX_DUAL)
0619             busw = OP_BUSW_2;
0620     } else if (t->rx_buf) {
0621         if (spi->mode & SPI_RX_QUAD)
0622             busw = OP_BUSW_4;
0623         else if (spi->mode & SPI_RX_DUAL)
0624             busw = OP_BUSW_2;
0625     }
0626
0627     writel(OP_CMD_BYTES(1) | OP_CMD_BUSW(busw) |
0628            OP_DATA_BUSW(busw) | (t->rx_buf ? OP_READ : 0),
0629            mxic->regs + SS_CTRL(0));
0630
0631     ret = mxic_spi_data_xfer(mxic, t->tx_buf, t->rx_buf, t->len);
0632     if (ret)
0633         return ret;
0634
0635     spi_finalize_current_transfer(master);
0636
0637     return 0;
0638 }
0639
0640 /* ECC wrapper */
0641 static int mxic_spi_mem_ecc_init_ctx(struct nand_device *nand)
0642 {
0643     struct nand_ecc_engine_ops *ops = mxic_ecc_get_pipelined_ops();
0644     struct mxic_spi *mxic = nand->ecc.engine->priv;
0645
0646     mxic->ecc.use_pipelined_conf = true;
0647
0648     return ops->init_ctx(nand);
0649 }
0650
0651 static void mxic_spi_mem_ecc_cleanup_ctx(struct nand_device *nand)
0652 {
0653     struct nand_ecc_engine_ops *ops = mxic_ecc_get_pipelined_ops();
0654     struct mxic_spi *mxic = nand->ecc.engine->priv;
0655
0656     mxic->ecc.use_pipelined_conf = false;
0657
0658     ops->cleanup_ctx(nand);
0659 }
0660
0661 static int mxic_spi_mem_ecc_prepare_io_req(struct nand_device *nand,
0662                        struct nand_page_io_req *req)
0663 {
0664     struct nand_ecc_engine_ops *ops = mxic_ecc_get_pipelined_ops();
0665
0666     return ops->prepare_io_req(nand, req);
0667 }
0668
0669 static int mxic_spi_mem_ecc_finish_io_req(struct nand_device *nand,
0670                       struct nand_page_io_req *req)
0671 {
0672     struct nand_ecc_engine_ops *ops = mxic_ecc_get_pipelined_ops();
0673
0674     return ops->finish_io_req(nand, req);
0675 }
0676
0677 static struct nand_ecc_engine_ops mxic_spi_mem_ecc_engine_pipelined_ops = {
0678     .init_ctx = mxic_spi_mem_ecc_init_ctx,
0679     .cleanup_ctx = mxic_spi_mem_ecc_cleanup_ctx,
0680     .prepare_io_req = mxic_spi_mem_ecc_prepare_io_req,
0681     .finish_io_req = mxic_spi_mem_ecc_finish_io_req,
0682 };
0683
0684 static void mxic_spi_mem_ecc_remove(struct mxic_spi *mxic)
0685 {
0686     if (mxic->ecc.pipelined_engine) {
0687         mxic_ecc_put_pipelined_engine(mxic->ecc.pipelined_engine);
0688         nand_ecc_unregister_on_host_hw_engine(mxic->ecc.pipelined_engine);
0689     }
0690 }
0691
0692 static int mxic_spi_mem_ecc_probe(struct platform_device *pdev,
0693                   struct mxic_spi *mxic)
0694 {
0695     struct nand_ecc_engine *eng;
0696
0697     if (!mxic_ecc_get_pipelined_ops())
0698         return -EOPNOTSUPP;
0699
0700     eng = mxic_ecc_get_pipelined_engine(pdev);
0701     if (IS_ERR(eng))
0702         return PTR_ERR(eng);
0703
0704     eng->dev = &pdev->dev;
0705     eng->integration = NAND_ECC_ENGINE_INTEGRATION_PIPELINED;
0706     eng->ops = &mxic_spi_mem_ecc_engine_pipelined_ops;
0707     eng->priv = mxic;
0708     mxic->ecc.pipelined_engine = eng;
0709     nand_ecc_register_on_host_hw_engine(eng);
0710
0711     return 0;
0712 }
0713
0714 static int __maybe_unused mxic_spi_runtime_suspend(struct device *dev)
0715 {
0716     struct spi_master *master = dev_get_drvdata(dev);
0717     struct mxic_spi *mxic = spi_master_get_devdata(master);
0718
0719     mxic_spi_clk_disable(mxic);
0720     clk_disable_unprepare(mxic->ps_clk);
0721
0722     return 0;
0723 }
0724
0725 static int __maybe_unused mxic_spi_runtime_resume(struct device *dev)
0726 {
0727     struct spi_master *master = dev_get_drvdata(dev);
0728     struct mxic_spi *mxic = spi_master_get_devdata(master);
0729     int ret;
0730
0731     ret = clk_prepare_enable(mxic->ps_clk);
0732     if (ret) {
0733         dev_err(dev, "Cannot enable ps_clock.\n");
0734         return ret;
0735     }
0736
0737     return mxic_spi_clk_enable(mxic);
0738 }
0739
0740 static const struct dev_pm_ops mxic_spi_dev_pm_ops = {
0741     SET_RUNTIME_PM_OPS(mxic_spi_runtime_suspend,
0742                mxic_spi_runtime_resume, NULL)
0743 };
0744
0745 static int mxic_spi_probe(struct platform_device *pdev)
0746 {
0747     struct spi_master *master;
0748     struct resource *res;
0749     struct mxic_spi *mxic;
0750     int ret;
0751
0752     master = devm_spi_alloc_master(&pdev->dev, sizeof(struct mxic_spi));
0753     if (!master)
0754         return -ENOMEM;
0755
0756     platform_set_drvdata(pdev, master);
0757
0758     mxic = spi_master_get_devdata(master);
0759     mxic->dev = &pdev->dev;
0760
0761     master->dev.of_node = pdev->dev.of_node;
0762
0763     mxic->ps_clk = devm_clk_get(&pdev->dev, "ps_clk");
0764     if (IS_ERR(mxic->ps_clk))
0765         return PTR_ERR(mxic->ps_clk);
0766
0767     mxic->send_clk = devm_clk_get(&pdev->dev, "send_clk");
0768     if (IS_ERR(mxic->send_clk))
0769         return PTR_ERR(mxic->send_clk);
0770
0771     mxic->send_dly_clk = devm_clk_get(&pdev->dev, "send_dly_clk");
0772     if (IS_ERR(mxic->send_dly_clk))
0773         return PTR_ERR(mxic->send_dly_clk);
0774
0775     res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
0776     mxic->regs = devm_ioremap_resource(&pdev->dev, res);
0777     if (IS_ERR(mxic->regs))
0778         return PTR_ERR(mxic->regs);
0779
0780     res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dirmap");
0781     mxic->linear.map = devm_ioremap_resource(&pdev->dev, res);
0782     if (!IS_ERR(mxic->linear.map)) {
0783         mxic->linear.dma = res->start;
0784         mxic->linear.size = resource_size(res);
0785     } else {
0786         mxic->linear.map = NULL;
0787     }
0788
0789     pm_runtime_enable(&pdev->dev);
0790     master->auto_runtime_pm = true;
0791
0792     master->num_chipselect = 1;
0793     master->mem_ops = &mxic_spi_mem_ops;
0794     master->mem_caps = &mxic_spi_mem_caps;
0795
0796     master->set_cs = mxic_spi_set_cs;
0797     master->transfer_one = mxic_spi_transfer_one;
0798     master->bits_per_word_mask = SPI_BPW_MASK(8);
0799     master->mode_bits = SPI_CPOL | SPI_CPHA |
0800             SPI_RX_DUAL | SPI_TX_DUAL |
0801             SPI_RX_QUAD | SPI_TX_QUAD |
0802             SPI_RX_OCTAL | SPI_TX_OCTAL;
0803
0804     mxic_spi_hw_init(mxic);
0805
0806     ret = mxic_spi_mem_ecc_probe(pdev, mxic);
0807     if (ret == -EPROBE_DEFER) {
0808         pm_runtime_disable(&pdev->dev);
0809         return ret;
0810     }
0811
0812     ret = spi_register_master(master);
0813     if (ret) {
0814         dev_err(&pdev->dev, "spi_register_master failed\n");
0815         pm_runtime_disable(&pdev->dev);
0816         mxic_spi_mem_ecc_remove(mxic);
0817     }
0818
0819     return ret;
0820 }
0821
0822 static int mxic_spi_remove(struct platform_device *pdev)
0823 {
0824     struct spi_master *master = platform_get_drvdata(pdev);
0825     struct mxic_spi *mxic = spi_master_get_devdata(master);
0826
0827     pm_runtime_disable(&pdev->dev);
0828     mxic_spi_mem_ecc_remove(mxic);
0829     spi_unregister_master(master);
0830
0831     return 0;
0832 }
0833
0834 static const struct of_device_id mxic_spi_of_ids[] = {
0835     { .compatible = "mxicy,mx25f0a-spi", },
0836     { /* sentinel */ }
0837 };
0838 MODULE_DEVICE_TABLE(of, mxic_spi_of_ids);
0839
0840 static struct platform_driver mxic_spi_driver = {
0841     .probe = mxic_spi_probe,
0842     .remove = mxic_spi_remove,
0843     .driver = {
0844         .name = "mxic-spi",
0845         .of_match_table = mxic_spi_of_ids,
0846         .pm = &mxic_spi_dev_pm_ops,
0847     },
0848 };
0849 module_platform_driver(mxic_spi_driver);
0850
0851 MODULE_AUTHOR("Mason Yang <masonccyang@mxic.com.tw>");
0852 MODULE_DESCRIPTION("MX25F0A SPI controller driver");
0853 MODULE_LICENSE("GPL v2");