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0001 // SPDX-License-Identifier: GPL-2.0
0002 //
0003 // Mediatek SPI NOR controller driver
0004 //
0005 // Copyright (C) 2020 Chuanhong Guo <gch981213@gmail.com>
0006 
0007 #include <linux/bits.h>
0008 #include <linux/clk.h>
0009 #include <linux/completion.h>
0010 #include <linux/dma-mapping.h>
0011 #include <linux/interrupt.h>
0012 #include <linux/io.h>
0013 #include <linux/iopoll.h>
0014 #include <linux/kernel.h>
0015 #include <linux/module.h>
0016 #include <linux/of_device.h>
0017 #include <linux/pm_runtime.h>
0018 #include <linux/spi/spi.h>
0019 #include <linux/spi/spi-mem.h>
0020 #include <linux/string.h>
0021 
0022 #define DRIVER_NAME "mtk-spi-nor"
0023 
0024 #define MTK_NOR_REG_CMD         0x00
0025 #define MTK_NOR_CMD_WRITE       BIT(4)
0026 #define MTK_NOR_CMD_PROGRAM     BIT(2)
0027 #define MTK_NOR_CMD_READ        BIT(0)
0028 #define MTK_NOR_CMD_MASK        GENMASK(5, 0)
0029 
0030 #define MTK_NOR_REG_PRG_CNT     0x04
0031 #define MTK_NOR_PRG_CNT_MAX     56
0032 #define MTK_NOR_REG_RDATA       0x0c
0033 
0034 #define MTK_NOR_REG_RADR0       0x10
0035 #define MTK_NOR_REG_RADR(n)     (MTK_NOR_REG_RADR0 + 4 * (n))
0036 #define MTK_NOR_REG_RADR3       0xc8
0037 
0038 #define MTK_NOR_REG_WDATA       0x1c
0039 
0040 #define MTK_NOR_REG_PRGDATA0        0x20
0041 #define MTK_NOR_REG_PRGDATA(n)      (MTK_NOR_REG_PRGDATA0 + 4 * (n))
0042 #define MTK_NOR_REG_PRGDATA_MAX     5
0043 
0044 #define MTK_NOR_REG_SHIFT0      0x38
0045 #define MTK_NOR_REG_SHIFT(n)        (MTK_NOR_REG_SHIFT0 + 4 * (n))
0046 #define MTK_NOR_REG_SHIFT_MAX       9
0047 
0048 #define MTK_NOR_REG_CFG1        0x60
0049 #define MTK_NOR_FAST_READ       BIT(0)
0050 
0051 #define MTK_NOR_REG_CFG2        0x64
0052 #define MTK_NOR_WR_CUSTOM_OP_EN     BIT(4)
0053 #define MTK_NOR_WR_BUF_EN       BIT(0)
0054 
0055 #define MTK_NOR_REG_PP_DATA     0x98
0056 
0057 #define MTK_NOR_REG_IRQ_STAT        0xa8
0058 #define MTK_NOR_REG_IRQ_EN      0xac
0059 #define MTK_NOR_IRQ_DMA         BIT(7)
0060 #define MTK_NOR_IRQ_MASK        GENMASK(7, 0)
0061 
0062 #define MTK_NOR_REG_CFG3        0xb4
0063 #define MTK_NOR_DISABLE_WREN        BIT(7)
0064 #define MTK_NOR_DISABLE_SR_POLL     BIT(5)
0065 
0066 #define MTK_NOR_REG_WP          0xc4
0067 #define MTK_NOR_ENABLE_SF_CMD       0x30
0068 
0069 #define MTK_NOR_REG_BUSCFG      0xcc
0070 #define MTK_NOR_4B_ADDR         BIT(4)
0071 #define MTK_NOR_QUAD_ADDR       BIT(3)
0072 #define MTK_NOR_QUAD_READ       BIT(2)
0073 #define MTK_NOR_DUAL_ADDR       BIT(1)
0074 #define MTK_NOR_DUAL_READ       BIT(0)
0075 #define MTK_NOR_BUS_MODE_MASK       GENMASK(4, 0)
0076 
0077 #define MTK_NOR_REG_DMA_CTL     0x718
0078 #define MTK_NOR_DMA_START       BIT(0)
0079 
0080 #define MTK_NOR_REG_DMA_FADR        0x71c
0081 #define MTK_NOR_REG_DMA_DADR        0x720
0082 #define MTK_NOR_REG_DMA_END_DADR    0x724
0083 #define MTK_NOR_REG_DMA_DADR_HB     0x738
0084 #define MTK_NOR_REG_DMA_END_DADR_HB 0x73c
0085 
0086 #define MTK_NOR_PRG_MAX_SIZE        6
0087 // Reading DMA src/dst addresses have to be 16-byte aligned
0088 #define MTK_NOR_DMA_ALIGN       16
0089 #define MTK_NOR_DMA_ALIGN_MASK      (MTK_NOR_DMA_ALIGN - 1)
0090 // and we allocate a bounce buffer if destination address isn't aligned.
0091 #define MTK_NOR_BOUNCE_BUF_SIZE     PAGE_SIZE
0092 
0093 // Buffered page program can do one 128-byte transfer
0094 #define MTK_NOR_PP_SIZE         128
0095 
0096 #define CLK_TO_US(sp, clkcnt)       DIV_ROUND_UP(clkcnt, sp->spi_freq / 1000000)
0097 
0098 struct mtk_nor_caps {
0099     u8 dma_bits;
0100 
0101     /* extra_dummy_bit is adding for the IP of new SoCs.
0102      * Some new SoCs modify the timing of fetching registers' values
0103      * and IDs of nor flash, they need a extra_dummy_bit which can add
0104      * more clock cycles for fetching data.
0105      */
0106     u8 extra_dummy_bit;
0107 };
0108 
0109 struct mtk_nor {
0110     struct spi_controller *ctlr;
0111     struct device *dev;
0112     void __iomem *base;
0113     u8 *buffer;
0114     dma_addr_t buffer_dma;
0115     struct clk *spi_clk;
0116     struct clk *ctlr_clk;
0117     struct clk *axi_clk;
0118     struct clk *axi_s_clk;
0119     unsigned int spi_freq;
0120     bool wbuf_en;
0121     bool has_irq;
0122     bool high_dma;
0123     struct completion op_done;
0124     const struct mtk_nor_caps *caps;
0125 };
0126 
0127 static inline void mtk_nor_rmw(struct mtk_nor *sp, u32 reg, u32 set, u32 clr)
0128 {
0129     u32 val = readl(sp->base + reg);
0130 
0131     val &= ~clr;
0132     val |= set;
0133     writel(val, sp->base + reg);
0134 }
0135 
0136 static inline int mtk_nor_cmd_exec(struct mtk_nor *sp, u32 cmd, ulong clk)
0137 {
0138     ulong delay = CLK_TO_US(sp, clk);
0139     u32 reg;
0140     int ret;
0141 
0142     writel(cmd, sp->base + MTK_NOR_REG_CMD);
0143     ret = readl_poll_timeout(sp->base + MTK_NOR_REG_CMD, reg, !(reg & cmd),
0144                  delay / 3, (delay + 1) * 200);
0145     if (ret < 0)
0146         dev_err(sp->dev, "command %u timeout.\n", cmd);
0147     return ret;
0148 }
0149 
0150 static void mtk_nor_set_addr(struct mtk_nor *sp, const struct spi_mem_op *op)
0151 {
0152     u32 addr = op->addr.val;
0153     int i;
0154 
0155     for (i = 0; i < 3; i++) {
0156         writeb(addr & 0xff, sp->base + MTK_NOR_REG_RADR(i));
0157         addr >>= 8;
0158     }
0159     if (op->addr.nbytes == 4) {
0160         writeb(addr & 0xff, sp->base + MTK_NOR_REG_RADR3);
0161         mtk_nor_rmw(sp, MTK_NOR_REG_BUSCFG, MTK_NOR_4B_ADDR, 0);
0162     } else {
0163         mtk_nor_rmw(sp, MTK_NOR_REG_BUSCFG, 0, MTK_NOR_4B_ADDR);
0164     }
0165 }
0166 
0167 static bool need_bounce(struct mtk_nor *sp, const struct spi_mem_op *op)
0168 {
0169     return ((uintptr_t)op->data.buf.in & MTK_NOR_DMA_ALIGN_MASK);
0170 }
0171 
0172 static bool mtk_nor_match_read(const struct spi_mem_op *op)
0173 {
0174     int dummy = 0;
0175 
0176     if (op->dummy.nbytes)
0177         dummy = op->dummy.nbytes * BITS_PER_BYTE / op->dummy.buswidth;
0178 
0179     if ((op->data.buswidth == 2) || (op->data.buswidth == 4)) {
0180         if (op->addr.buswidth == 1)
0181             return dummy == 8;
0182         else if (op->addr.buswidth == 2)
0183             return dummy == 4;
0184         else if (op->addr.buswidth == 4)
0185             return dummy == 6;
0186     } else if ((op->addr.buswidth == 1) && (op->data.buswidth == 1)) {
0187         if (op->cmd.opcode == 0x03)
0188             return dummy == 0;
0189         else if (op->cmd.opcode == 0x0b)
0190             return dummy == 8;
0191     }
0192     return false;
0193 }
0194 
0195 static bool mtk_nor_match_prg(const struct spi_mem_op *op)
0196 {
0197     int tx_len, rx_len, prg_len, prg_left;
0198 
0199     // prg mode is spi-only.
0200     if ((op->cmd.buswidth > 1) || (op->addr.buswidth > 1) ||
0201         (op->dummy.buswidth > 1) || (op->data.buswidth > 1))
0202         return false;
0203 
0204     tx_len = op->cmd.nbytes + op->addr.nbytes;
0205 
0206     if (op->data.dir == SPI_MEM_DATA_OUT) {
0207         // count dummy bytes only if we need to write data after it
0208         tx_len += op->dummy.nbytes;
0209 
0210         // leave at least one byte for data
0211         if (tx_len > MTK_NOR_REG_PRGDATA_MAX)
0212             return false;
0213 
0214         // if there's no addr, meaning adjust_op_size is impossible,
0215         // check data length as well.
0216         if ((!op->addr.nbytes) &&
0217             (tx_len + op->data.nbytes > MTK_NOR_REG_PRGDATA_MAX + 1))
0218             return false;
0219     } else if (op->data.dir == SPI_MEM_DATA_IN) {
0220         if (tx_len > MTK_NOR_REG_PRGDATA_MAX + 1)
0221             return false;
0222 
0223         rx_len = op->data.nbytes;
0224         prg_left = MTK_NOR_PRG_CNT_MAX / 8 - tx_len - op->dummy.nbytes;
0225         if (prg_left > MTK_NOR_REG_SHIFT_MAX + 1)
0226             prg_left = MTK_NOR_REG_SHIFT_MAX + 1;
0227         if (rx_len > prg_left) {
0228             if (!op->addr.nbytes)
0229                 return false;
0230             rx_len = prg_left;
0231         }
0232 
0233         prg_len = tx_len + op->dummy.nbytes + rx_len;
0234         if (prg_len > MTK_NOR_PRG_CNT_MAX / 8)
0235             return false;
0236     } else {
0237         prg_len = tx_len + op->dummy.nbytes;
0238         if (prg_len > MTK_NOR_PRG_CNT_MAX / 8)
0239             return false;
0240     }
0241     return true;
0242 }
0243 
0244 static void mtk_nor_adj_prg_size(struct spi_mem_op *op)
0245 {
0246     int tx_len, tx_left, prg_left;
0247 
0248     tx_len = op->cmd.nbytes + op->addr.nbytes;
0249     if (op->data.dir == SPI_MEM_DATA_OUT) {
0250         tx_len += op->dummy.nbytes;
0251         tx_left = MTK_NOR_REG_PRGDATA_MAX + 1 - tx_len;
0252         if (op->data.nbytes > tx_left)
0253             op->data.nbytes = tx_left;
0254     } else if (op->data.dir == SPI_MEM_DATA_IN) {
0255         prg_left = MTK_NOR_PRG_CNT_MAX / 8 - tx_len - op->dummy.nbytes;
0256         if (prg_left > MTK_NOR_REG_SHIFT_MAX + 1)
0257             prg_left = MTK_NOR_REG_SHIFT_MAX + 1;
0258         if (op->data.nbytes > prg_left)
0259             op->data.nbytes = prg_left;
0260     }
0261 }
0262 
0263 static int mtk_nor_adjust_op_size(struct spi_mem *mem, struct spi_mem_op *op)
0264 {
0265     struct mtk_nor *sp = spi_controller_get_devdata(mem->spi->master);
0266 
0267     if (!op->data.nbytes)
0268         return 0;
0269 
0270     if ((op->addr.nbytes == 3) || (op->addr.nbytes == 4)) {
0271         if ((op->data.dir == SPI_MEM_DATA_IN) &&
0272             mtk_nor_match_read(op)) {
0273             // limit size to prevent timeout calculation overflow
0274             if (op->data.nbytes > 0x400000)
0275                 op->data.nbytes = 0x400000;
0276 
0277             if ((op->addr.val & MTK_NOR_DMA_ALIGN_MASK) ||
0278                 (op->data.nbytes < MTK_NOR_DMA_ALIGN))
0279                 op->data.nbytes = 1;
0280             else if (!need_bounce(sp, op))
0281                 op->data.nbytes &= ~MTK_NOR_DMA_ALIGN_MASK;
0282             else if (op->data.nbytes > MTK_NOR_BOUNCE_BUF_SIZE)
0283                 op->data.nbytes = MTK_NOR_BOUNCE_BUF_SIZE;
0284             return 0;
0285         } else if (op->data.dir == SPI_MEM_DATA_OUT) {
0286             if (op->data.nbytes >= MTK_NOR_PP_SIZE)
0287                 op->data.nbytes = MTK_NOR_PP_SIZE;
0288             else
0289                 op->data.nbytes = 1;
0290             return 0;
0291         }
0292     }
0293 
0294     mtk_nor_adj_prg_size(op);
0295     return 0;
0296 }
0297 
0298 static bool mtk_nor_supports_op(struct spi_mem *mem,
0299                 const struct spi_mem_op *op)
0300 {
0301     if (!spi_mem_default_supports_op(mem, op))
0302         return false;
0303 
0304     if (op->cmd.buswidth != 1)
0305         return false;
0306 
0307     if ((op->addr.nbytes == 3) || (op->addr.nbytes == 4)) {
0308         switch (op->data.dir) {
0309         case SPI_MEM_DATA_IN:
0310             if (mtk_nor_match_read(op))
0311                 return true;
0312             break;
0313         case SPI_MEM_DATA_OUT:
0314             if ((op->addr.buswidth == 1) &&
0315                 (op->dummy.nbytes == 0) &&
0316                 (op->data.buswidth == 1))
0317                 return true;
0318             break;
0319         default:
0320             break;
0321         }
0322     }
0323 
0324     return mtk_nor_match_prg(op);
0325 }
0326 
0327 static void mtk_nor_setup_bus(struct mtk_nor *sp, const struct spi_mem_op *op)
0328 {
0329     u32 reg = 0;
0330 
0331     if (op->addr.nbytes == 4)
0332         reg |= MTK_NOR_4B_ADDR;
0333 
0334     if (op->data.buswidth == 4) {
0335         reg |= MTK_NOR_QUAD_READ;
0336         writeb(op->cmd.opcode, sp->base + MTK_NOR_REG_PRGDATA(4));
0337         if (op->addr.buswidth == 4)
0338             reg |= MTK_NOR_QUAD_ADDR;
0339     } else if (op->data.buswidth == 2) {
0340         reg |= MTK_NOR_DUAL_READ;
0341         writeb(op->cmd.opcode, sp->base + MTK_NOR_REG_PRGDATA(3));
0342         if (op->addr.buswidth == 2)
0343             reg |= MTK_NOR_DUAL_ADDR;
0344     } else {
0345         if (op->cmd.opcode == 0x0b)
0346             mtk_nor_rmw(sp, MTK_NOR_REG_CFG1, MTK_NOR_FAST_READ, 0);
0347         else
0348             mtk_nor_rmw(sp, MTK_NOR_REG_CFG1, 0, MTK_NOR_FAST_READ);
0349     }
0350     mtk_nor_rmw(sp, MTK_NOR_REG_BUSCFG, reg, MTK_NOR_BUS_MODE_MASK);
0351 }
0352 
0353 static int mtk_nor_dma_exec(struct mtk_nor *sp, u32 from, unsigned int length,
0354                 dma_addr_t dma_addr)
0355 {
0356     int ret = 0;
0357     ulong delay;
0358     u32 reg;
0359 
0360     writel(from, sp->base + MTK_NOR_REG_DMA_FADR);
0361     writel(dma_addr, sp->base + MTK_NOR_REG_DMA_DADR);
0362     writel(dma_addr + length, sp->base + MTK_NOR_REG_DMA_END_DADR);
0363 
0364     if (sp->high_dma) {
0365         writel(upper_32_bits(dma_addr),
0366                sp->base + MTK_NOR_REG_DMA_DADR_HB);
0367         writel(upper_32_bits(dma_addr + length),
0368                sp->base + MTK_NOR_REG_DMA_END_DADR_HB);
0369     }
0370 
0371     if (sp->has_irq) {
0372         reinit_completion(&sp->op_done);
0373         mtk_nor_rmw(sp, MTK_NOR_REG_IRQ_EN, MTK_NOR_IRQ_DMA, 0);
0374     }
0375 
0376     mtk_nor_rmw(sp, MTK_NOR_REG_DMA_CTL, MTK_NOR_DMA_START, 0);
0377 
0378     delay = CLK_TO_US(sp, (length + 5) * BITS_PER_BYTE);
0379 
0380     if (sp->has_irq) {
0381         if (!wait_for_completion_timeout(&sp->op_done,
0382                          (delay + 1) * 100))
0383             ret = -ETIMEDOUT;
0384     } else {
0385         ret = readl_poll_timeout(sp->base + MTK_NOR_REG_DMA_CTL, reg,
0386                      !(reg & MTK_NOR_DMA_START), delay / 3,
0387                      (delay + 1) * 100);
0388     }
0389 
0390     if (ret < 0)
0391         dev_err(sp->dev, "dma read timeout.\n");
0392 
0393     return ret;
0394 }
0395 
0396 static int mtk_nor_read_bounce(struct mtk_nor *sp, const struct spi_mem_op *op)
0397 {
0398     unsigned int rdlen;
0399     int ret;
0400 
0401     if (op->data.nbytes & MTK_NOR_DMA_ALIGN_MASK)
0402         rdlen = (op->data.nbytes + MTK_NOR_DMA_ALIGN) & ~MTK_NOR_DMA_ALIGN_MASK;
0403     else
0404         rdlen = op->data.nbytes;
0405 
0406     ret = mtk_nor_dma_exec(sp, op->addr.val, rdlen, sp->buffer_dma);
0407 
0408     if (!ret)
0409         memcpy(op->data.buf.in, sp->buffer, op->data.nbytes);
0410 
0411     return ret;
0412 }
0413 
0414 static int mtk_nor_read_dma(struct mtk_nor *sp, const struct spi_mem_op *op)
0415 {
0416     int ret;
0417     dma_addr_t dma_addr;
0418 
0419     if (need_bounce(sp, op))
0420         return mtk_nor_read_bounce(sp, op);
0421 
0422     dma_addr = dma_map_single(sp->dev, op->data.buf.in,
0423                   op->data.nbytes, DMA_FROM_DEVICE);
0424 
0425     if (dma_mapping_error(sp->dev, dma_addr))
0426         return -EINVAL;
0427 
0428     ret = mtk_nor_dma_exec(sp, op->addr.val, op->data.nbytes, dma_addr);
0429 
0430     dma_unmap_single(sp->dev, dma_addr, op->data.nbytes, DMA_FROM_DEVICE);
0431 
0432     return ret;
0433 }
0434 
0435 static int mtk_nor_read_pio(struct mtk_nor *sp, const struct spi_mem_op *op)
0436 {
0437     u8 *buf = op->data.buf.in;
0438     int ret;
0439 
0440     ret = mtk_nor_cmd_exec(sp, MTK_NOR_CMD_READ, 6 * BITS_PER_BYTE);
0441     if (!ret)
0442         buf[0] = readb(sp->base + MTK_NOR_REG_RDATA);
0443     return ret;
0444 }
0445 
0446 static int mtk_nor_write_buffer_enable(struct mtk_nor *sp)
0447 {
0448     int ret;
0449     u32 val;
0450 
0451     if (sp->wbuf_en)
0452         return 0;
0453 
0454     val = readl(sp->base + MTK_NOR_REG_CFG2);
0455     writel(val | MTK_NOR_WR_BUF_EN, sp->base + MTK_NOR_REG_CFG2);
0456     ret = readl_poll_timeout(sp->base + MTK_NOR_REG_CFG2, val,
0457                  val & MTK_NOR_WR_BUF_EN, 0, 10000);
0458     if (!ret)
0459         sp->wbuf_en = true;
0460     return ret;
0461 }
0462 
0463 static int mtk_nor_write_buffer_disable(struct mtk_nor *sp)
0464 {
0465     int ret;
0466     u32 val;
0467 
0468     if (!sp->wbuf_en)
0469         return 0;
0470     val = readl(sp->base + MTK_NOR_REG_CFG2);
0471     writel(val & ~MTK_NOR_WR_BUF_EN, sp->base + MTK_NOR_REG_CFG2);
0472     ret = readl_poll_timeout(sp->base + MTK_NOR_REG_CFG2, val,
0473                  !(val & MTK_NOR_WR_BUF_EN), 0, 10000);
0474     if (!ret)
0475         sp->wbuf_en = false;
0476     return ret;
0477 }
0478 
0479 static int mtk_nor_pp_buffered(struct mtk_nor *sp, const struct spi_mem_op *op)
0480 {
0481     const u8 *buf = op->data.buf.out;
0482     u32 val;
0483     int ret, i;
0484 
0485     ret = mtk_nor_write_buffer_enable(sp);
0486     if (ret < 0)
0487         return ret;
0488 
0489     for (i = 0; i < op->data.nbytes; i += 4) {
0490         val = buf[i + 3] << 24 | buf[i + 2] << 16 | buf[i + 1] << 8 |
0491               buf[i];
0492         writel(val, sp->base + MTK_NOR_REG_PP_DATA);
0493     }
0494     return mtk_nor_cmd_exec(sp, MTK_NOR_CMD_WRITE,
0495                 (op->data.nbytes + 5) * BITS_PER_BYTE);
0496 }
0497 
0498 static int mtk_nor_pp_unbuffered(struct mtk_nor *sp,
0499                  const struct spi_mem_op *op)
0500 {
0501     const u8 *buf = op->data.buf.out;
0502     int ret;
0503 
0504     ret = mtk_nor_write_buffer_disable(sp);
0505     if (ret < 0)
0506         return ret;
0507     writeb(buf[0], sp->base + MTK_NOR_REG_WDATA);
0508     return mtk_nor_cmd_exec(sp, MTK_NOR_CMD_WRITE, 6 * BITS_PER_BYTE);
0509 }
0510 
0511 static int mtk_nor_spi_mem_prg(struct mtk_nor *sp, const struct spi_mem_op *op)
0512 {
0513     int rx_len = 0;
0514     int reg_offset = MTK_NOR_REG_PRGDATA_MAX;
0515     int tx_len, prg_len;
0516     int i, ret;
0517     void __iomem *reg;
0518     u8 bufbyte;
0519 
0520     tx_len = op->cmd.nbytes + op->addr.nbytes;
0521 
0522     // count dummy bytes only if we need to write data after it
0523     if (op->data.dir == SPI_MEM_DATA_OUT)
0524         tx_len += op->dummy.nbytes + op->data.nbytes;
0525     else if (op->data.dir == SPI_MEM_DATA_IN)
0526         rx_len = op->data.nbytes;
0527 
0528     prg_len = op->cmd.nbytes + op->addr.nbytes + op->dummy.nbytes +
0529           op->data.nbytes;
0530 
0531     // an invalid op may reach here if the caller calls exec_op without
0532     // adjust_op_size. return -EINVAL instead of -ENOTSUPP so that
0533     // spi-mem won't try this op again with generic spi transfers.
0534     if ((tx_len > MTK_NOR_REG_PRGDATA_MAX + 1) ||
0535         (rx_len > MTK_NOR_REG_SHIFT_MAX + 1) ||
0536         (prg_len > MTK_NOR_PRG_CNT_MAX / 8))
0537         return -EINVAL;
0538 
0539     // fill tx data
0540     for (i = op->cmd.nbytes; i > 0; i--, reg_offset--) {
0541         reg = sp->base + MTK_NOR_REG_PRGDATA(reg_offset);
0542         bufbyte = (op->cmd.opcode >> ((i - 1) * BITS_PER_BYTE)) & 0xff;
0543         writeb(bufbyte, reg);
0544     }
0545 
0546     for (i = op->addr.nbytes; i > 0; i--, reg_offset--) {
0547         reg = sp->base + MTK_NOR_REG_PRGDATA(reg_offset);
0548         bufbyte = (op->addr.val >> ((i - 1) * BITS_PER_BYTE)) & 0xff;
0549         writeb(bufbyte, reg);
0550     }
0551 
0552     if (op->data.dir == SPI_MEM_DATA_OUT) {
0553         for (i = 0; i < op->dummy.nbytes; i++, reg_offset--) {
0554             reg = sp->base + MTK_NOR_REG_PRGDATA(reg_offset);
0555             writeb(0, reg);
0556         }
0557 
0558         for (i = 0; i < op->data.nbytes; i++, reg_offset--) {
0559             reg = sp->base + MTK_NOR_REG_PRGDATA(reg_offset);
0560             writeb(((const u8 *)(op->data.buf.out))[i], reg);
0561         }
0562     }
0563 
0564     for (; reg_offset >= 0; reg_offset--) {
0565         reg = sp->base + MTK_NOR_REG_PRGDATA(reg_offset);
0566         writeb(0, reg);
0567     }
0568 
0569     // trigger op
0570     if (rx_len)
0571         writel(prg_len * BITS_PER_BYTE + sp->caps->extra_dummy_bit,
0572                sp->base + MTK_NOR_REG_PRG_CNT);
0573     else
0574         writel(prg_len * BITS_PER_BYTE, sp->base + MTK_NOR_REG_PRG_CNT);
0575 
0576     ret = mtk_nor_cmd_exec(sp, MTK_NOR_CMD_PROGRAM,
0577                    prg_len * BITS_PER_BYTE);
0578     if (ret)
0579         return ret;
0580 
0581     // fetch read data
0582     reg_offset = 0;
0583     if (op->data.dir == SPI_MEM_DATA_IN) {
0584         for (i = op->data.nbytes - 1; i >= 0; i--, reg_offset++) {
0585             reg = sp->base + MTK_NOR_REG_SHIFT(reg_offset);
0586             ((u8 *)(op->data.buf.in))[i] = readb(reg);
0587         }
0588     }
0589 
0590     return 0;
0591 }
0592 
0593 static int mtk_nor_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)
0594 {
0595     struct mtk_nor *sp = spi_controller_get_devdata(mem->spi->master);
0596     int ret;
0597 
0598     if ((op->data.nbytes == 0) ||
0599         ((op->addr.nbytes != 3) && (op->addr.nbytes != 4)))
0600         return mtk_nor_spi_mem_prg(sp, op);
0601 
0602     if (op->data.dir == SPI_MEM_DATA_OUT) {
0603         mtk_nor_set_addr(sp, op);
0604         writeb(op->cmd.opcode, sp->base + MTK_NOR_REG_PRGDATA0);
0605         if (op->data.nbytes == MTK_NOR_PP_SIZE)
0606             return mtk_nor_pp_buffered(sp, op);
0607         return mtk_nor_pp_unbuffered(sp, op);
0608     }
0609 
0610     if ((op->data.dir == SPI_MEM_DATA_IN) && mtk_nor_match_read(op)) {
0611         ret = mtk_nor_write_buffer_disable(sp);
0612         if (ret < 0)
0613             return ret;
0614         mtk_nor_setup_bus(sp, op);
0615         if (op->data.nbytes == 1) {
0616             mtk_nor_set_addr(sp, op);
0617             return mtk_nor_read_pio(sp, op);
0618         } else {
0619             return mtk_nor_read_dma(sp, op);
0620         }
0621     }
0622 
0623     return mtk_nor_spi_mem_prg(sp, op);
0624 }
0625 
0626 static int mtk_nor_setup(struct spi_device *spi)
0627 {
0628     struct mtk_nor *sp = spi_controller_get_devdata(spi->master);
0629 
0630     if (spi->max_speed_hz && (spi->max_speed_hz < sp->spi_freq)) {
0631         dev_err(&spi->dev, "spi clock should be %u Hz.\n",
0632             sp->spi_freq);
0633         return -EINVAL;
0634     }
0635     spi->max_speed_hz = sp->spi_freq;
0636 
0637     return 0;
0638 }
0639 
0640 static int mtk_nor_transfer_one_message(struct spi_controller *master,
0641                     struct spi_message *m)
0642 {
0643     struct mtk_nor *sp = spi_controller_get_devdata(master);
0644     struct spi_transfer *t = NULL;
0645     unsigned long trx_len = 0;
0646     int stat = 0;
0647     int reg_offset = MTK_NOR_REG_PRGDATA_MAX;
0648     void __iomem *reg;
0649     const u8 *txbuf;
0650     u8 *rxbuf;
0651     int i;
0652 
0653     list_for_each_entry(t, &m->transfers, transfer_list) {
0654         txbuf = t->tx_buf;
0655         for (i = 0; i < t->len; i++, reg_offset--) {
0656             reg = sp->base + MTK_NOR_REG_PRGDATA(reg_offset);
0657             if (txbuf)
0658                 writeb(txbuf[i], reg);
0659             else
0660                 writeb(0, reg);
0661         }
0662         trx_len += t->len;
0663     }
0664 
0665     writel(trx_len * BITS_PER_BYTE, sp->base + MTK_NOR_REG_PRG_CNT);
0666 
0667     stat = mtk_nor_cmd_exec(sp, MTK_NOR_CMD_PROGRAM,
0668                 trx_len * BITS_PER_BYTE);
0669     if (stat < 0)
0670         goto msg_done;
0671 
0672     reg_offset = trx_len - 1;
0673     list_for_each_entry(t, &m->transfers, transfer_list) {
0674         rxbuf = t->rx_buf;
0675         for (i = 0; i < t->len; i++, reg_offset--) {
0676             reg = sp->base + MTK_NOR_REG_SHIFT(reg_offset);
0677             if (rxbuf)
0678                 rxbuf[i] = readb(reg);
0679         }
0680     }
0681 
0682     m->actual_length = trx_len;
0683 msg_done:
0684     m->status = stat;
0685     spi_finalize_current_message(master);
0686 
0687     return 0;
0688 }
0689 
0690 static void mtk_nor_disable_clk(struct mtk_nor *sp)
0691 {
0692     clk_disable_unprepare(sp->spi_clk);
0693     clk_disable_unprepare(sp->ctlr_clk);
0694     clk_disable_unprepare(sp->axi_clk);
0695     clk_disable_unprepare(sp->axi_s_clk);
0696 }
0697 
0698 static int mtk_nor_enable_clk(struct mtk_nor *sp)
0699 {
0700     int ret;
0701 
0702     ret = clk_prepare_enable(sp->spi_clk);
0703     if (ret)
0704         return ret;
0705 
0706     ret = clk_prepare_enable(sp->ctlr_clk);
0707     if (ret) {
0708         clk_disable_unprepare(sp->spi_clk);
0709         return ret;
0710     }
0711 
0712     ret = clk_prepare_enable(sp->axi_clk);
0713     if (ret) {
0714         clk_disable_unprepare(sp->spi_clk);
0715         clk_disable_unprepare(sp->ctlr_clk);
0716         return ret;
0717     }
0718 
0719     ret = clk_prepare_enable(sp->axi_s_clk);
0720     if (ret) {
0721         clk_disable_unprepare(sp->spi_clk);
0722         clk_disable_unprepare(sp->ctlr_clk);
0723         clk_disable_unprepare(sp->axi_clk);
0724         return ret;
0725     }
0726 
0727     return 0;
0728 }
0729 
0730 static void mtk_nor_init(struct mtk_nor *sp)
0731 {
0732     writel(0, sp->base + MTK_NOR_REG_IRQ_EN);
0733     writel(MTK_NOR_IRQ_MASK, sp->base + MTK_NOR_REG_IRQ_STAT);
0734 
0735     writel(MTK_NOR_ENABLE_SF_CMD, sp->base + MTK_NOR_REG_WP);
0736     mtk_nor_rmw(sp, MTK_NOR_REG_CFG2, MTK_NOR_WR_CUSTOM_OP_EN, 0);
0737     mtk_nor_rmw(sp, MTK_NOR_REG_CFG3,
0738             MTK_NOR_DISABLE_WREN | MTK_NOR_DISABLE_SR_POLL, 0);
0739 }
0740 
0741 static irqreturn_t mtk_nor_irq_handler(int irq, void *data)
0742 {
0743     struct mtk_nor *sp = data;
0744     u32 irq_status, irq_enabled;
0745 
0746     irq_status = readl(sp->base + MTK_NOR_REG_IRQ_STAT);
0747     irq_enabled = readl(sp->base + MTK_NOR_REG_IRQ_EN);
0748     // write status back to clear interrupt
0749     writel(irq_status, sp->base + MTK_NOR_REG_IRQ_STAT);
0750 
0751     if (!(irq_status & irq_enabled))
0752         return IRQ_NONE;
0753 
0754     if (irq_status & MTK_NOR_IRQ_DMA) {
0755         complete(&sp->op_done);
0756         writel(0, sp->base + MTK_NOR_REG_IRQ_EN);
0757     }
0758 
0759     return IRQ_HANDLED;
0760 }
0761 
0762 static size_t mtk_max_msg_size(struct spi_device *spi)
0763 {
0764     return MTK_NOR_PRG_MAX_SIZE;
0765 }
0766 
0767 static const struct spi_controller_mem_ops mtk_nor_mem_ops = {
0768     .adjust_op_size = mtk_nor_adjust_op_size,
0769     .supports_op = mtk_nor_supports_op,
0770     .exec_op = mtk_nor_exec_op
0771 };
0772 
0773 static const struct mtk_nor_caps mtk_nor_caps_mt8173 = {
0774     .dma_bits = 32,
0775     .extra_dummy_bit = 0,
0776 };
0777 
0778 static const struct mtk_nor_caps mtk_nor_caps_mt8186 = {
0779     .dma_bits = 32,
0780     .extra_dummy_bit = 1,
0781 };
0782 
0783 static const struct mtk_nor_caps mtk_nor_caps_mt8192 = {
0784     .dma_bits = 36,
0785     .extra_dummy_bit = 0,
0786 };
0787 
0788 static const struct of_device_id mtk_nor_match[] = {
0789     { .compatible = "mediatek,mt8173-nor", .data = &mtk_nor_caps_mt8173 },
0790     { .compatible = "mediatek,mt8186-nor", .data = &mtk_nor_caps_mt8186 },
0791     { .compatible = "mediatek,mt8192-nor", .data = &mtk_nor_caps_mt8192 },
0792     { /* sentinel */ }
0793 };
0794 MODULE_DEVICE_TABLE(of, mtk_nor_match);
0795 
0796 static int mtk_nor_probe(struct platform_device *pdev)
0797 {
0798     struct spi_controller *ctlr;
0799     struct mtk_nor *sp;
0800     struct mtk_nor_caps *caps;
0801     void __iomem *base;
0802     struct clk *spi_clk, *ctlr_clk, *axi_clk, *axi_s_clk;
0803     int ret, irq;
0804 
0805     base = devm_platform_ioremap_resource(pdev, 0);
0806     if (IS_ERR(base))
0807         return PTR_ERR(base);
0808 
0809     spi_clk = devm_clk_get(&pdev->dev, "spi");
0810     if (IS_ERR(spi_clk))
0811         return PTR_ERR(spi_clk);
0812 
0813     ctlr_clk = devm_clk_get(&pdev->dev, "sf");
0814     if (IS_ERR(ctlr_clk))
0815         return PTR_ERR(ctlr_clk);
0816 
0817     axi_clk = devm_clk_get_optional(&pdev->dev, "axi");
0818     if (IS_ERR(axi_clk))
0819         return PTR_ERR(axi_clk);
0820 
0821     axi_s_clk = devm_clk_get_optional(&pdev->dev, "axi_s");
0822     if (IS_ERR(axi_s_clk))
0823         return PTR_ERR(axi_s_clk);
0824 
0825     caps = (struct mtk_nor_caps *)of_device_get_match_data(&pdev->dev);
0826 
0827     ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(caps->dma_bits));
0828     if (ret) {
0829         dev_err(&pdev->dev, "failed to set dma mask(%u)\n", caps->dma_bits);
0830         return ret;
0831     }
0832 
0833     ctlr = devm_spi_alloc_master(&pdev->dev, sizeof(*sp));
0834     if (!ctlr) {
0835         dev_err(&pdev->dev, "failed to allocate spi controller\n");
0836         return -ENOMEM;
0837     }
0838 
0839     ctlr->bits_per_word_mask = SPI_BPW_MASK(8);
0840     ctlr->dev.of_node = pdev->dev.of_node;
0841     ctlr->max_message_size = mtk_max_msg_size;
0842     ctlr->mem_ops = &mtk_nor_mem_ops;
0843     ctlr->mode_bits = SPI_RX_DUAL | SPI_RX_QUAD | SPI_TX_DUAL | SPI_TX_QUAD;
0844     ctlr->num_chipselect = 1;
0845     ctlr->setup = mtk_nor_setup;
0846     ctlr->transfer_one_message = mtk_nor_transfer_one_message;
0847     ctlr->auto_runtime_pm = true;
0848 
0849     dev_set_drvdata(&pdev->dev, ctlr);
0850 
0851     sp = spi_controller_get_devdata(ctlr);
0852     sp->base = base;
0853     sp->has_irq = false;
0854     sp->wbuf_en = false;
0855     sp->ctlr = ctlr;
0856     sp->dev = &pdev->dev;
0857     sp->spi_clk = spi_clk;
0858     sp->ctlr_clk = ctlr_clk;
0859     sp->axi_clk = axi_clk;
0860     sp->axi_s_clk = axi_s_clk;
0861     sp->caps = caps;
0862     sp->high_dma = caps->dma_bits > 32;
0863     sp->buffer = dmam_alloc_coherent(&pdev->dev,
0864                 MTK_NOR_BOUNCE_BUF_SIZE + MTK_NOR_DMA_ALIGN,
0865                 &sp->buffer_dma, GFP_KERNEL);
0866     if (!sp->buffer)
0867         return -ENOMEM;
0868 
0869     if ((uintptr_t)sp->buffer & MTK_NOR_DMA_ALIGN_MASK) {
0870         dev_err(sp->dev, "misaligned allocation of internal buffer.\n");
0871         return -ENOMEM;
0872     }
0873 
0874     ret = mtk_nor_enable_clk(sp);
0875     if (ret < 0)
0876         return ret;
0877 
0878     sp->spi_freq = clk_get_rate(sp->spi_clk);
0879 
0880     mtk_nor_init(sp);
0881 
0882     irq = platform_get_irq_optional(pdev, 0);
0883 
0884     if (irq < 0) {
0885         dev_warn(sp->dev, "IRQ not available.");
0886     } else {
0887         ret = devm_request_irq(sp->dev, irq, mtk_nor_irq_handler, 0,
0888                        pdev->name, sp);
0889         if (ret < 0) {
0890             dev_warn(sp->dev, "failed to request IRQ.");
0891         } else {
0892             init_completion(&sp->op_done);
0893             sp->has_irq = true;
0894         }
0895     }
0896 
0897     pm_runtime_set_autosuspend_delay(&pdev->dev, -1);
0898     pm_runtime_use_autosuspend(&pdev->dev);
0899     pm_runtime_set_active(&pdev->dev);
0900     pm_runtime_enable(&pdev->dev);
0901     pm_runtime_get_noresume(&pdev->dev);
0902 
0903     ret = devm_spi_register_controller(&pdev->dev, ctlr);
0904     if (ret < 0)
0905         goto err_probe;
0906 
0907     pm_runtime_mark_last_busy(&pdev->dev);
0908     pm_runtime_put_autosuspend(&pdev->dev);
0909 
0910     dev_info(&pdev->dev, "spi frequency: %d Hz\n", sp->spi_freq);
0911 
0912     return 0;
0913 
0914 err_probe:
0915     pm_runtime_disable(&pdev->dev);
0916     pm_runtime_set_suspended(&pdev->dev);
0917     pm_runtime_dont_use_autosuspend(&pdev->dev);
0918 
0919     mtk_nor_disable_clk(sp);
0920 
0921     return ret;
0922 }
0923 
0924 static int mtk_nor_remove(struct platform_device *pdev)
0925 {
0926     struct spi_controller *ctlr = dev_get_drvdata(&pdev->dev);
0927     struct mtk_nor *sp = spi_controller_get_devdata(ctlr);
0928 
0929     pm_runtime_disable(&pdev->dev);
0930     pm_runtime_set_suspended(&pdev->dev);
0931     pm_runtime_dont_use_autosuspend(&pdev->dev);
0932 
0933     mtk_nor_disable_clk(sp);
0934 
0935     return 0;
0936 }
0937 
0938 static int __maybe_unused mtk_nor_runtime_suspend(struct device *dev)
0939 {
0940     struct spi_controller *ctlr = dev_get_drvdata(dev);
0941     struct mtk_nor *sp = spi_controller_get_devdata(ctlr);
0942 
0943     mtk_nor_disable_clk(sp);
0944 
0945     return 0;
0946 }
0947 
0948 static int __maybe_unused mtk_nor_runtime_resume(struct device *dev)
0949 {
0950     struct spi_controller *ctlr = dev_get_drvdata(dev);
0951     struct mtk_nor *sp = spi_controller_get_devdata(ctlr);
0952 
0953     return mtk_nor_enable_clk(sp);
0954 }
0955 
0956 static int __maybe_unused mtk_nor_suspend(struct device *dev)
0957 {
0958     return pm_runtime_force_suspend(dev);
0959 }
0960 
0961 static int __maybe_unused mtk_nor_resume(struct device *dev)
0962 {
0963     struct spi_controller *ctlr = dev_get_drvdata(dev);
0964     struct mtk_nor *sp = spi_controller_get_devdata(ctlr);
0965     int ret;
0966 
0967     ret = pm_runtime_force_resume(dev);
0968     if (ret)
0969         return ret;
0970 
0971     mtk_nor_init(sp);
0972 
0973     return 0;
0974 }
0975 
0976 static const struct dev_pm_ops mtk_nor_pm_ops = {
0977     SET_RUNTIME_PM_OPS(mtk_nor_runtime_suspend,
0978                mtk_nor_runtime_resume, NULL)
0979     SET_SYSTEM_SLEEP_PM_OPS(mtk_nor_suspend, mtk_nor_resume)
0980 };
0981 
0982 static struct platform_driver mtk_nor_driver = {
0983     .driver = {
0984         .name = DRIVER_NAME,
0985         .of_match_table = mtk_nor_match,
0986         .pm = &mtk_nor_pm_ops,
0987     },
0988     .probe = mtk_nor_probe,
0989     .remove = mtk_nor_remove,
0990 };
0991 
0992 module_platform_driver(mtk_nor_driver);
0993 
0994 MODULE_DESCRIPTION("Mediatek SPI NOR controller driver");
0995 MODULE_AUTHOR("Chuanhong Guo <gch981213@gmail.com>");
0996 MODULE_LICENSE("GPL v2");
0997 MODULE_ALIAS("platform:" DRIVER_NAME);
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