drivers/spi/spi-mt7621.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 //
0003 // spi-mt7621.c -- MediaTek MT7621 SPI controller driver
0004 //
0005 // Copyright (C) 2011 Sergiy <piratfm@gmail.com>
0006 // Copyright (C) 2011-2013 Gabor Juhos <juhosg@openwrt.org>
0007 // Copyright (C) 2014-2015 Felix Fietkau <nbd@nbd.name>
0008 //
0009 // Some parts are based on spi-orion.c:
0010 //   Author: Shadi Ammouri <shadi@marvell.com>
0011 //   Copyright (C) 2007-2008 Marvell Ltd.
0012
0013 #include <linux/clk.h>
0014 #include <linux/delay.h>
0015 #include <linux/io.h>
0016 #include <linux/module.h>
0017 #include <linux/of_device.h>
0018 #include <linux/reset.h>
0019 #include <linux/spi/spi.h>
0020
0021 #define DRIVER_NAME     "spi-mt7621"
0022
0023 /* in usec */
0024 #define RALINK_SPI_WAIT_MAX_LOOP 2000
0025
0026 /* SPISTAT register bit field */
0027 #define SPISTAT_BUSY        BIT(0)
0028
0029 #define MT7621_SPI_TRANS    0x00
0030 #define SPITRANS_BUSY       BIT(16)
0031
0032 #define MT7621_SPI_OPCODE   0x04
0033 #define MT7621_SPI_DATA0    0x08
0034 #define MT7621_SPI_DATA4    0x18
0035 #define SPI_CTL_TX_RX_CNT_MASK  0xff
0036 #define SPI_CTL_START       BIT(8)
0037
0038 #define MT7621_SPI_MASTER   0x28
0039 #define MASTER_MORE_BUFMODE BIT(2)
0040 #define MASTER_FULL_DUPLEX  BIT(10)
0041 #define MASTER_RS_CLK_SEL   GENMASK(27, 16)
0042 #define MASTER_RS_CLK_SEL_SHIFT 16
0043 #define MASTER_RS_SLAVE_SEL GENMASK(31, 29)
0044
0045 #define MT7621_SPI_MOREBUF  0x2c
0046 #define MT7621_SPI_POLAR    0x38
0047 #define MT7621_SPI_SPACE    0x3c
0048
0049 #define MT7621_CPHA     BIT(5)
0050 #define MT7621_CPOL     BIT(4)
0051 #define MT7621_LSB_FIRST    BIT(3)
0052
0053 struct mt7621_spi {
0054     struct spi_controller   *master;
0055     void __iomem        *base;
0056     unsigned int        sys_freq;
0057     unsigned int        speed;
0058     struct clk      *clk;
0059     int         pending_write;
0060 };
0061
0062 static inline struct mt7621_spi *spidev_to_mt7621_spi(struct spi_device *spi)
0063 {
0064     return spi_controller_get_devdata(spi->master);
0065 }
0066
0067 static inline u32 mt7621_spi_read(struct mt7621_spi *rs, u32 reg)
0068 {
0069     return ioread32(rs->base + reg);
0070 }
0071
0072 static inline void mt7621_spi_write(struct mt7621_spi *rs, u32 reg, u32 val)
0073 {
0074     iowrite32(val, rs->base + reg);
0075 }
0076
0077 static void mt7621_spi_set_cs(struct spi_device *spi, int enable)
0078 {
0079     struct mt7621_spi *rs = spidev_to_mt7621_spi(spi);
0080     int cs = spi->chip_select;
0081     u32 polar = 0;
0082     u32 master;
0083
0084     /*
0085      * Select SPI device 7, enable "more buffer mode" and disable
0086      * full-duplex (only half-duplex really works on this chip
0087      * reliably)
0088      */
0089     master = mt7621_spi_read(rs, MT7621_SPI_MASTER);
0090     master |= MASTER_RS_SLAVE_SEL | MASTER_MORE_BUFMODE;
0091     master &= ~MASTER_FULL_DUPLEX;
0092     mt7621_spi_write(rs, MT7621_SPI_MASTER, master);
0093
0094     rs->pending_write = 0;
0095
0096     if (enable)
0097         polar = BIT(cs);
0098     mt7621_spi_write(rs, MT7621_SPI_POLAR, polar);
0099 }
0100
0101 static int mt7621_spi_prepare(struct spi_device *spi, unsigned int speed)
0102 {
0103     struct mt7621_spi *rs = spidev_to_mt7621_spi(spi);
0104     u32 rate;
0105     u32 reg;
0106
0107     dev_dbg(&spi->dev, "speed:%u\n", speed);
0108
0109     rate = DIV_ROUND_UP(rs->sys_freq, speed);
0110     dev_dbg(&spi->dev, "rate-1:%u\n", rate);
0111
0112     if (rate > 4097)
0113         return -EINVAL;
0114
0115     if (rate < 2)
0116         rate = 2;
0117
0118     reg = mt7621_spi_read(rs, MT7621_SPI_MASTER);
0119     reg &= ~MASTER_RS_CLK_SEL;
0120     reg |= (rate - 2) << MASTER_RS_CLK_SEL_SHIFT;
0121     rs->speed = speed;
0122
0123     reg &= ~MT7621_LSB_FIRST;
0124     if (spi->mode & SPI_LSB_FIRST)
0125         reg |= MT7621_LSB_FIRST;
0126
0127     /*
0128      * This SPI controller seems to be tested on SPI flash only and some
0129      * bits are swizzled under other SPI modes probably due to incorrect
0130      * wiring inside the silicon. Only mode 0 works correctly.
0131      */
0132     reg &= ~(MT7621_CPHA | MT7621_CPOL);
0133
0134     mt7621_spi_write(rs, MT7621_SPI_MASTER, reg);
0135
0136     return 0;
0137 }
0138
0139 static inline int mt7621_spi_wait_till_ready(struct mt7621_spi *rs)
0140 {
0141     int i;
0142
0143     for (i = 0; i < RALINK_SPI_WAIT_MAX_LOOP; i++) {
0144         u32 status;
0145
0146         status = mt7621_spi_read(rs, MT7621_SPI_TRANS);
0147         if ((status & SPITRANS_BUSY) == 0)
0148             return 0;
0149         cpu_relax();
0150         udelay(1);
0151     }
0152
0153     return -ETIMEDOUT;
0154 }
0155
0156 static void mt7621_spi_read_half_duplex(struct mt7621_spi *rs,
0157                     int rx_len, u8 *buf)
0158 {
0159     int tx_len;
0160
0161     /*
0162      * Combine with any pending write, and perform one or more half-duplex
0163      * transactions reading 'len' bytes. Data to be written is already in
0164      * MT7621_SPI_DATA.
0165      */
0166     tx_len = rs->pending_write;
0167     rs->pending_write = 0;
0168
0169     while (rx_len || tx_len) {
0170         int i;
0171         u32 val = (min(tx_len, 4) * 8) << 24;
0172         int rx = min(rx_len, 32);
0173
0174         if (tx_len > 4)
0175             val |= (tx_len - 4) * 8;
0176         val |= (rx * 8) << 12;
0177         mt7621_spi_write(rs, MT7621_SPI_MOREBUF, val);
0178
0179         tx_len = 0;
0180
0181         val = mt7621_spi_read(rs, MT7621_SPI_TRANS);
0182         val |= SPI_CTL_START;
0183         mt7621_spi_write(rs, MT7621_SPI_TRANS, val);
0184
0185         mt7621_spi_wait_till_ready(rs);
0186
0187         for (i = 0; i < rx; i++) {
0188             if ((i % 4) == 0)
0189                 val = mt7621_spi_read(rs, MT7621_SPI_DATA0 + i);
0190             *buf++ = val & 0xff;
0191             val >>= 8;
0192         }
0193
0194         rx_len -= i;
0195     }
0196 }
0197
0198 static inline void mt7621_spi_flush(struct mt7621_spi *rs)
0199 {
0200     mt7621_spi_read_half_duplex(rs, 0, NULL);
0201 }
0202
0203 static void mt7621_spi_write_half_duplex(struct mt7621_spi *rs,
0204                      int tx_len, const u8 *buf)
0205 {
0206     int len = rs->pending_write;
0207     int val = 0;
0208
0209     if (len & 3) {
0210         val = mt7621_spi_read(rs, MT7621_SPI_OPCODE + (len & ~3));
0211         if (len < 4) {
0212             val <<= (4 - len) * 8;
0213             val = swab32(val);
0214         }
0215     }
0216
0217     while (tx_len > 0) {
0218         if (len >= 36) {
0219             rs->pending_write = len;
0220             mt7621_spi_flush(rs);
0221             len = 0;
0222         }
0223
0224         val |= *buf++ << (8 * (len & 3));
0225         len++;
0226         if ((len & 3) == 0) {
0227             if (len == 4)
0228                 /* The byte-order of the opcode is weird! */
0229                 val = swab32(val);
0230             mt7621_spi_write(rs, MT7621_SPI_OPCODE + len - 4, val);
0231             val = 0;
0232         }
0233         tx_len -= 1;
0234     }
0235
0236     if (len & 3) {
0237         if (len < 4) {
0238             val = swab32(val);
0239             val >>= (4 - len) * 8;
0240         }
0241         mt7621_spi_write(rs, MT7621_SPI_OPCODE + (len & ~3), val);
0242     }
0243
0244     rs->pending_write = len;
0245 }
0246
0247 static int mt7621_spi_transfer_one_message(struct spi_controller *master,
0248                        struct spi_message *m)
0249 {
0250     struct mt7621_spi *rs = spi_controller_get_devdata(master);
0251     struct spi_device *spi = m->spi;
0252     unsigned int speed = spi->max_speed_hz;
0253     struct spi_transfer *t = NULL;
0254     int status = 0;
0255
0256     mt7621_spi_wait_till_ready(rs);
0257
0258     list_for_each_entry(t, &m->transfers, transfer_list)
0259         if (t->speed_hz < speed)
0260             speed = t->speed_hz;
0261
0262     if (mt7621_spi_prepare(spi, speed)) {
0263         status = -EIO;
0264         goto msg_done;
0265     }
0266
0267     /* Assert CS */
0268     mt7621_spi_set_cs(spi, 1);
0269
0270     m->actual_length = 0;
0271     list_for_each_entry(t, &m->transfers, transfer_list) {
0272         if ((t->rx_buf) && (t->tx_buf)) {
0273             /*
0274              * This controller will shift some extra data out
0275              * of spi_opcode if (mosi_bit_cnt > 0) &&
0276              * (cmd_bit_cnt == 0). So the claimed full-duplex
0277              * support is broken since we have no way to read
0278              * the MISO value during that bit.
0279              */
0280             status = -EIO;
0281             goto msg_done;
0282         } else if (t->rx_buf) {
0283             mt7621_spi_read_half_duplex(rs, t->len, t->rx_buf);
0284         } else if (t->tx_buf) {
0285             mt7621_spi_write_half_duplex(rs, t->len, t->tx_buf);
0286         }
0287         m->actual_length += t->len;
0288     }
0289
0290     /* Flush data and deassert CS */
0291     mt7621_spi_flush(rs);
0292     mt7621_spi_set_cs(spi, 0);
0293
0294 msg_done:
0295     m->status = status;
0296     spi_finalize_current_message(master);
0297
0298     return 0;
0299 }
0300
0301 static int mt7621_spi_setup(struct spi_device *spi)
0302 {
0303     struct mt7621_spi *rs = spidev_to_mt7621_spi(spi);
0304
0305     if ((spi->max_speed_hz == 0) ||
0306         (spi->max_speed_hz > (rs->sys_freq / 2)))
0307         spi->max_speed_hz = rs->sys_freq / 2;
0308
0309     if (spi->max_speed_hz < (rs->sys_freq / 4097)) {
0310         dev_err(&spi->dev, "setup: requested speed is too low %d Hz\n",
0311             spi->max_speed_hz);
0312         return -EINVAL;
0313     }
0314
0315     return 0;
0316 }
0317
0318 static const struct of_device_id mt7621_spi_match[] = {
0319     { .compatible = "ralink,mt7621-spi" },
0320     {},
0321 };
0322 MODULE_DEVICE_TABLE(of, mt7621_spi_match);
0323
0324 static int mt7621_spi_probe(struct platform_device *pdev)
0325 {
0326     const struct of_device_id *match;
0327     struct spi_controller *master;
0328     struct mt7621_spi *rs;
0329     void __iomem *base;
0330     int status = 0;
0331     struct clk *clk;
0332     int ret;
0333
0334     match = of_match_device(mt7621_spi_match, &pdev->dev);
0335     if (!match)
0336         return -EINVAL;
0337
0338     base = devm_platform_ioremap_resource(pdev, 0);
0339     if (IS_ERR(base))
0340         return PTR_ERR(base);
0341
0342     clk = devm_clk_get(&pdev->dev, NULL);
0343     if (IS_ERR(clk)) {
0344         dev_err(&pdev->dev, "unable to get SYS clock, err=%d\n",
0345             status);
0346         return PTR_ERR(clk);
0347     }
0348
0349     status = clk_prepare_enable(clk);
0350     if (status)
0351         return status;
0352
0353     master = devm_spi_alloc_master(&pdev->dev, sizeof(*rs));
0354     if (!master) {
0355         dev_info(&pdev->dev, "master allocation failed\n");
0356         clk_disable_unprepare(clk);
0357         return -ENOMEM;
0358     }
0359
0360     master->mode_bits = SPI_LSB_FIRST;
0361     master->flags = SPI_CONTROLLER_HALF_DUPLEX;
0362     master->setup = mt7621_spi_setup;
0363     master->transfer_one_message = mt7621_spi_transfer_one_message;
0364     master->bits_per_word_mask = SPI_BPW_MASK(8);
0365     master->dev.of_node = pdev->dev.of_node;
0366     master->num_chipselect = 2;
0367
0368     dev_set_drvdata(&pdev->dev, master);
0369
0370     rs = spi_controller_get_devdata(master);
0371     rs->base = base;
0372     rs->clk = clk;
0373     rs->master = master;
0374     rs->sys_freq = clk_get_rate(rs->clk);
0375     rs->pending_write = 0;
0376     dev_info(&pdev->dev, "sys_freq: %u\n", rs->sys_freq);
0377
0378     ret = device_reset(&pdev->dev);
0379     if (ret) {
0380         dev_err(&pdev->dev, "SPI reset failed!\n");
0381         clk_disable_unprepare(clk);
0382         return ret;
0383     }
0384
0385     ret = spi_register_controller(master);
0386     if (ret)
0387         clk_disable_unprepare(clk);
0388
0389     return ret;
0390 }
0391
0392 static int mt7621_spi_remove(struct platform_device *pdev)
0393 {
0394     struct spi_controller *master;
0395     struct mt7621_spi *rs;
0396
0397     master = dev_get_drvdata(&pdev->dev);
0398     rs = spi_controller_get_devdata(master);
0399
0400     spi_unregister_controller(master);
0401     clk_disable_unprepare(rs->clk);
0402
0403     return 0;
0404 }
0405
0406 MODULE_ALIAS("platform:" DRIVER_NAME);
0407
0408 static struct platform_driver mt7621_spi_driver = {
0409     .driver = {
0410         .name = DRIVER_NAME,
0411         .of_match_table = mt7621_spi_match,
0412     },
0413     .probe = mt7621_spi_probe,
0414     .remove = mt7621_spi_remove,
0415 };
0416
0417 module_platform_driver(mt7621_spi_driver);
0418
0419 MODULE_DESCRIPTION("MT7621 SPI driver");
0420 MODULE_AUTHOR("Felix Fietkau <nbd@nbd.name>");
0421 MODULE_LICENSE("GPL");