drivers/spi/spi-mpc52xx.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * MPC52xx SPI bus driver.
0004  *
0005  * Copyright (C) 2008 Secret Lab Technologies Ltd.
0006  *
0007  * This is the driver for the MPC5200's dedicated SPI controller.
0008  *
0009  * Note: this driver does not support the MPC5200 PSC in SPI mode.  For
0010  * that driver see drivers/spi/mpc52xx_psc_spi.c
0011  */
0012
0013 #include <linux/module.h>
0014 #include <linux/errno.h>
0015 #include <linux/of_platform.h>
0016 #include <linux/interrupt.h>
0017 #include <linux/delay.h>
0018 #include <linux/spi/spi.h>
0019 #include <linux/io.h>
0020 #include <linux/of_gpio.h>
0021 #include <linux/slab.h>
0022 #include <linux/of_address.h>
0023 #include <linux/of_irq.h>
0024
0025 #include <asm/time.h>
0026 #include <asm/mpc52xx.h>
0027
0028 MODULE_AUTHOR("Grant Likely <grant.likely@secretlab.ca>");
0029 MODULE_DESCRIPTION("MPC52xx SPI (non-PSC) Driver");
0030 MODULE_LICENSE("GPL");
0031
0032 /* Register offsets */
0033 #define SPI_CTRL1   0x00
0034 #define SPI_CTRL1_SPIE      (1 << 7)
0035 #define SPI_CTRL1_SPE       (1 << 6)
0036 #define SPI_CTRL1_MSTR      (1 << 4)
0037 #define SPI_CTRL1_CPOL      (1 << 3)
0038 #define SPI_CTRL1_CPHA      (1 << 2)
0039 #define SPI_CTRL1_SSOE      (1 << 1)
0040 #define SPI_CTRL1_LSBFE     (1 << 0)
0041
0042 #define SPI_CTRL2   0x01
0043 #define SPI_BRR     0x04
0044
0045 #define SPI_STATUS  0x05
0046 #define SPI_STATUS_SPIF     (1 << 7)
0047 #define SPI_STATUS_WCOL     (1 << 6)
0048 #define SPI_STATUS_MODF     (1 << 4)
0049
0050 #define SPI_DATA    0x09
0051 #define SPI_PORTDATA    0x0d
0052 #define SPI_DATADIR 0x10
0053
0054 /* FSM state return values */
0055 #define FSM_STOP    0   /* Nothing more for the state machine to */
0056                 /* do.  If something interesting happens */
0057                 /* then an IRQ will be received */
0058 #define FSM_POLL    1   /* need to poll for completion, an IRQ is */
0059                 /* not expected */
0060 #define FSM_CONTINUE    2   /* Keep iterating the state machine */
0061
0062 /* Driver internal data */
0063 struct mpc52xx_spi {
0064     struct spi_master *master;
0065     void __iomem *regs;
0066     int irq0;   /* MODF irq */
0067     int irq1;   /* SPIF irq */
0068     unsigned int ipb_freq;
0069
0070     /* Statistics; not used now, but will be reintroduced for debugfs */
0071     int msg_count;
0072     int wcol_count;
0073     int wcol_ticks;
0074     u32 wcol_tx_timestamp;
0075     int modf_count;
0076     int byte_count;
0077
0078     struct list_head queue;     /* queue of pending messages */
0079     spinlock_t lock;
0080     struct work_struct work;
0081
0082     /* Details of current transfer (length, and buffer pointers) */
0083     struct spi_message *message;    /* current message */
0084     struct spi_transfer *transfer;  /* current transfer */
0085     int (*state)(int irq, struct mpc52xx_spi *ms, u8 status, u8 data);
0086     int len;
0087     int timestamp;
0088     u8 *rx_buf;
0089     const u8 *tx_buf;
0090     int cs_change;
0091     int gpio_cs_count;
0092     unsigned int *gpio_cs;
0093 };
0094
0095 /*
0096  * CS control function
0097  */
0098 static void mpc52xx_spi_chipsel(struct mpc52xx_spi *ms, int value)
0099 {
0100     int cs;
0101
0102     if (ms->gpio_cs_count > 0) {
0103         cs = ms->message->spi->chip_select;
0104         gpio_set_value(ms->gpio_cs[cs], value ? 0 : 1);
0105     } else
0106         out_8(ms->regs + SPI_PORTDATA, value ? 0 : 0x08);
0107 }
0108
0109 /*
0110  * Start a new transfer.  This is called both by the idle state
0111  * for the first transfer in a message, and by the wait state when the
0112  * previous transfer in a message is complete.
0113  */
0114 static void mpc52xx_spi_start_transfer(struct mpc52xx_spi *ms)
0115 {
0116     ms->rx_buf = ms->transfer->rx_buf;
0117     ms->tx_buf = ms->transfer->tx_buf;
0118     ms->len = ms->transfer->len;
0119
0120     /* Activate the chip select */
0121     if (ms->cs_change)
0122         mpc52xx_spi_chipsel(ms, 1);
0123     ms->cs_change = ms->transfer->cs_change;
0124
0125     /* Write out the first byte */
0126     ms->wcol_tx_timestamp = mftb();
0127     if (ms->tx_buf)
0128         out_8(ms->regs + SPI_DATA, *ms->tx_buf++);
0129     else
0130         out_8(ms->regs + SPI_DATA, 0);
0131 }
0132
0133 /* Forward declaration of state handlers */
0134 static int mpc52xx_spi_fsmstate_transfer(int irq, struct mpc52xx_spi *ms,
0135                      u8 status, u8 data);
0136 static int mpc52xx_spi_fsmstate_wait(int irq, struct mpc52xx_spi *ms,
0137                      u8 status, u8 data);
0138
0139 /*
0140  * IDLE state
0141  *
0142  * No transfers are in progress; if another transfer is pending then retrieve
0143  * it and kick it off.  Otherwise, stop processing the state machine
0144  */
0145 static int
0146 mpc52xx_spi_fsmstate_idle(int irq, struct mpc52xx_spi *ms, u8 status, u8 data)
0147 {
0148     struct spi_device *spi;
0149     int spr, sppr;
0150     u8 ctrl1;
0151
0152     if (status && (irq != NO_IRQ))
0153         dev_err(&ms->master->dev, "spurious irq, status=0x%.2x\n",
0154             status);
0155
0156     /* Check if there is another transfer waiting. */
0157     if (list_empty(&ms->queue))
0158         return FSM_STOP;
0159
0160     /* get the head of the queue */
0161     ms->message = list_first_entry(&ms->queue, struct spi_message, queue);
0162     list_del_init(&ms->message->queue);
0163
0164     /* Setup the controller parameters */
0165     ctrl1 = SPI_CTRL1_SPIE | SPI_CTRL1_SPE | SPI_CTRL1_MSTR;
0166     spi = ms->message->spi;
0167     if (spi->mode & SPI_CPHA)
0168         ctrl1 |= SPI_CTRL1_CPHA;
0169     if (spi->mode & SPI_CPOL)
0170         ctrl1 |= SPI_CTRL1_CPOL;
0171     if (spi->mode & SPI_LSB_FIRST)
0172         ctrl1 |= SPI_CTRL1_LSBFE;
0173     out_8(ms->regs + SPI_CTRL1, ctrl1);
0174
0175     /* Setup the controller speed */
0176     /* minimum divider is '2'.  Also, add '1' to force rounding the
0177      * divider up. */
0178     sppr = ((ms->ipb_freq / ms->message->spi->max_speed_hz) + 1) >> 1;
0179     spr = 0;
0180     if (sppr < 1)
0181         sppr = 1;
0182     while (((sppr - 1) & ~0x7) != 0) {
0183         sppr = (sppr + 1) >> 1; /* add '1' to force rounding up */
0184         spr++;
0185     }
0186     sppr--;     /* sppr quantity in register is offset by 1 */
0187     if (spr > 7) {
0188         /* Don't overrun limits of SPI baudrate register */
0189         spr = 7;
0190         sppr = 7;
0191     }
0192     out_8(ms->regs + SPI_BRR, sppr << 4 | spr); /* Set speed */
0193
0194     ms->cs_change = 1;
0195     ms->transfer = container_of(ms->message->transfers.next,
0196                     struct spi_transfer, transfer_list);
0197
0198     mpc52xx_spi_start_transfer(ms);
0199     ms->state = mpc52xx_spi_fsmstate_transfer;
0200
0201     return FSM_CONTINUE;
0202 }
0203
0204 /*
0205  * TRANSFER state
0206  *
0207  * In the middle of a transfer.  If the SPI core has completed processing
0208  * a byte, then read out the received data and write out the next byte
0209  * (unless this transfer is finished; in which case go on to the wait
0210  * state)
0211  */
0212 static int mpc52xx_spi_fsmstate_transfer(int irq, struct mpc52xx_spi *ms,
0213                      u8 status, u8 data)
0214 {
0215     if (!status)
0216         return ms->irq0 ? FSM_STOP : FSM_POLL;
0217
0218     if (status & SPI_STATUS_WCOL) {
0219         /* The SPI controller is stoopid.  At slower speeds, it may
0220          * raise the SPIF flag before the state machine is actually
0221          * finished, which causes a collision (internal to the state
0222          * machine only).  The manual recommends inserting a delay
0223          * between receiving the interrupt and sending the next byte,
0224          * but it can also be worked around simply by retrying the
0225          * transfer which is what we do here. */
0226         ms->wcol_count++;
0227         ms->wcol_ticks += mftb() - ms->wcol_tx_timestamp;
0228         ms->wcol_tx_timestamp = mftb();
0229         data = 0;
0230         if (ms->tx_buf)
0231             data = *(ms->tx_buf - 1);
0232         out_8(ms->regs + SPI_DATA, data); /* try again */
0233         return FSM_CONTINUE;
0234     } else if (status & SPI_STATUS_MODF) {
0235         ms->modf_count++;
0236         dev_err(&ms->master->dev, "mode fault\n");
0237         mpc52xx_spi_chipsel(ms, 0);
0238         ms->message->status = -EIO;
0239         if (ms->message->complete)
0240             ms->message->complete(ms->message->context);
0241         ms->state = mpc52xx_spi_fsmstate_idle;
0242         return FSM_CONTINUE;
0243     }
0244
0245     /* Read data out of the spi device */
0246     ms->byte_count++;
0247     if (ms->rx_buf)
0248         *ms->rx_buf++ = data;
0249
0250     /* Is the transfer complete? */
0251     ms->len--;
0252     if (ms->len == 0) {
0253         ms->timestamp = mftb();
0254         if (ms->transfer->delay.unit == SPI_DELAY_UNIT_USECS)
0255             ms->timestamp += ms->transfer->delay.value *
0256                      tb_ticks_per_usec;
0257         ms->state = mpc52xx_spi_fsmstate_wait;
0258         return FSM_CONTINUE;
0259     }
0260
0261     /* Write out the next byte */
0262     ms->wcol_tx_timestamp = mftb();
0263     if (ms->tx_buf)
0264         out_8(ms->regs + SPI_DATA, *ms->tx_buf++);
0265     else
0266         out_8(ms->regs + SPI_DATA, 0);
0267
0268     return FSM_CONTINUE;
0269 }
0270
0271 /*
0272  * WAIT state
0273  *
0274  * A transfer has completed; need to wait for the delay period to complete
0275  * before starting the next transfer
0276  */
0277 static int
0278 mpc52xx_spi_fsmstate_wait(int irq, struct mpc52xx_spi *ms, u8 status, u8 data)
0279 {
0280     if (status && irq)
0281         dev_err(&ms->master->dev, "spurious irq, status=0x%.2x\n",
0282             status);
0283
0284     if (((int)mftb()) - ms->timestamp < 0)
0285         return FSM_POLL;
0286
0287     ms->message->actual_length += ms->transfer->len;
0288
0289     /* Check if there is another transfer in this message.  If there
0290      * aren't then deactivate CS, notify sender, and drop back to idle
0291      * to start the next message. */
0292     if (ms->transfer->transfer_list.next == &ms->message->transfers) {
0293         ms->msg_count++;
0294         mpc52xx_spi_chipsel(ms, 0);
0295         ms->message->status = 0;
0296         if (ms->message->complete)
0297             ms->message->complete(ms->message->context);
0298         ms->state = mpc52xx_spi_fsmstate_idle;
0299         return FSM_CONTINUE;
0300     }
0301
0302     /* There is another transfer; kick it off */
0303
0304     if (ms->cs_change)
0305         mpc52xx_spi_chipsel(ms, 0);
0306
0307     ms->transfer = container_of(ms->transfer->transfer_list.next,
0308                     struct spi_transfer, transfer_list);
0309     mpc52xx_spi_start_transfer(ms);
0310     ms->state = mpc52xx_spi_fsmstate_transfer;
0311     return FSM_CONTINUE;
0312 }
0313
0314 /**
0315  * mpc52xx_spi_fsm_process - Finite State Machine iteration function
0316  * @irq: irq number that triggered the FSM or 0 for polling
0317  * @ms: pointer to mpc52xx_spi driver data
0318  */
0319 static void mpc52xx_spi_fsm_process(int irq, struct mpc52xx_spi *ms)
0320 {
0321     int rc = FSM_CONTINUE;
0322     u8 status, data;
0323
0324     while (rc == FSM_CONTINUE) {
0325         /* Interrupt cleared by read of STATUS followed by
0326          * read of DATA registers */
0327         status = in_8(ms->regs + SPI_STATUS);
0328         data = in_8(ms->regs + SPI_DATA);
0329         rc = ms->state(irq, ms, status, data);
0330     }
0331
0332     if (rc == FSM_POLL)
0333         schedule_work(&ms->work);
0334 }
0335
0336 /**
0337  * mpc52xx_spi_irq - IRQ handler
0338  */
0339 static irqreturn_t mpc52xx_spi_irq(int irq, void *_ms)
0340 {
0341     struct mpc52xx_spi *ms = _ms;
0342     spin_lock(&ms->lock);
0343     mpc52xx_spi_fsm_process(irq, ms);
0344     spin_unlock(&ms->lock);
0345     return IRQ_HANDLED;
0346 }
0347
0348 /**
0349  * mpc52xx_spi_wq - Workqueue function for polling the state machine
0350  */
0351 static void mpc52xx_spi_wq(struct work_struct *work)
0352 {
0353     struct mpc52xx_spi *ms = container_of(work, struct mpc52xx_spi, work);
0354     unsigned long flags;
0355
0356     spin_lock_irqsave(&ms->lock, flags);
0357     mpc52xx_spi_fsm_process(0, ms);
0358     spin_unlock_irqrestore(&ms->lock, flags);
0359 }
0360
0361 /*
0362  * spi_master ops
0363  */
0364
0365 static int mpc52xx_spi_transfer(struct spi_device *spi, struct spi_message *m)
0366 {
0367     struct mpc52xx_spi *ms = spi_master_get_devdata(spi->master);
0368     unsigned long flags;
0369
0370     m->actual_length = 0;
0371     m->status = -EINPROGRESS;
0372
0373     spin_lock_irqsave(&ms->lock, flags);
0374     list_add_tail(&m->queue, &ms->queue);
0375     spin_unlock_irqrestore(&ms->lock, flags);
0376     schedule_work(&ms->work);
0377
0378     return 0;
0379 }
0380
0381 /*
0382  * OF Platform Bus Binding
0383  */
0384 static int mpc52xx_spi_probe(struct platform_device *op)
0385 {
0386     struct spi_master *master;
0387     struct mpc52xx_spi *ms;
0388     void __iomem *regs;
0389     u8 ctrl1;
0390     int rc, i = 0;
0391     int gpio_cs;
0392
0393     /* MMIO registers */
0394     dev_dbg(&op->dev, "probing mpc5200 SPI device\n");
0395     regs = of_iomap(op->dev.of_node, 0);
0396     if (!regs)
0397         return -ENODEV;
0398
0399     /* initialize the device */
0400     ctrl1 = SPI_CTRL1_SPIE | SPI_CTRL1_SPE | SPI_CTRL1_MSTR;
0401     out_8(regs + SPI_CTRL1, ctrl1);
0402     out_8(regs + SPI_CTRL2, 0x0);
0403     out_8(regs + SPI_DATADIR, 0xe); /* Set output pins */
0404     out_8(regs + SPI_PORTDATA, 0x8);    /* Deassert /SS signal */
0405
0406     /* Clear the status register and re-read it to check for a MODF
0407      * failure.  This driver cannot currently handle multiple masters
0408      * on the SPI bus.  This fault will also occur if the SPI signals
0409      * are not connected to any pins (port_config setting) */
0410     in_8(regs + SPI_STATUS);
0411     out_8(regs + SPI_CTRL1, ctrl1);
0412
0413     in_8(regs + SPI_DATA);
0414     if (in_8(regs + SPI_STATUS) & SPI_STATUS_MODF) {
0415         dev_err(&op->dev, "mode fault; is port_config correct?\n");
0416         rc = -EIO;
0417         goto err_init;
0418     }
0419
0420     dev_dbg(&op->dev, "allocating spi_master struct\n");
0421     master = spi_alloc_master(&op->dev, sizeof(*ms));
0422     if (!master) {
0423         rc = -ENOMEM;
0424         goto err_alloc;
0425     }
0426
0427     master->transfer = mpc52xx_spi_transfer;
0428     master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST;
0429     master->bits_per_word_mask = SPI_BPW_MASK(8);
0430     master->dev.of_node = op->dev.of_node;
0431
0432     platform_set_drvdata(op, master);
0433
0434     ms = spi_master_get_devdata(master);
0435     ms->master = master;
0436     ms->regs = regs;
0437     ms->irq0 = irq_of_parse_and_map(op->dev.of_node, 0);
0438     ms->irq1 = irq_of_parse_and_map(op->dev.of_node, 1);
0439     ms->state = mpc52xx_spi_fsmstate_idle;
0440     ms->ipb_freq = mpc5xxx_get_bus_frequency(&op->dev);
0441     ms->gpio_cs_count = of_gpio_count(op->dev.of_node);
0442     if (ms->gpio_cs_count > 0) {
0443         master->num_chipselect = ms->gpio_cs_count;
0444         ms->gpio_cs = kmalloc_array(ms->gpio_cs_count,
0445                         sizeof(*ms->gpio_cs),
0446                         GFP_KERNEL);
0447         if (!ms->gpio_cs) {
0448             rc = -ENOMEM;
0449             goto err_alloc_gpio;
0450         }
0451
0452         for (i = 0; i < ms->gpio_cs_count; i++) {
0453             gpio_cs = of_get_gpio(op->dev.of_node, i);
0454             if (!gpio_is_valid(gpio_cs)) {
0455                 dev_err(&op->dev,
0456                     "could not parse the gpio field in oftree\n");
0457                 rc = -ENODEV;
0458                 goto err_gpio;
0459             }
0460
0461             rc = gpio_request(gpio_cs, dev_name(&op->dev));
0462             if (rc) {
0463                 dev_err(&op->dev,
0464                     "can't request spi cs gpio #%d on gpio line %d\n",
0465                     i, gpio_cs);
0466                 goto err_gpio;
0467             }
0468
0469             gpio_direction_output(gpio_cs, 1);
0470             ms->gpio_cs[i] = gpio_cs;
0471         }
0472     }
0473
0474     spin_lock_init(&ms->lock);
0475     INIT_LIST_HEAD(&ms->queue);
0476     INIT_WORK(&ms->work, mpc52xx_spi_wq);
0477
0478     /* Decide if interrupts can be used */
0479     if (ms->irq0 && ms->irq1) {
0480         rc = request_irq(ms->irq0, mpc52xx_spi_irq, 0,
0481                   "mpc5200-spi-modf", ms);
0482         rc |= request_irq(ms->irq1, mpc52xx_spi_irq, 0,
0483                   "mpc5200-spi-spif", ms);
0484         if (rc) {
0485             free_irq(ms->irq0, ms);
0486             free_irq(ms->irq1, ms);
0487             ms->irq0 = ms->irq1 = 0;
0488         }
0489     } else {
0490         /* operate in polled mode */
0491         ms->irq0 = ms->irq1 = 0;
0492     }
0493
0494     if (!ms->irq0)
0495         dev_info(&op->dev, "using polled mode\n");
0496
0497     dev_dbg(&op->dev, "registering spi_master struct\n");
0498     rc = spi_register_master(master);
0499     if (rc)
0500         goto err_register;
0501
0502     dev_info(&ms->master->dev, "registered MPC5200 SPI bus\n");
0503
0504     return rc;
0505
0506  err_register:
0507     dev_err(&ms->master->dev, "initialization failed\n");
0508  err_gpio:
0509     while (i-- > 0)
0510         gpio_free(ms->gpio_cs[i]);
0511
0512     kfree(ms->gpio_cs);
0513  err_alloc_gpio:
0514     spi_master_put(master);
0515  err_alloc:
0516  err_init:
0517     iounmap(regs);
0518     return rc;
0519 }
0520
0521 static int mpc52xx_spi_remove(struct platform_device *op)
0522 {
0523     struct spi_master *master = spi_master_get(platform_get_drvdata(op));
0524     struct mpc52xx_spi *ms = spi_master_get_devdata(master);
0525     int i;
0526
0527     free_irq(ms->irq0, ms);
0528     free_irq(ms->irq1, ms);
0529
0530     for (i = 0; i < ms->gpio_cs_count; i++)
0531         gpio_free(ms->gpio_cs[i]);
0532
0533     kfree(ms->gpio_cs);
0534     spi_unregister_master(master);
0535     iounmap(ms->regs);
0536     spi_master_put(master);
0537
0538     return 0;
0539 }
0540
0541 static const struct of_device_id mpc52xx_spi_match[] = {
0542     { .compatible = "fsl,mpc5200-spi", },
0543     {}
0544 };
0545 MODULE_DEVICE_TABLE(of, mpc52xx_spi_match);
0546
0547 static struct platform_driver mpc52xx_spi_of_driver = {
0548     .driver = {
0549         .name = "mpc52xx-spi",
0550         .of_match_table = mpc52xx_spi_match,
0551     },
0552     .probe = mpc52xx_spi_probe,
0553     .remove = mpc52xx_spi_remove,
0554 };
0555 module_platform_driver(mpc52xx_spi_of_driver);